Datasheet

MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
17Maxim Integrated
Figure 4. I
2
C Single Register Write Sequence
I
2
C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5813/MAX5814/MAX5815 use to hand-
shake receipt of each byte of data as shown in Figure 3.
The MAX5813/MAX5814/MAX5815 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccess-
ful data transfer, the bus master will retry communication.
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5813/MAX5814/MAX5815. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5813/MAX5814/
MAX5815, followed by a STOP condition.
I
2
C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitch-
ing or digital feedthrough to the DACs while the interface
is active.
I
2
C Write Operations
A master device communicates with the MAX5813/
MAX5814/MAX5815 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed
by an acknowledge clock (ACK) pulse as shown in the
Figure 4 and Figure 5. The first byte contains the address
of the MAX5813/MAX5814/MAX5815 with R/W = 0 to
indicate a write. The second byte contains the register
(or command) to be written and the third and fourth bytes
contain the data to be written. By repeating the register
address plus data pairs (Byte #2 through Byte #4 in
Figure 4 and Figure 5), the user can perform multiple
register writes using a single I
2
C command sequence.
There is no limit as to how many registers the user can
write with a single command. The MAX5813/MAX5814/
MAX5815 support this capability for all user-accessible
write mode commands.
SCL
AW 20 19 18 17 A16 15 14 13 12 11 10 9A8
START
SDA
WRITE ADDRESS
BYTE #1: I
2
C SLAVE ADDRESS*
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
212223
STOP
7 6 5 4 3 2 1 A0
ACK. GENERATED BY MAX5813/MAX5814/MAX5815
COMMAND EXECUTED
*I
2
C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
A3 A2 A1 A0100
A