Datasheet

MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
6Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Voltage (Note 11) V
IL
2.2V < V
DDIO
< 5.5V
0.3 x
V
DDIO
V
1.8V < V
DDIO
< 2.2V
0.2 x
V
DDIO
Hysteresis Voltage V
H
0.15 V
Input Leakage Current I
IN
V
IN
= 0V or V
DDIO
(Note 11) Q0.1 Q1 FA
Input Capacitance (Note 10) C
IN
3 pF
ADDR_ Pullup/Pulldown Strength R
PU
, R
PD
(Note 12) 30 50 90 kI
DIGITAL OUTPUT (SDA)
Output Low Voltage V
OL
I
SINK
= 3mA 0.2 V
I
2
C TIMING CHARACTERISTICS (SCL, SDA, LDAC, CLR)
SCL Clock Frequency f
SCL
400 kHz
Bus Free Time Between a STOP
and a START Condition
t
BUF
1.3 Fs
Hold Time Repeated for a
START Condition
t
HD;STA
0.6 Fs
SCL Pulse Width Low t
LOW
1.3 Fs
SCL Pulse Width High t
HIGH
0.6 Fs
Setup Time for Repeated START
Condition
t
SU;STA
0.6 Fs
Data Hold Time t
HD;DAT
0 900 ns
Data Setup Time t
SU;DAT
100 ns
SDA and SCL Receiving
Rise Time
t
r
20 +
C
B
/10
300 ns
SDA and SCL Receiving
Fall Time
t
f
20 +
C
B
/10
300 ns
SDA Transmitting Fall Time t
f
20 +
C
B
/10
250 ns
Setup Time for STOP Condition t
SU;STO
0.6 Fs
Bus Capacitance Allowed C
B
V
DD
= 2.7V to 5.5V 10 400 pF
Pulse Width of Suppressed Spike t
sp
50 ns
CLR Removal Time Prior to a
Recognized START
t
CLRSTA
100 ns
CLR Pulse Width Low t
CLPW
20 ns
LDAC Pulse Width Low t
LDPW
20 ns
SCLK Rise to LDAC Fall to Hold t
LDH
Applies to execution edge 400 ns