Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) TQFN 40 EP

General Description

The MAX5852 dual, 8-bit, 165Msps digital-to-analog

converter (DAC) provides superior dynamic performance

in wideband communication systems. The device inte-

grates two 8-bit DAC cores, and a 1.24V reference. The

MAX5852 supports single-ended and differential modes

of operation. The dynamic performance is maintained

over the entire 2.7V to 3.6V power-supply operating

range. The analog outputs support a -1.0V to +1.25V

compliance voltage.

The MAX5852 can operate in interleaved data mode to

reduce the I/O pin count. This allows the converter to

be updated on a single, 8-bit bus.

The MAX5852 features digital control of channel gain

matching to within ±0.4dB in sixteen 0.05dB steps.

Channel matching improves sideband suppression in

analog quadrature modulation applications. The on-

chip 1.24V bandgap reference includes a control

amplifier that allows external full-scale adjustments of

both channels through a single resistor. The internal ref-

erence can be disabled and an external reference may

be applied for high-accuracy applications.

The MAX5852 features full-scale current outputs of 2mA

to 20mA and operates from a 2.7V to 3.6V single sup-

ply. The DAC supports three modes of power-control

operation: normal, low-power standby, and complete

power-down. In power-down mode, the operating

current is reduced to 1µA.

The MAX5852 is packaged in a 40-pin thin QFN with

exposed paddle (EP) and is specified for the extended

(-40°C to +85°C) temperature range.

Pin-compatible, lower speed, and higher resolution ver-

sions are also available. Refer to the MAX5853 (10 bit,

80Msps), the MAX5851 (8 bit, 80Msps), and the

MAX5854 (10 bit, 165Msps) data sheets for more infor-

mation. See Table 4.

Applications

Communications

VSAT, LMDS, MMDS, WLAN,

Point-to-Point Microwave Links

Wireless Base Stations

Quadrature Modulation

Direct Digital Synthesis (DDS)

Instrumentation/ATE

Features

♦ 8-Bit, 165Msps Dual DAC

♦ Low Power

190mW with I

= 20mA at f

CLK

= 165MHz

♦ 2.7V to 3.6V Single Supply

♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

67dBc SFDR at f

OUT

= 40MHz

♦ Programmable Channel Gain Matching

♦ Integrated 1.24V Low-Noise Bandgap Reference

♦ Single-Resistor Gain Control

♦ Interleaved Data Mode

♦ Single-Ended and Differential Clock Input Modes

♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm

♦ EV Kit Available—MAX5852 EV Kit

MAX5852

Dual, 8-Bit, 165Msps, Current-Output DAC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3232; Rev 0; 4/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5852ETL -40°C to +85°C

40 Thin QFN-EP*

40 36373839

19 2016 17

3132

3435

N.C.

DB6

AGND

MAX5852

THIN QFN

TOP VIEW

OUTPA

OUTNA

AGND

OUTPB

OUTNB

REFR

REFO

DB7

DB4

DB5

DB3

DB2

DGND

DB0

DB1

CGND

CLK

CLKXN

CLKXP

DCE

N.C.

DA0/G0

DA1/G1

DA2/G2

DA3/G3

DA4/REN

DA5/IDE

DA6/DACEN

DA7/PD

Pin Configuration

*EP = Exposed paddle.

Summary of content (18 pages)

PAGE 1
9-3232; Rev 0; 4/04 KIT ATION EVALU LE B A IL A AV Dual, 8-Bit, 165Msps, Current-Output DAC ♦ 2.7V to 3.6V Single Supply ♦ Full Output Swing and Dynamic Performance at 2.7V Supply ♦ Superior Dynamic Performance 67dBc SFDR at fOUT = 40MHz ♦ Programmable Channel Gain Matching ♦ Integrated 1.
PAGE 2
MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ...................................................... -0.3V to +4V DVDD to DGND...................................................... -0.3V to +4V CVDD to CGND...................................................... -0.3V to +4V AVDD to DVDD .............................................................-4V to +4V AVDD to CVDD .............................................................-4V to +4V DVDD to CVDD .............
PAGE 3
Dual, 8-Bit, 165Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS 8 tones at 2.1MHz spacing, fCLK = 165MHz, fOUT = 28.3MHz to 45.
PAGE 4
MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
Dual, 8-Bit, 165Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Analog Supply Current (Note 2) SYMBOL IAVDD MAX IFS = 20mA, single-ended clock mode 43.
PAGE 6
MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 7
Dual, 8-Bit, 165Msps, Current-Output DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 100MHz) 0dBFS 70 75 75 55 -6dBFS 50 -12dBFS 65 SFDR (dBc) 60 60 55 -12dBFS 50 60 55 45 45 40 40 40 35 35 35 30 30 10 20 30 40 50 60 70 80 30 0 90 -6dBFS -12dBFS 50 45 0 0dBFS 70 65 SFDR (dBc) 10 15 20 25 30 35 40 45 50 5 0 2 4 6 8 10 12 14 fOUT (MHz) fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 200MHz) SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 8
Typical Operating Characteristics (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) SINGLE-TONE SFDR (fCLK = 165MHz, 10MHz WINDOW) fT6 -40 fT2 fT7 -50 fT8 fT1 -60 -20 -40 -50 -60 -30 -40 -50 -60 -70 -70 -80 -80 -90 -90 -90 -100 -100 -100 11.7 -70 -80 4 21.7 31.7 41.7 51.7 61.7 fOUT (MHz) fT5 = 38.7002MHz fT1 = 28.3667MHz fT6 = 41.0333MHz fT2 = 30.
PAGE 9
Dual, 8-Bit, 165Msps, Current-Output DAC POWER DISSIPATION vs. SUPPLY VOLTAGES (fCLK = 165MHz, fOUT = 10MHz) DIFFERENTIAL CLOCK DRIVE 190 180 SINGLE-ENDED CLOCK DRIVE 220 210 200 190 170 150 160 70 95 120 1.21460 1.21450 1.21440 1.21430 1.21420 1.21410 2.70 170 145 1.21470 2.85 3.00 3.15 3.30 3.45 1.21400 2.70 3.60 2.85 SUPPLY VOLTAGES (V) fCLK (MHz) REFERENCE VOLTAGE vs. TEMPERATURE 3.00 3.15 3.30 3.45 3.60 SUPPLY VOLTAGES (V) DYNAMIC RESPONSE RISE TIME MAX5852 toc20 1.
PAGE 10
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852 Pin Description PIN NAME 1 DA7/PD 2 3 FUNCTION Channel A Input Data Bit 7 (MSB)/Power-Down DA6/DACEN Channel A Input Data Bit 6/DAC Enable Control DA5/IDE Channel A Input Data Bit 5/Interleaved Data Enable 4 DA4/REN Channel A Input Data Bit 4/Reference Enable. Setting REN = 0 enables the internal reference. Setting REN = 1 disables the internal reference.
PAGE 11
Dual, 8-Bit, 165Msps, Current-Output DAC PIN NAME FUNCTION 32 REFR Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET. 33, 39 AVDD Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
PAGE 12
MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC Table 1. Control Word Format and Function MSB LSB PD DACEN REN IDE CONTROL WORD PD G2 G1 G0 FUNCTION Power-Down. The part enters power-down mode if PD = 1. DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode. IDE Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both channels is applied through channel A in a multiplexed fashion.
PAGE 13
Dual, 8-Bit, 165Msps, Current-Output DAC 10µF MAX4040 1.24V BANDGAP REFERENCE AGND 1.24V BANDGAP REFERENCE AVDD MAX6520 CCOMP* REFR CURRENTSOURCE ARRAY IREF IFS AGND IREF = EXTERNAL 1.2V REFERENCE REFR MAX5852 Figure 3. Setting IFS with the Internal 1.24V Reference and the Control Amplifier The CLK pin now becomes an output, and provides a single-ended replica of the differential clock signal, which may be used to synchronize the input data.
PAGE 14
MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC tCXH tCXL CLKXN CLKXP tCDL tCDH CLK OUTPUT tCWL CW tDCS DA0–DA7 DACA - 1 tCS tDCH DACA + 1 DACA tCW CONTROL WORD DACA + 2 DACA + 3 OUTNA DACA - 1 DACA DACA + 1 DACA + 2 XXXX (CONTROL WORD DATA) DACA + 3 OUTPA tDCS DB0–DB7 DACB - 1 tDCH DACB + 1 DACB DACB + 2 XXXX DACB + 3 OUTNB DACB - 1 DACB DACB + 1 DACB + 2 XXXX OUTPB Figure 5.
PAGE 15
Dual, 8-Bit, 165Msps, Current-Output DAC AVDD DVDD CVDD 50Ω OUTPA DA0–DA7 MAX5852 AVDD DVDD CVDD VOUTA, SINGLE ENDED 50Ω DA0–DA7 1/2 OUTPA 1/2 100Ω MAX5852 8 MAX5852 8 OUTNA OUTNA 50Ω 50Ω OUTPB DB0–DB7 50Ω 50Ω VOUTB, SINGLE ENDED DB0–DB7 1/2 100Ω 8 MAX5852 8 OUTPB 1/2 MAX5852 OUTNB OUTNB 50Ω 50Ω AGND DGND CGND Figure 7.
PAGE 16
MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5852. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the powersupply and filter configuration to realize optimum dynamic performance. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended.
PAGE 17
Dual, 8-Bit, 165Msps, Current-Output DAC Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.
PAGE 18
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS MAX5852 Dual, 8-Bit, 165Msps, Current-Output DAC D2 D CL D/2 b D2/2 k E/2 E2/2 (NE-1) X e E CL E2 k e L (ND-1) X e e L CL CL L1 L L e A1 A2 e A PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm 21-0141 E 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.