Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) TQFN 40 EP

General Description

The MAX5853 dual, 10-bit, 80Msps digital-to-analog

converter (DAC) provides superior dynamic performance

in wideband communication systems. The device inte-

grates two 10-bit DAC cores, and a 1.24V reference. The

converter supports single-ended and differential modes

of operation. The MAX5853 dynamic performance is

maintained over the entire 2.7V to 3.6V power-supply

operating range. The analog outputs support a -1.0V to

+1.25V compliance voltage.

The MAX5853 can also operate in interleave data mode

to reduce the I/O pin count. This allows the converter to

be updated on a single, 10-bit bus.

The MAX5853 features digital control of channel gain

matching to within ±0.4dB in sixteen 0.05dB steps.

Channel matching improves sideband suppression in

analog quadrature modulation applications. The on-

chip 1.24V bandgap reference includes a control

amplifier that allows external full-scale adjustments of

both channels through a single resistor. The internal ref-

erence can be disabled and an external reference may

be applied for high-accuracy applications.

The MAX5853 features full-scale current outputs of 2mA

to 20mA and operates from a 2.7V to 3.6V single supply.

The DAC supports three modes of power-control opera-

tion: normal, low-power standby, and complete power-

down. In power-down mode, the operating current is

reduced to 1µA.

The MAX5853 is packaged in a 40-pin thin QFN with

exposed paddle (EP) and is specified for the extended

(-40°C to +85°C) temperature range.

Pin-compatible, higher speed, and lower resolution

versions are also available. Refer to the MAX5854

(10-bit, 165Msps), the MAX5852** (8-bit, 165Msps), and

the MAX5851** (8-bit, 80Msps) data sheets for more

information. See Table 4 at the end of the data sheet.

Applications

Communications

SatCom, LMDS, MMDS, HFC, DSL, WLAN,

Point-to-Point Microwave Links

Wireless Base Stations

Quadrature Modulation

Direct Digital Synthesis (DDS)

Instrumentation/ATE

Features

♦ 10-Bit, 80Msps Dual DAC

♦ Low Power

77mW with I

= 5mA at f

CLK

= 80MHz

♦ 2.7V to 3.6V Single Supply

♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

78dBc SFDR at f

OUT

= 20MHz

♦ Programmable Channel Gain Matching

♦ Integrated 1.24V Low-Noise Bandgap Reference

♦ Single-Resistor Gain Control

♦ Interleaved Data Mode

♦ Single-Ended and Differential Clock Input Modes

♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm

♦ EV Kit Available—MAX5854 EV Kit

MAX5853

Dual, 10-Bit, 80Msps, Current-Output DAC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3196; Rev 0; 2/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX5853ETL -40°C to +85°C

40 Thin QFN-EP*

40 36373839

19 2016 17

3132

3435

DA0

DB8

AGND

MAX5853

THIN QFN

TOP VIEW

OUTPA

OUTNA

AGND

OUTPB

OUTNB

REFR

REFO

DB9

DB6

DB7

DB5

DB4

DGND

DB2

DB3

CGND

CLK

CLKXN

CLKXP

DCE

DB0

DB1

DA1

DA2/G0

DA3/G1

DA4/G2

DA5/G3

DA6/REN

DA7/IDE

DA8/DACEN

DA9/PD

Pin Configuration

*EP = Exposed paddle.

**Future product—contact factory for availability.

Summary of content (18 pages)

PAGE 1
9-3196; Rev 0; 2/04 KIT ATION EVALU LE B A IL A AV Dual, 10-Bit, 80Msps, Current-Output DAC Applications Communications SatCom, LMDS, MMDS, HFC, DSL, WLAN, Point-to-Point Microwave Links Wireless Base Stations Quadrature Modulation Direct Digital Synthesis (DDS) Instrumentation/ATE ♦ 2.7V to 3.6V Single Supply ♦ Full Output Swing and Dynamic Performance at 2.7V Supply ♦ Superior Dynamic Performance 78dBc SFDR at fOUT = 20MHz ♦ Programmable Channel Gain Matching ♦ Integrated 1.
PAGE 2
MAX5853 Dual, 10-Bit, 80Msps, Current-Output DAC ABSOLUTE MAXIMUM RATINGS OUTPA, OUTNA to AGND ..........(AVDD - 4.8V) to (AVDD + 0.3V) OUTPB, OUTNB to AGND ..........(AVDD - 4.8V) to (AVDD + 0.3V) Maximum Current into Any Pin (excluding power supplies) ..........................................±50mA Continuous Power Dissipation (TA = +70°C) 40-Pin Thin QFN (derate 26.3mW/°C above +70°C)....2105mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range ..............
PAGE 3
Dual, 10-Bit, 80Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, differential output, output amplitude = 0dBFS, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C, guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX5853 Dual, 10-Bit, 80Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, differential output, output amplitude = 0dBFS, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C, guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
Dual, 10-Bit, 80Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, differential output, output amplitude = 0dBFS, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C, guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 6
MAX5853 Dual, 10-Bit, 80Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, differential output, output amplitude = 0dBFS, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C, guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 7
Dual, 10-Bit, 80Msps, Current-Output DAC -6dBFS 90 85 75 70 65 70 65 -12dBFS 60 55 SFDR (dBc) 75 70 65 60 55 -12dBFS 50 45 40 35 30 0 5 10 15 20 25 30 35 40 0dBFS -6dBFS 80 75 SFDR (dBc) -12dBFS 60 55 50 45 40 35 30 0 2 4 6 8 10 12 14 16 18 20 22 3 1 5 7 9 11 13 fOUT (MHz) fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 65MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 80MHz) SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 8
Typical Operating Characteristics (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, IFS = 20mA, differential output, differential clock (unless otherwise noted), TA = +25°C.) fT5 -40 fT3 fT6 -50 fT2 fT7 fT1 fT8 -60 -80 -30 -40 -50 -60 -30 -40 -50 -60 -70 -70 -80 -80 -90 -90 -90 -100 -100 100 6.5 9.5 12.5 15.5 18.5 21.5 5 7 fOUT (MHz) 9 11 0.9 1.
PAGE 9
Dual, 10-Bit, 80Msps, Current-Output DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 0.4 0.3 0.1 0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 150 300 450 600 750 900 1050 150 300 450 600 750 900 20 25 30 35 40 45 50 55 60 65 70 75 80 POWER DISSIPATION vs. SUPPLY VOLTAGES (fCLK = 80MHz, fOUT = 10MHz) REFERENCE VOLTAGE vs. SUPPLY VOLTAGES (fCLK = 80MHz, fOUT = 10MHz) DIFFERENTIAL CLOCK DRIVE 210 200 190 SINGLE-ENDED CLOCK DRIVE 180 170 REFERENCE VOLTAGE vs.
PAGE 10
Dual, 10-Bit, 80Msps, Current-Output DAC MAX5853 Pin Description PIN 1 2 10 NAME DA9/PD FUNCTION Channel A Input Data Bit 9 (MSB)/Power-Down DA8/DACEN Channel A Input Data Bit 8/DAC Enable Control 3 DA7/IDE Channel A Input Data Bit 7/Interleaved Data Enable 4 DA6/REN Channel A Input Data Bit 6/Reference Enable. Setting REN = 0 enables the internal reference. Setting REN = 1 disables the internal reference.
PAGE 11
Dual, 10-Bit, 80Msps, Current-Output DAC PIN NAME FUNCTION 32 REFR Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET. 33, 39 AVDD Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
PAGE 12
MAX5853 Dual, 10-Bit, 80Msps, Current-Output DAC Table 1. Control Word Format and Function MSB LSB DACEN PD REN IDE G3 CONTROL WORD PD G1 G0 X X FUNCTION Power-Down. The part enters power-down mode if PD = 1. DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode. IDE Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both channels is applied through channel A in a multiplexed fashion.
PAGE 13
Dual, 10-Bit, 80Msps, Current-Output DAC 10µF MAX4040 1.24V BANDGAP REFERENCE AGND 1.24V BANDGAP REFERENCE AVDD MAX6520 CCOMP* REFR CURRENTSOURCE ARRAY IREF IFS AGND IREF = EXTERNAL 1.2V REFERENCE REFR MAX5853 Figure 3. Setting IFS with the Internal 1.24V Reference and the Control Amplifier CURRENTSOURCE ARRAY IREF IFS AGND RSET AGND *COMPENSATION CAPACITOR (CCOMP ≈ 100nF). REN = 1 REFO RSET RSET 0.
PAGE 14
MAX5853 Dual, 10-Bit, 80Msps, Current-Output DAC tCXH tCXL CLKXN CLKXP tCDL tCDH CLK OUTPUT tCWL CW tDCS DA0–DA9 DACA - 1 tCS tDCH DACA + 1 DACA tCW CONTROL WORD DACA + 2 DACA + 3 OUTNA DACA - 1 DACA DACA + 1 XXXX DACA + 2 (CONTROL WORD DATA) DACA + 3 OUTPA tDCS DB0–DB9 DACB - 1 tDCH DACB DACB + 1 DACB + 2 XXXX DACB + 3 OUTNB DACB - 1 DACB DACB + 1 DACB + 2 XXXX DACB + 3 OUTPB Figure 5.
PAGE 15
Dual, 10-Bit, 80Msps, Current-Output DAC AVDD DVDD CVDD 50Ω OUTPA DA0–DA9 MAX5853 AVDD DVDD CVDD VOUTA, SINGLE ENDED 50Ω DA0–DA9 1/2 OUTPA 1/2 100Ω MAX5853 10 MAX5853 10 OUTNA OUTNA 50Ω 50Ω OUTPB DB0–DB9 50Ω 50Ω VOUTB, SINGLE ENDED DB0–DB9 1/2 100Ω 10 MAX5853 10 OUTPB 1/2 MAX5853 OUTNB OUTNB 50Ω 50Ω AGND DGND CGND Figure 7.
PAGE 16
MAX5853 Dual, 10-Bit, 80Msps, Current-Output DAC power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5853. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the power supply and filter configuration to realize optimum dynamic performance.
PAGE 17
Dual, 10-Bit, 80Msps, Current-Output DAC Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.
PAGE 18
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS MAX5853 Dual, 10-Bit, 80Msps, Current-Output DAC D2 D CL D/2 b D2/2 k E/2 E2/2 E (NE-1) X e CL E2 k e L (ND-1) X e CL CL L L e A1 A2 e A PACKAGE OUTLINE 36,40L THIN QFN, 6x6x0.8 mm 21-0141 D 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2.