Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 10 Bit TQFN 48

General Description

The MAX5864 ultra-low-power, highly integrated analog

front end is ideal for portable communication equipment

such as handsets, PDAs, WLAN, and 3G wireless termi-

nals. The MAX5864 integrates dual 8-bit receive ADCs

and dual 10-bit transmit DACs while providing the high-

est dynamic performance at ultra-low power. The ADCs’

analog I-Q input amplifiers are fully differential and

accept 1V

P-P

full-scale signals. Typical I-Q channel

phase matching is ±0.1° and amplitude matching is

±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc

spurious-free dynamic range (SFDR) at f

= 5.5MHz and

CLK

= 22Msps. The DACs’ analog I-Q outputs are fully

differential with ±400mV full-scale output, and 1.4V com-

mon-mode level. Typical I-Q channel phase match is

±0.15° and amplitude match is ±0.05dB. The DACs also

feature dual 10-bit resolution with 71.7dBc SFDR, and

57dB SNR at f

OUT

= 2.2MHz and f

CLK

= 22MHz.

The ADCs and DACs operate simultaneously or indepen-

dently for frequency-division duplex (FDD) and time-divi-

sion duplex (TDD) modes. A 3-wire serial interface

controls power-down and transceiver modes of opera-

tion. The typical operating power is 42mW at f

CLK

22Msps with the ADCs and DACs operating simultane-

ously in transceiver mode. The MAX5864 features an

internal 1.024V voltage reference that is stable over the

entire operating power-supply range and temperature

range. The MAX5864 operates on a +2.7V to +3.3V ana-

log power supply and a +1.8V to +3.3V digital I/O power

supply for logic compatibility. The quiescent current is

5.6mA in idle mode and 1µA in shutdown mode. The

MAX5864 is specified for the extended (-40°C to +85°C)

temperature range and is available in a 48-pin thin QFN

package.

Applications

Narrowband/Wideband CDMA Handsets

and PDAs

Fixed/Mobile Broadband Wireless Modems

3G Wireless Terminals

Features

♦ Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs

♦ Ultra-Low Power

42mW at f

CLK

= 22MHz (Transceiver Mode)

34mW at f

CLK

= 15.36MHz (Transceiver Mode)

Low-Current Idle and Shutdown Modes

♦ Excellent Dynamic Performance

48.5dB SINAD at f

= 5.5MHz (ADC)

71.7dB SFDR at f

OUT

= 2.2MHz (DAC)

♦ Excellent Gain/Phase Match

±0.1° Phase, ±0.03dB Gain at f

= 5.5MHz (ADC)

♦ Internal/External Reference Option

♦ +1.8V to +3.3V Digital Output Level (TTL/CMOS

Compatible)

♦ Multiplexed Parallel Digital Input/Output for

ADCs/DACs

♦ Miniature 48-Pin Thin QFN Package (7mm

7mm)

♦ Evaluation Kit Available (Order MAX5865EVKIT)

MAX5864

Ultra-Low-Power, High-Dynamic-

Performance, 22Msps Analog Front End

________________________________________________________________ Maxim Integrated Products 1

ADC

IA+

IA-

QA+

QA-

ID+

ID-

QD+

QD-

REFP

COM

REFN

DIN

SCLK

REFIN

DAC

ADC

OUTPUT

MUX

DAC

INPUT

MUX

CLK

DA0–DA7

DD0–DD9

MAX5864

REF AND

BIAS

SERIAL

INTERFACE

AND SYSTEM

CONTROL

Functional Diagram

19-2915; Rev 1; 10/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX5864ETM -40°C to +85°C

48 Thin QFN-EP*

(7mm x 7mm)

MAX5864E/D -40°C to +85°C Dice**

*EP = Exposed paddle.

**Contact factory for dice specifications.

Pin Configuration appears at end of data sheet.

Summary of content (26 pages)

PAGE 1
9-2915; Rev 1; 10/03 KIT ATION EVALU E L B AVAILA Ultra-Low-Power, High-DynamicPerformance, 22Msps Analog Front End Applications Features ♦ Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs ♦ Ultra-Low Power 42mW at fCLK = 22MHz (Transceiver Mode) 34mW at fCLK = 15.36MHz (Transceiver Mode) Low-Current Idle and Shutdown Modes ♦ Excellent Dynamic Performance 48.5dB SINAD at fIN = 5.5MHz (ADC) 71.7dB SFDR at fOUT = 2.2MHz (DAC) ♦ Excellent Gain/Phase Match ±0.1° Phase, ±0.03dB Gain at fIN = 5.
PAGE 2
MAX5864 Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND................................-0.3V to +3.3V GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V to (VDD + 0.3V) DD0–DD9, SCLK, DIN, CS, CLK, DA0–DA7 to OGND .............................-0.3V to (OVDD + 0.
PAGE 3
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC DC ACCURACY Resolution 8 Bits ±0.
PAGE 4
MAX5864 Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
PAGE 5
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
PAGE 6
MAX5864 Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
PAGE 7
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.
PAGE 8
Typical Operating Characteristics (continued) (VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.) -40 -60 IA 49 48 48 -50 MAX5864 toc06 F2 IA QA 47 SINAD (dB) F1 -30 49 50 MAX5864 toc05 fCLK = 22MHz f1 = 1.8MHz f2 = 2.
PAGE 9
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE 70 QA 49 50 MAX5864 toc14 fIN = 5.50885 75 50 MAX5864 toc13 80 ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING RATE MAX5864 toc15 ADC SPURIOUS -FREE DYNAMIC RANGE vs. ANALOG INPUT POWER QA 49 55 50 SINAD (dB) 60 SNR (dB) SFDR (dBc) 65 IA 48 47 IA 48 47 45 40 46 46 35 fIN = 5.
PAGE 10
Typical Operating Characteristics (continued) (VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.) -0.4 -0.5 -0.6 -0.7 -0.8 Rx MODE ONLY 10 SUPPLY CURRENT (mA) 1.5 GAIN ERROR (% FS) -0.3 12 MAX5864 toc23 -0.2 OFFSET ERROR (% FS) 2.
PAGE 11
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End f1 f2 -40 -40 -50 -60 -70 Xcrv MODE 14 SUPPLY CURRENT (mA) -30 OUTPUT POWER (dBm) AMPLITUDE (dB) -20 fCLK = 15.36Msps WCDMA -30 16 MAX5864 toc32 f1 = 2.0MHz, f2 = 2.2MHz, -7dBFS -10 SUPPLY CURRENT vs.
PAGE 12
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End MAX5864 Pin Description PIN NAME 1 REFP 2, 8, 43 VDD Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 3 IA+ Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+. 4 IA- Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM. 5, 7, 12, 37, 42 GND Analog Ground. Connect all pins to GND ground plane.
PAGE 13
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End The MAX5864 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing ultra-low power and highest dynamic performance at a conversion rate of 22Msps. The ADCs’ analog input amplifiers are fully differential and accept 1VP-P full-scale signals. The DACs’ analog outputs are fully differential with ±400mV full-scale output range at 1.4V common mode.
PAGE 14
MAX5864 Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End Dual 8-Bit ADC The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA.
PAGE 15
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End 1 LSB = 2 x VREF 256 VREF = VREFP - VREFN VREF VREF 1000 0001 1000 0000 0111 1111 (COM) VREF OFFSET BINARY OUTPUT CODE (LSB) VREF 1111 1111 1111 1110 1111 1101 0000 0011 0000 0010 0000 0001 0000 0000 -128 -127 -126 -125 -1 0 +1 +125 +126 +127 +128 (COM) INPUT VOLTAGE (LSB) puts. CHI data is updated on the rising edge and CHQ data is updated on the falling edge of the CLK.
PAGE 16
MAX5864 Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN) DIFFERENTIAL OUTPUT VOLTAGE OFFSET BINARY (DD0–DD9) INPUT DECIMAL CODE VREFDAC 1023 × 2.56 1023 11 1111 1111 1023 VREFDAC 1021 × 2.56 1023 11 1111 1110 1022 VREFDAC 3 × 2.56 1023 10 0000 0001 513 1 VREFDAC × 2.56 1023 10 0000 0000 512 − VREFDAC 2.56 − VREFDAC 2.56 − VREFDAC 2.
PAGE 17
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End MAX5864 Table 3. MAX5864 Operation Modes D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Shutdown Device shutdown. REF is off, ADCs are off, and the ADC bus is tri-stated; DACs are off and the DAC input bus must be set to zero or OVDD. X X X X X 0 0 0 Idle REF and CLK are on, ADCs are off, and the ADC bus is tri-stated; DACs are off and the DAC input bus must be set to zero or OVDD.
PAGE 18
MAX5864 Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End tCSW CS tCSS tCP tCH tCL tCS SCLK tDS DIN LSB MSB tDH Figure 5. 3-Wire Serial Interface Timing Diagram CS SCLK DIN 8-BIT DATA tWAKE, SD, ST_ (Rx) OR tENABLE, Rx DAO–DA7 ID/QD ADC DIGITAL OUTPUT. SINAD SETTLES WITHIN 1dB DAC ANALOG OUTPUT. OUTPUT SETTLES TO 10 LSB ERROR tWAKE, SD, ST_ (Tx) OR tENABLE, TX Figure 6.
PAGE 19
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End Reference Configurations The MAX5864 features an internal precision 1.024V bandgap reference is stable over the entire power supply and temperature range. The REFIN input provides two modes of reference operation. The voltage at REFIN (VREFIN) sets reference operation mode (Table 4). In internal reference mode, connect REFIN to V DD. VREF is an internally generated 0.512V.
PAGE 20
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End MAX5864 Using Op-Amp Coupling ID+ VOUT MAX5864 ID- QD+ VOUT QD- Figure 8. Balun-Transformer Coupled Differential to SingleEnded Output Drive for DACs REFP 1kΩ VIN 0.1µF RISO 50Ω INA+ 100Ω CIN 22pF 1kΩ COM REFN 0.1µF RISO 50Ω INA- 100Ω CIN 22pF REFP VIN 0.1µF 1kΩ MAX5864 RISO 50Ω INB+ 100Ω 1kΩ REFN CIN 22pF 0.
PAGE 21
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End MAX5864 R4 600Ω R5 600Ω MAX5864 RISO 22Ω R1 600Ω INACIN 5pF R2 600Ω R6 600Ω R7 600Ω R8 600Ω R9 600Ω COM R3 600Ω RISO 22Ω CIN 5pF R10 600Ω INA+ R11 600Ω Figure 10. ADC DC-Coupled Differential Drive CLK ADC MAX2391 QUADRATURE DEMODULATOR ADC T/R CLK MAX2395 QUADRATURE TRANSMITTER DAC DIGITAL BASEBAND PROCESSOR ADC OUTPUT MUX DAC INPUT MUX DAC MAX5864 SERIAL BUS Figure 11.
PAGE 22
Figure 11 illustrates the MAX5864 working with the MAX2391 and MAX2395 in TDD mode to provide a complete radio front-end solution. Because the MAX5864 DAC has full differential analog outputs with a common-mode level of 1.4V, it can interface directly with RF quadrature modulators while eliminating discrete components and amplifiers used for level-shifting circuits.
PAGE 23
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End ADC Dynamic Parameter Definitions ADC and DAC Static Parameter Definitions Aperture Jitter Figure 13 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line.
PAGE 24
VDD N.C. GND 37 38 39 40 GND QDQD+ 41 42 43 ID+ IDVDD 45 44 COM REFIN 46 REFN REFP VDD 1 36 2 35 IA+ IAGND CLK 3 34 4 33 5 32 DIN VDD DD9 31 DD8 GND VDD QAQA+ VDD 7 30 8 29 DD7 DD6 MAX5864 CS SCLK 24 DD5 DD4 DD3 DD2 DA7 DD0 DD1 DA5 DA6 23 25 22 26 12 21 11 20 27 19 28 18 9 10 17 GND 6 16 Full-Power Bandwidth A large -0.
PAGE 25
Ultra-Low-Power, High DynamicPerformance, 22Msps Analog Front End 32, 44, 48L QFN .EPS D2 D CL D/2 b D2/2 k E/2 E2/2 E CL (NE-1) X e E2 k L DETAIL A e (ND-1) X e CL CL L L e A1 A2 e A PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 REV.
PAGE 26
MAX5864 Ultra-Low-Power, High-DynamicPerformance, 22Msps Analog Front End Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) COMMON DIMENSIONS EXPOSED PAD VARIATIONS ** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED. TOTAL NUMBER OF LEADS ARE 44. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.