9-2916; Rev 1; 10/03 KIT ATION EVALU E L B AVAILA Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End Applications Narrowband/Wideband CDMA Handsets and PDAs Features ♦ Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs ♦ Ultra-Low Power 75.6mW at fCLK = 40MHz (Transceiver Mode) 64mW at fCLK = 22MHz (Transceiver Mode) Low-Current Idle and Shutdown Modes ♦ Excellent Dynamic Performance 48.4dB SINAD at fIN = 5.5MHz (ADC) 70dB SFDR at fOUT = 2.2MHz (DAC) ♦ Excellent Gain/Phase Match ±0.
MAX5865 Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND................................-0.3V to +3.3V GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V to (VDD + 0.3V) DD0–DD9, SCLK, DIN, CS, CLK, DA0–DA7 to OGND .............................-0.3V to (OVDD + 0.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
MAX5865 Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) Large-Signal Bandwidth FBW AIN = -0.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
MAX5865 Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.
Typical Operating Characteristics (continued) (VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.) -30 -40 IA 49.5 -60 QA 48.0 47.5 47.5 47.0 47.0 46.5 46.5 -110 46.0 46.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End 70 65 QA 49 SINAD (dB) 55 fIN = 10.0732MHz IA 48 60 SNR (dB) SFDR (dBc) fIN = 10.0732MHz QA 49 50 MAX5865 toc14 fIN = 10.0732MHz 75 50 MAX5865 toc13 80 ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING RATE MAX5865 toc15 ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE ADC SPURIOUS-FREE DYNAMIC RANGE vs.
Typical Operating Characteristics (continued) (VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.) ADC GAIN ERROR vs. TEMPERATURE 1.6 GAIN ERROR (%FS) 0.4 1.8 0.2 0 -0.2 -0.4 1.2 1.0 0.8 0.6 0.4 -0.8 0.2 -1.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End SUPPLY CURRENT vs. SAMPLING RATE f2 -40 -50 -60 -70 -80 IDD 0.4 0.3 0.2 20 INL (LSB) SUPPLY CURRENT (mA) f1 -30 15 10 0.1 0 -0.1 -0.2 5 -0.3 IOVDD -0.4 -90 -0.5 0 -100 7.5 11.0 14.5 18.0 22 24 26 28 30 32 34 36 0 40 38 32 64 0.3 0.8 0.6 0.4 0.1 0.2 INL (LSB) 0.2 0 MAX5865 toc36 1.0 MAX5865 toc35 0.4 128 160 192 224 256 DAC INTEGRAL NONLINEARITY ADC DIFFERENTIAL NONLINEARITY 0.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End MAX5865 Pin Description PIN NAME 1 REFP 2, 8, 43 VDD Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 3 IA+ Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+. 4 IA- Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM. 5, 7, 12, 37, 42 GND Analog Ground. Connect all pins to GND ground plane.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End The MAX5865 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing ultra-low power and highest dynamic performance at a conversion rate of 40Msps. The ADCs’ analog input amplifiers are fully differential and accept 1VP-P full-scale signals. The DACs’ analog outputs are fully differential with ±400mV full-scale output range at 1.4V common mode.
MAX5865 Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End Dual 8-Bit ADC The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End 1 LSB = 2 x VREF 256 VREF = VREFP - VREFN VREF VREF 1000 0001 1000 0000 0111 1111 (COM) VREF OFFSET BINARY OUTPUT CODE (LSB) VREF 1111 1111 1111 1110 1111 1101 0000 0011 0000 0010 0000 0001 0000 0000 -128 -127 -126 -125 -1 0 +1 +125 +126 +127 +128 (COM) INPUT VOLTAGE (LSB) puts. CHI data is updated on the rising edge and CHQ data is updated on the falling edge of the CLK.
MAX5865 Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN) OFFSET BINARY (DD0–DD9) INPUT DECIMAL CODE VREFDAC 1023 × 2.56 1023 11 1111 1111 1023 VREFDAC 1021 × 2.56 1023 11 1111 1110 1022 3 VREFDAC × 2.56 1023 10 0000 0001 513 1 VREFDAC × 2.56 1023 10 0000 0000 512 DIFFERENTIAL OUTPUT VOLTAGE − VREFDAC 2.56 − VREFDAC 2.56 − VREFDAC 2.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End MAX5865 Table 3. MAX5865 Operation Modes D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Shutdown Device shutdown. REF is off, ADCs are off, and the ADC bus is tri-stated; DACs are off and the DAC input bus must be set to zero or OVDD. X X X X X 0 0 0 Idle REF and CLK are on, ADCs are off, and the ADC bus is tri-stated; DACs are off and the DAC input bus must be set to zero or OVDD.
MAX5865 Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End tCSW CS tCSS tCP tCH tCL tCS SCLK tDS DIN LSB MSB tDH Figure 5. 3-Wire Serial Interface Timing Diagram CS SCLK DIN 8-BIT DATA tWAKE, SD, ST_ (Rx) OR tENABLE, Rx DAO–DA7 ID/QD ADC DIGITAL OUTPUT. SINAD SETTLES WITHIN 1dB DAC ANALOG OUTPUT. OUTPUT SETTLES TO 10 LSB ERROR tWAKE, SD, ST_ (Tx) OR tENABLE TX Figure 6.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End Reference Configurations The MAX5865 features an internal precision 1.024V bandgap reference that is stable over the entire power supply and temperature range. The REFIN input provides two modes of reference operation. The voltage at REFIN (VREFIN) sets reference operation mode (Table 4). In internal reference mode, connect REFIN to V DD. VREF is an internally generated 0.512V.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End MAX5865 Using Op-Amp Coupling ID+ VOUT MAX5865 ID- QD+ VOUT QD- Figure 8. Balun-Transformer Coupled Differential to SingleEnded Output Drive for DACs REFP 1kΩ VIN 0.1µF RISO 50Ω INA+ 100Ω CIN 22pF 1kΩ COM REFN 0.1µF RISO 50Ω INA- 100Ω CIN 22pF REFP VIN 0.1µF 1kΩ MAX5865 RISO 50Ω INB+ 100Ω 1kΩ REFN CIN 22pF 0.1µF RISO 50Ω 100Ω INBCIN 22pF Figure 9.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End MAX5865 R4 600Ω R5 600Ω MAX5865 RISO 22Ω R1 600Ω INACIN 5pF R2 600Ω R6 600Ω R7 600Ω R8 600Ω R9 600Ω COM R3 600Ω RISO 22Ω CIN 5pF R10 600Ω INA+ R11 600Ω Figure 10. ADC DC-Coupled Differential Drive CLK ADC MAX2391 QUADRATURE DEMODULATOR ADC T/R 10 BIT MAX2395 QUADRATURE TRANSMITTER DAC DIGITAL BASEBAND PROCESSOR ADC OUTPUT MUX DAC INPUT MUX DAC MAX5865 SERIAL BUS Figure 11.
range, it can interface directly with RF transceivers while eliminating discrete components and amplifiers used for level-shifting circuits. Also, the DAC’s full dynamic range is preserved because the internally generated commonmode level eliminates code-generated level shifting or attenuation due to resistor level shifting. The MAX5865 ADC has 1VP-P full-scale range and accepts input common-mode levels of VDD/2 (±200mV).
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. ADC Dynamic Parameter Definitions MAX5865 DAC Offset Error Offset error (Figure 12a) is the difference between the ideal and actual offset point.
Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. THD = 20log (V22 + V32 + ...+ Vn2 ) V1 where V1 is the fundamental amplitude and V2 through Vn are the amplitudes of the 2nd through nth harmonic up to the Nyquist frequency. VDD N.C.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End 32, 44, 48L QFN .EPS D2 D CL D/2 b D2/2 k E/2 E2/2 E CL (NE-1) X e E2 k L DETAIL A e (ND-1) X e CL CL L L e A1 A2 e A PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 REV.
MAX5865 Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) COMMON DIMENSIONS EXPOSED PAD VARIATIONS ** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED. TOTAL NUMBER OF LEADS ARE 44. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.