Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) QFN 68 Exposed Pad

General Description

The MAX5874 is an advanced 14-bit, 200Msps, dual

digital-to-analog converter (DAC). This DAC meets the

demanding performance requirements of signal synthesis

applications found in wireless base stations and other

communications applications. Operating from 3.3V and

1.8V supplies, this dual DAC offers exceptional dynamic

performance such as 78dBc spurious-free dynamic range

(SFDR) at f

OUT

= 16MHz and supports update rates of

200Msps, with a power dissipation of only 260mW.

The MAX5874 utilizes a current-steering architecture

that supports a 2mA to 20mA full-scale output current

range, and allows a 0.1V

P-P

to 1V

P-P

differential

output voltage swing. The device features an integrated

1.2V bandgap reference and control amplifier to ensure

high-accuracy and low-noise performance. A separate

reference input (REFIO) allows for the use of an exter-

nal reference source for optimum flexibility and

improved gain accuracy.

The digital and clock inputs of the MAX5874 accept

3.3V CMOS voltage levels. The device features a flexi-

ble input data bus that allows for dual-port input or a

single-interleaved data port. The MAX5874 is available

in a 68-pin QFN package with an exposed paddle (EP)

and is specified for the extended temperature range

(-40°C to +85°C).

Refer to the MAX5873 and MAX5875 data sheets for

pin-compatible 12-bit and 16-bit versions of the

MAX5874, respectively. Refer to the MAX5877 for an

LVDS-compatible version of the MAX5874.

Applications

Base Stations: Single/Multicarrier UMTS, CDMA, GSM

Communications: Fixed Broadband Wireless Access,

Point-to-Point Microwave

Direct Digital Synthesis (DDS)

Cable Modem Termination System (CMTS)

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 200Msps Output Update Rate

♦ Noise Spectral Density = -160dBFS/Hz at

OUT

= 16MHz

♦ Excellent SFDR and IMD Performance

SFDR = 78dBc at f

OUT

= 16MHz (to Nyquist)

SFDR = 74dBc at f

OUT

= 80MHz (to Nyquist)

IMD = -86dBc at f

OUT

= 10MHz

IMD = -74dBc at f

OUT

= 80MHz

♦ ACLR = 75dB at f

OUT

= 61MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ CMOS-Compatible Digital and Clock Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low 260mW Power Dissipation

♦ 68-Lead QFN-EP Package

♦ Evaluation Kit Available (MAX5874EVKIT)

MAX5874

14-Bit, 200Msps, High-Dynamic-Performance,

Dual DAC with CMOS Inputs

________________________________________________________________ Maxim Integrated Products 1

5859606162 5455565763

DD3.3

DD1.8

A12

QFN

TOP VIEW

A13

DD1.8

N.C.

5253

DACREF

DD3.3

GND

DD3.3

OUTQP

OUTQN

GND

OUTIP

OUTIN

DD3.3

GND

DD3.3

B11

B12

B13

SELIQ

GND

XOR

DORI

TORB

CLKP

CLKN

GND

CLK

GND

N.C.

REFIO

GND

DD3.3

GND

48 B10

A11

656667

A10

2322212019 2726252418 2928 323130

GND

DD1.8

3433

51 B7

FSADJ 17

MAX5874

Pin Configuration

Ordering Information

19-3514; Rev 2; 1/07

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed pad.

+ = Lead-free package. D = Dry pack.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE

PIN-

PACKAGE

PKG

CODE

MAX5874EGK-D -40°C to +85°C

68 QFN-EP*

G6800-4

MAX5874EGK+D -40°C to +85°C

68 QFN-EP*

G6800-4

Selector Guide

PART

RESOLUTION

(Bits)

UPDATE

RATE (Msps)

LOGIC

INPUTS

MAX5873 12 200 CMOS

MAX5874 14 200 CMOS

MAX5875 16 200 CMOS

MAX5876 12 250 LVDS

MAX5877 14 250 LVDS

MAX5878 16 250 LVDS

Summary of content (16 pages)

PAGE 1
KIT ATION EVALU E L B A AVAIL 19-3514; Rev 2; 1/07 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs ♦ 200Msps Output Update Rate ♦ Noise Spectral Density = -160dBFS/Hz at fOUT = 16MHz ♦ Excellent SFDR and IMD Performance SFDR = 78dBc at fOUT = 16MHz (to Nyquist) SFDR = 74dBc at fOUT = 80MHz (to Nyquist) IMD = -86dBc at fOUT = 10MHz IMD = -74dBc at fOUT = 80MHz ♦ ACLR = 75dB at fOUT = 61MHz ♦ 2mA to 20mA Full-Scale Output Current ♦ CMOS-Compatible Digital and Clock Inputs ♦ On-Chip 1.
PAGE 2
MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS TORB, DORI, PD to GND, DACREF ....-0.3V to (DVDD3.3 + 0.3V) Continuous Power Dissipation (TA = +70°C) 68-Pin QFN-EP (derate 41.7mW/°C above +70°C) (Note 1) ............3333.3mW Thermal Resistance θJA (Note 1)...................................+24°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................
PAGE 3
14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50Ω doubleterminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50Ω doubleterminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, external reference VREFIO = 1.25V, output load 50Ω doubleterminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Analog Supply Current SYMBOL CONDITIONS IAVDD3.3 + IAVCLK fDAC = 200Msps, fOUT = 1MHz IAVDD1.8 IDVDD3.3 Digital Supply Current IDVDD1.
PAGE 6
Typical Operating Characteristics (continued) (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50Ω double-terminated, IOUTFS = 20mA, TA = +25°C, unless otherwise noted.) 60 40 20 -60 -70 -12dBFS -80 BW = 12MHz fOUT1 = 29.8706MHz fOUT2 = 30.9937MHz fOUT1 -20 OUTPUT POWER (dBFS) -50 TWO-TONE IMD (dBc) -12dBFS -6dBFS 0 MAX5874 toc05 0dBFS 80 SFDR (dBc) -40 MAX5874 toc04 100 TWO-TONE IMD (fCLK = 100Msps) TWO-TONE IMD vs.
PAGE 7
14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs FOUR-TONE POWER RATIO PLOT (fCLK = 150MHz, fCENTER = 31.6040MHz ) 220 210 INTERNAL REFERENCE fOUT1 -20 -30 fOUT4 -40 -60 -80 200 -40 MAX5874 toc15 -20 OUTPUT POWER (dBFS) EXTERNAL REFERENCE fOUT1 = 29.9997MHz fOUT2 fOUT3 f OUT2 = 31.0251MHz fOUT3 = 31.0640MHz fOUT4 = 32.9829MHz BW = 12MHz ANALOG OUTPUT POWER (dBm) 0 MAX5874 toc13 230 AOUT = 0dBFS fCLK = 184.32MHz fCENTER = 30.
PAGE 8
MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs Pin Description PIN 1–7 NAME FUNCTION A6, A5, A4, Data Bits A6–A0. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits A3, A2, A1, A0 are not used. Connect bits A6–A0 to GND in single-port mode. 8, 9, 59, 60 N.C. No Connection. Leave floating or connect to GND. 10, 12, 13, 15, 20, 23, 26, 27, 30, 33, 36, 43 GND Converter Ground 11 DVDD3.3 Digital Supply Voltage. Accepts a 3.135V to 3.
PAGE 9
14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs PIN NAME FUNCTION 42 XOR DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND. 44 SELIQ DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct data into the I-DAC inputs. If unused, connect SELIQ to GND.
PAGE 10
MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs DVDD3.3 GND DVDD1.8 AVDD1.8 AVDD3.3 OUTIP TORB LATCH DORI XOR/ DECODE LATCH LATCH DAC OUTIN SELIQ CMOS RECEIVER DATA13– DATA0 LATCH XOR OUTQP LATCH XOR/ DECODE LATCH LATCH DAC OUTQN AVCLK CLKP CLKN DACREF CLK INTERFACE 1.2V REFERENCE GND REFIO FSADJ MAX5874 POWER-DOWN BLOCK PD GND Figure 1.
PAGE 11
14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5874 1.2V REFERENCE AVDD CURRENT SOURCES 10kΩ CURRENT SWITCHES REFIO 1µF OUTIP FSADJ CURRENT-SOURCE ARRAY DAC IREF RSET IOUT OUTIN IOUT DACREF IREF = VREFIO / RSET OUTIN OUTIP Figure 2. Reference Architecture, Internal Reference Configuration Figure 3. Simplified Analog Output Structure Table 2. DAC Output Code Table bit applied to XOR through exclusive-OR gates. Pulling XOR high inverts the input data.
PAGE 12
MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs DATA13–DATA0, XOR N-1 N N+1 N+2 tH tS CLK tPD DAC OUTPUT N-2 N-4 N-5 N-6 N-3 (a) DUAL-PORT (PARALLEL) TIMING DIAGRAM CLK I0 DATAIN Q0 I1 Q1 I2 Q2 I3 Q3 SELIQ tS tH I-4 I-5 I OUT Q OUT I-3 I-2 I-6 Q-6 Q-5 Q-4 Q-3 tPD Q-2 (b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM Figure 4.
PAGE 13
14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs 0.1µF CLKP 25Ω SINGLE-ENDED CLOCK SOURCE The distortion performance of the DAC depends on the load impedance. The MAX5874 is optimized for 50Ω differential double termination. It can be used with a transformer output as shown in Figure 6 or just one 25Ω resistor from each output to ground and one 50Ω resistor between the outputs (Figure 7). This produces a fullscale output power of up to -2dBm, depending on the output current setting.
PAGE 14
MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs 25Ω OUTIP/OUTQP DATA13–DATA0 50Ω MAX5874 14 OUTP OUTN OUTIN/OUTQN 25Ω GND Figure 7. Differential Output Configuration optimizing the DAC’s dynamic performance. Keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. The MAX5874 requires five separate power-supply inputs for analog (AV DD1.8 and AV DD3.3 ), digital (DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry.
PAGE 15
14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.
PAGE 16
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 68L QFN.EPS MAX5874 14-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 PACKAGE OUTLINE, 68L QFN, 10x10x0.