Datasheet

MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
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Pin Description
PIN NAME FUNCTION
1, 2, 16,
25–29
N.C. No connection. Do not connect to these pins. Do not tie these pins together.
3XOR
XOR Input Pin.
XOR = 1 inverts the digital input data.
XOR = 0 leaves the digital input data unchanged.
XOR has an internal pulldown resistor and may be left unconnected if not used.
4, 9 VCLK
Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest CLKGND.
5, 8
CLKGND
Clock Ground
6 CLKP Converter Clock Input. Positive input terminal for the converter clock.
7 CLKN Complementary Converter Clock Input. Negative input terminal for the converter clock.
10 PD
Power-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows for
normal operation of the DAC.
11, 21, 23
AV
DD
Analog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest AGND.
12, 17, 20,
22, 24, EP
AGND Analog Ground. Exposed paddle (EP) must be connected to AGND.
13 REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 0.1µF
capacitor to AGND. Can be driven with an external reference source.
14 FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2kΩ resistor between FSADJ and DACREF.
15 DACREF
Return Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF.
18 IOUTN
Complementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.
19 IOUTP
DAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.
30 SEL0
Mode Select Input SEL0. This pin has an internal pulldown resistor; it can be left open to disable the
segment-shuffling function (see the Segment Shuffling section).
31, 43 DV
DD
Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest DGND.
32, 42 DGND Digital Ground
33 B13 Data Bit 13 (MSB)
34 B12 Data Bit 12
35 B11 Data Bit 11
36 B10 Data Bit 10
37 B9 Data Bit 9