Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) QFN 48 EP

General Description

The MAX5885 is an advanced, 16-bit, 200Msps digital-

to-analog converter (DAC) designed to meet the

demanding performance requirements of signal synthe-

sis applications found in wireless base stations and

other communications applications. Operating from a

single 3.3V supply, this DAC offers exceptional dyna-

mic performance such as 77dBc spurious-free dynamic

range (SFDR) at f

OUT

= 10MHz. The DAC supports

update rates of 200Msps at a power dissipation of less

than 200mW.

The MAX5885 utilizes a current-steering architecture,

which supports a full-scale output current range of 2mA

to 20mA, and allows a differential output voltage swing

between 0.1V

P-P

and 1V

P-P

The MAX5885 features an integrated 1.2V bandgap

reference and control amplifier to ensure high accuracy

and low noise performance. Additionally, a separate

reference input pin enables the user to apply an exter-

nal reference source for optimum flexibility and to

improve gain accuracy.

The digital and clock inputs of the MAX5885 are

designed for CMOS-compatible voltage levels. The

MAX5885 is available in a 48-pin QFN package with an

exposed paddle (EP) and is specified for the extended

industrial temperature range (-40°C to +85°C).

Refer to the MAX5883 and MAX5884 data sheets for

pin-compatible 12- and 14-bit versions of the MAX5885.

For LVDS high-speed versions, refer to the MAX5886/

MAX5887/MAX5888 data sheet.

Applications

Base Stations: Single/Multicarrier UMTS,

CDMA, GSM

Communications: LMDS, MMDS, Point-to-Point

Microwave

Digital Signal Synthesis

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 200Msps Output Update Rate

♦ Single 3.3V Supply Operation

♦ Excellent SFDR and IMD Performance

SFDR = 77dBc at f

OUT

= 10MHz (to Nyquist)

IMD = -88dBc at f

OUT

= 10MHz

ACLR = 74dB at f

OUT

= 30.72MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ CMOS-Compatible Digital and Clock Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low Power Dissipation

♦ 48-Pin QFN-EP Package

MAX5885

3.3V, 16-Bit, 200Msps High Dynamic

Performance DAC with CMOS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2786; Rev 1; 12/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX5885EGM -40°C to +85°C 48 QFN-EP*

B12

B13

B15

DGND

N.C.

SEL0

B14

XOR

VCLK

CLKGND

CLKP

CLKN

CLKGND

VCLK

AGND

IOUTN

IOUTP

AGND

N.C.

DACREF

FSADJ

REFIO

DGND

B11

B10

QFN

MAX5885

AGND

TOP VIEW

Pin Configuration

*EP = Exposed paddle.

Summary of content (18 pages)

PAGE 1
9-2786; Rev 1; 12/03 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at fOUT = 10MHz (to Nyquist) IMD = -88dBc at fOUT = 10MHz ACLR = 74dB at fOUT = 30.72MHz ♦ 2mA to 20mA Full-Scale Output Current ♦ CMOS-Compatible Digital and Clock Inputs ♦ On-Chip 1.
PAGE 2
MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW Thermal Resistance (θJA) ..............................................+37°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................
PAGE 3
.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs (AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, fCLK = 200Msps, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, fCLK = 200Msps, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data Latency 3.
PAGE 5
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs 80 90 0dB FS 50 40 70 60 0dB FS 50 -12dB FS 40 30 20 20 10 10 10 0 10 15 20 0 0 25 0dB FS 40 30 5 -6dB FS 50 20 0 10 20 30 40 50 0 15 30 45 60 75 fOUT (MHz) fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 200MHz) TWO-TONE IMD vs.
PAGE 6
Typical Operating Characteristics (continued) (AVDD = DVDD = VCLK = 3.3V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, TA = +25°C, unless otherwise noted.) 3 POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz, AOUT = 0dB FS, IOUT = 20mA) 2 1 DNL (LSB) 0 -1 0 -1 -2 -2 -3 -4 -3 0 170 POWER DISSIPATION (mW) 2 1 190 MAX5885 toc11 3 MAX5885 toc10 4 DIFFERENTIAL NONLINEARTIY vs. DIGITAL INPUT CODE MAX5885 toc12 INTEGRAL NONLINEARITY vs.
PAGE 7
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs PIN NAME 1 B1 Data Bit 1 FUNCTION 2 B0 Data Bit 0 (LSB) 3 XOR XOR Input Pin. XOR = 1 inverts the digital input data. XOR = 0 leaves the digital input data unchanged. XOR has an internal pulldown resistor and may be left unconnected if not used. 4, 9 VCLK Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a 0.1µF capacitor to the nearest CLKGND.
PAGE 8
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs MAX5885 Pin Description (continued) PIN NAME FUNCTION 38 B10 Data Bit 10 39 B9 Data Bit 9 40 B8 Data Bit 8 41 B7 Data Bit 7 44 B6 Data Bit 6 45 B5 Data Bit 5 46 B4 Data Bit 4 47 B3 Data Bit 3 48 B2 Data Bit 2 DVDD DGND SEL0 PD FUNCTION SELECTION BLOCK 1.
PAGE 9
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs Architecture The MAX5885 is a high-performance, 16-bit, currentsteering DAC (Figure 1) capable of operating with clock speeds up to 200MHz. The converter consists of separate input and DAC registers, followed by a current-steering circuit. This circuit is capable of generating differential full-scale currents in the range of 2mA to 20mA.
PAGE 10
MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs Although not recommended because of additional noise pickup from the ground plane, for single-ended operation IOUTP should be selected as the output, with IOUTN connected to AGND. Note that a single-ended output configuration has a higher 2nd-order harmonic distortion at high output frequencies than a differential output configuration. Figure 3 displays a simplified diagram of the MAX5885’s internal output structure.
PAGE 11
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs B0 TO B15 OUTPUT DATA IS UPDATED ON THE FALLING EDGE OF CLKP N N-1 tSETUP MAX5885 DIGITAL DATA IS LATCHED ON THE RISING EDGE OF CLKP N+1 tHOLD N+2 tCH tCL CLKP CLKN tPD IOUT N-5 N-4 N-3 N-2 N-1 Figure 5. Detailed Timing Relationship Power-Down Operation (PD) The MAX5885 also features an active-high power-down mode, which allows the user to cut the DAC’s current consumption.
PAGE 12
MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs AVDD DVDD VCLK 50Ω T2, 1:1 VOUT, SINGLE ENDED IOUTP B0–B15 100Ω MAX5885 IOUTN 16 T1, 1:1 AGND DGND CLKGND 50Ω WIDEBAND RF TRANSFORMER T2 PERFORMS THE DIFFERENTIAL TO SINGLE-ENDED CONVERSION. Figure 6. Differential to Single-Ended Conversion Using a Wideband RF Transformer AVDD DVDD VCLK 50Ω OUTP IOUTP B0–B15 100Ω MAX5885 IOUTN 16 AGND DGND CLKGND OUTN 50Ω Figure 7.
PAGE 13
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs The transmitter sections of multicarrier base station transceiver systems for GSM/EDGE usually present communication DAC manufacturers with the difficult task of providing devices with higher resolution, while simultaneously reducing noise and spurious emissions over a desired bandwidth. To specify noise and spurious emissions from base stations, a GSM/EDGE Tx mask is used to identify the DAC requirements for these parameters.
PAGE 14
MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs Table 2. GSM/EDGE Noise Requirements for Multicarrier Systems NUMBER OF CARRIERS CARRIER POWER LEVEL (dB FS) DAC NOISE DENSITY REQUIREMENT (dB FS/Hz) 2 -6 -146 4 -12 -152 Another key factor in selecting the appropriate DAC for the Tx path of a multicarrier GSM/EDGE system is the converter’s ability to offer superior IMD and MTPR performance.
PAGE 15
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs MAX5885 FOUR-TONE MULTITONE POWER RATIO PLOT (fCLK = 150MHz, fCENTER = 31.9885MHz) 0 -10 AOUT = -12dB FS -20 OUTPUT POWER (dBm) harmonic distortion components and optimize the DAC’s dynamic performance. Digital signal paths should be kept short and run lengths matched to avoid propagation delay and data skew mismatches. The MAX5885 supports three separate power-supply inputs for analog (AVDD), digital (DVDD), and clock (VCLK) circuitry.
PAGE 16
MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
PAGE 17
3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs Commonly used in combination with W-CDMA, ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device.
PAGE 18
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32, 44, 48L QFN.EPS MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs PACKAGE OUTLINE 32,44,48L QFN, 7x7x0.90 MM 21-0092 H 1 2 U PACKAGE OUTLINE, 32,44,48L QFN, 7x7x0.