Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) QFN 68 Exposed Pad

General Description

The MAX5889 advanced 12-bit, 600Msps, digital-to-

analog converter (DAC) meets the demanding perfor-

mance requirements of signal synthesis applications

found in wireless base stations and other communica-

tions applications. Operating from 3.3V and 1.8V sup-

plies, the MAX5889 DAC supports update rates of

600Msps using high-speed LVDS inputs while consum-

ing only 292mW of power and offers exceptional

dynamic performance such as 79dBc spurious-free

dynamic range (SFDR) at f

OUT

= 30MHz.

The MAX5889 utilizes a current-steering architecture that

supports a 2mA to 20mA full-scale output current range,

and produces -2dBm to -22dBm full-scale output signal

levels with a double-terminated 50Ω load. The MAX5889

features an integrated 1.2V bandgap reference and con-

trol amplifier to ensure high-accuracy and low-noise per-

formance. A separate reference input (REFIO) allows for

the use of an external reference source for optimum flexi-

bility and improved gain accuracy.

The MAX5889 digital inputs accept LVDS voltage lev-

els, and the flexible clock input can be driven differen-

tially or single-ended, AC- or DC-coupled. The

MAX5889 is available in a 68-pin QFN package with an

exposed paddle (EP) and is specified for the extended

(-40°C to +85°C) temperature range.

Refer to the MAX5891 and MAX5890 data sheets for pin-

compatible 16-bit and 14-bit versions of the MAX5889.

Applications

Base Stations: Single-Carrier UMTS,

CDMA, GSM

Communications: Fixed Broadband Wireless

Access, Point-to-Point Microwave

Direct Digital Synthesis (DDS)

Cable Modem Termination Systems (CMTS)

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 600Msps Output Update Rate

♦ Low-Noise Spectral Density: -157dBFS/Hz at

OUT

= 36MHz

♦ Excellent SFDR and IMD Performance

SFDR = 79dBc at f

OUT

= 30MHz (to Nyquist)

SFDR = 67dBc at f

OUT

= 130MHz (to Nyquist)

IMD = -95dBc at f

OUT

= 30MHz

IMD = -70dBc at f

OUT

= 130MHz

♦ ACLR = 72dB at f

OUT

= 122.88MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ LVDS-Compatible Digital Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low 292mW Power Dissipation at 600Msps

♦ Compact (10mm x 10mm) QFN-EP Package

♦ Evaluation Kit Available (MAX5891EVKIT)

MAX5889

12-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3620; Rev 1; 3/07

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-

PACKAGE

PKG

CODE

MAX5889EGK-D

-40°C to +85°C 68 QFN-EP*

G6800-4

MAX5889EGK+D

-40°C to +85°C 68 QFN-EP*

G6800-4

MAX5889

1.2V

REFERENCE

REFIO

DACREF

FSADJ

CLK

INTERFACE

600MHz

12-BIT DAC

LATCH

LVDS

RECEIVER

D0–D11

LVDS DATA

INPUTS

POWER

DOWN

CLKP

CLKN

OUTP

OUTN

Functional Diagram

PART

RESOLUTION

(BITS)

UPDATE RATE

(Msps)

LOGIC INPUT

MAX5889

12 600 LVDS

MAX5890

14 600 LVDS

MAX5891

16 600 LVDS

Selector Guide

*EP = Exposed paddle.

D = Dry pack.

+Denotes lead-free package.

Pin Configuration appears at end of data sheet.

Summary of content (16 pages)

PAGE 1
KIT ATION EVALU LE B A IL A AV 19-3620; Rev 1; 3/07 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs The MAX5889 advanced 12-bit, 600Msps, digital-toanalog converter (DAC) meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and 1.
PAGE 2
MAX5889 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs ABSOLUTE MAXIMUM RATINGS AVDD1.8, DVDD1.8 to AGND, DGND, DACREF, and CGND.......................................................-0.3V to +2.16V AVDD3.3, DVDD3.3, AVCLK to AGND, DGND, DACREF, and CGND.........................................-0.3V to +3.9V REFIO, FSADJ to AGND, DACREF, DGND, and CGND ..........................-0.3V to (AVDD3.3 + 0.3V) OUTP, OUTN to AGND, DGND, DACREF, and CGND .......................................-1.
PAGE 3
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX5889 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = +25°C, unless otherwise noted.
PAGE 7
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs TTIIMD (dBc) -70 -80 -12dBFS -90 -100 -110 -120 0 40 80 120 ACLR = 72.0dB fCENTER = 122.88MHz -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 OUTPUT POWER (dBm) OUTPUT POWER (dBm) -6.5dBFS -60 200 160 MAX5889 toc07 MAX5889 toc06 -50 FOUR-CARRIER WCDMA ACLR (fCLK = 491.52MHz) SINGLE-CARRIER WCDMA ACLR (fCLK = 491.52MHz) MAX5889 toc08 TWO-TONE INTERMODULATION DISTORTION vs.
PAGE 8
MAX5889 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Pin Description 8 PIN NAME 1, 46, 48, 50, 52, 54, 56, 58, 60, 63, 65, 67 D0N, D11N, D10N, D9N, D8N, D7N, D6N, D5N, D4N, D3N, D2N, D1N 2–9 N.C. 10 DGND FUNCTION Differential Negative LVDS Inputs. Data bits D0–D11 (offset binary format). No Connection. Leave floating or connect to DGND. Digital Ground. Ground return for DVDD3.3 and DVDD1.8. 11 DVDD3.3 Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range.
PAGE 9
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Architecture The MAX5889 high-performance, 12-bit, current-steering DAC (see the Functional Diagram) operates with DAC update rates up to 600Msps. The current-steering array generates differential full-scale currents in the 2mA to 20mA range. An internal current-switching network, in combination with external 50Ω termination resistors, converts the differential output currents into a differential output voltage with a 0.
PAGE 10
MAX5889 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Data-Timing Relationship AVDD3.3 Figure 3 shows the timing relationship between digital LVDS data, clock, and output signals. The MAX5889 features a 2ns hold, a -1.2ns setup, and a 2.5ns propagation delay time. There is a 5.5 clock-cycle latency between data write operation and the corresponding analog output transition.
PAGE 11
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Clock Interface To achieve the best possible jitter performance, the MAX5889 features flexible differential clock inputs (CLKP, CLKN) that operate from a separate clock power supply (AVCLK). Use a low-jitter clock to reduce the DAC’s phase noise and wideband noise. To achieve the best DAC dynamic performance, the CLKP/CLKN input source must be designed carefully.
PAGE 12
MAX5889 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs 25Ω OUTP D0–D11 LVDS DATA INPUTS OUTP 50Ω MAX5889 OUTN OUTN 25Ω AGND Figure 6. Differential Output Configuration Grounding, Bypassing, and Power-Supply Considerations Grounding and power-supply decoupling strongly influence the MAX5889 performance. Unwanted digital crosstalk coupling through the input, reference, power supply, and ground connections affects dynamic performance.
PAGE 13
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.
PAGE 14
MAX5889 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs D8P D9N D9P D10N D10P D11N D11P N.C. N.C. N.C. AVCLK CGND CLKP CLKN CGND AVCLK AVDD1.8 Pin Configuration 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 D8N 52 34 AVDD1.8 D7P 53 33 AGND D7N 54 32 AVDD3.3 D6P 55 31 AVDD3.3 D6N 56 30 AGND D5P 57 29 OUTP D5N 58 28 OUTN D4P 59 27 AGND D4N 60 26 AVDD3.3 MAX5889 DVDD1.8 61 25 AVDD3.
PAGE 15
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs 68L QFN.EPS PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 ______________________________________________________________________________________ 15 MAX5889 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
PAGE 16
MAX5889 12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Revision History Pages changed at Rev 1: 1–7, 9, 12, 13, 15, 16 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.