Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) QFN 68 Exposed Pad

General Description

The MAX5891 advanced 16-bit, 600Msps, digital-to-

analog converter (DAC) meets the demanding perfor-

mance requirements of signal synthesis applications

found in wireless base stations and other communica-

tions applications. Operating from 3.3V and 1.8V sup-

plies, the MAX5891 DAC supports update rates of

600Msps using high-speed LVDS inputs while consum-

ing only 298mW of power and offers exceptional

dynamic performance such as 80dBc spurious-free

dynamic range (SFDR) at f

OUT

= 30MHz.

The MAX5891 utilizes a current-steering architecture that

supports a 2mA to 20mA full-scale output current range,

and produces -2dBm to -22dBm full-scale output signal

levels with a double-terminated 50Ω load. The MAX5891

features an integrated 1.2V bandgap reference and con-

trol amplifier to ensure high-accuracy and low-noise per-

formance. A separate reference input (REFIO) allows for

the use of an external reference source for optimum flexi-

bility and improved gain accuracy.

The MAX5891 digital inputs accept LVDS voltage lev-

els, and the flexible clock input can be driven differen-

tially or single-ended, AC- or DC-coupled. The

MAX5891 is available in a 68-pin QFN package with an

exposed paddle (EP) and is specified for the extended

(-40°C to +85°C) temperature range.

Refer to the MAX5890 and MAX5889 data sheets for pin-

compatible 14-bit and 12-bit versions of the MAX5891.

Applications

Base Stations: Single/Multicarrier UMTS,

CDMA, GSM

Communications: Fixed Broadband Wireless

Access, Point-to-Point Microwave

Direct Digital Synthesis (DDS)

Cable Modem Termination Systems (CMTS)

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 600Msps Output Update Rate

♦ Low Noise Spectral Density: -163dBFS/Hz at

OUT

= 36MHz

♦ Excellent SFDR and IMD Performance

SFDR = 80dBc at f

OUT

= 30MHz (to Nyquist)

SFDR = 71dBc at f

OUT

= 130MHz (to Nyquist)

IMD = -95dBc at f

OUT

= 30MHz

IMD = -70dBc at f

OUT

= 130MHz

♦ ACLR = 73dB at f

OUT

= 122.88MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ LVDS-Compatible Digital Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low 298mW Power Dissipation at 600Msps

♦ Compact (10mm x 10mm) QFN-EP Package

♦ Evaluation Kit Available (MAX5891EVKIT)

MAX5891

16-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3542; Rev 4; 2/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP

RANGE

PIN-

PACKAGE

PKG

CODE

M AX5891E GK-D

- 40°C to + 85°C

68 QFN -E P *

G6800- 4

M AX5891E GK+D

- 40°C to + 85°C

68 QFN -E P *

G6800- 4

MAX5891

1.2V

REFERENCE

REFIO

DACREF

FSADJ

CLK

INTERFACE

600MHz

16-BIT DAC

LATCH

LVDS

RECEIVER

D0–D15

LVDS DATA

INPUTS

POWER

DOWN

CLKP

CLKN

OUTP

OUTN

Functional Diagram

PART

RESOLUTION

(BITS)

UPDATE RATE

(Msps)

LOGIC INPUT

MAX5889

12 600 LVDS

MAX5890

14 600 LVDS

MAX5891

16 600 LVDS

Selector Guide

Pin Configuration appears at end of data sheet.

EP = Exposed paddle.

+ = Lead-free package.

D = Dry pack.

Summary of content (16 pages)

PAGE 1
KIT ATION EVALU LE B A IL A AV 19-3542; Rev 4; 2/07 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs The MAX5891 advanced 16-bit, 600Msps, digital-toanalog converter (DAC) meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and 1.
PAGE 2
MAX5891 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs ABSOLUTE MAXIMUM RATINGS AVDD1.8, DVDD1.8 to AGND, DGND, DACREF, and CGND.......................................................-0.3V to +2.16V AVDD3.3, DVDD3.3, AVCLK to AGND, DGND, DACREF, and CGND.........................................-0.3V to +3.9V REFIO, FSADJ to AGND, DACREF, DGND, and CGND ..........................-0.3V to (AVDD3.3 + 0.3V) OUTP, OUTN to AGND, DGND, DACREF, and CGND .......................................-1.
PAGE 3
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX5891 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Digital Supply Voltage Range SYMBOL IAVDD3.
PAGE 6
Typical Operating Characteristics (AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated, transformer-coupled output, IOUT = 20mA, TA = +25°C, unless otherwise noted.) SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 7
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs -60 -70 -80 -90 -100 -50 80 -60 75 -70 -80 -90 -100 -110 -110 -120 -120 -130 -130 fOUT = 10MHz 85 SFDR (dBc) -50 MAX5891 toc09 -40 OUTPUT POWER (dBm) OUTPUT POWER (dBm) -40 ACLR = 67.3dB fCENTER = 122.88MHz -30 90 MAX5891 toc08 ACLR = 72.3dB fCENTER = 122.88MHz -30 -20 MAX5891 toc07 -20 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (fCLK = 500MHz) FOUR-CARRIER WCDMA ACLR (fCLK = 491.
PAGE 8
MAX5891 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Pin Description PIN NAME FUNCTION 1, 3, 5, 7, 9, 46, 48, 50, 52, 54, 56, 58, 60, 63, 65, 67 D4N, D3N, D2N, D1N, D0N, D15N, D14N, D13N, D12N, Differential Negative LVDS Inputs. Data bits D0–D15 (offset binary format). D11N, D10N, D9N, D8N, D7N, D6N, D5N 2, 4, 6, 8, 45, 47, 49, 51, 53, 55, 57, 59, 62, 64, 66, 68 D3P, D2P, D1P, D0P, D15P, D14P, D13P, D12P, D11P, D10P, D9P, D8P, D7P, D6P, D5P, D4P 10 DGND Digital Ground.
PAGE 9
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Architecture The MAX5891 high-performance, 16-bit, current-steering DAC (see the Functional Diagram) operates with DAC update rates up to 600Msps. The current-steering array generates differential full-scale currents in the 2mA to 20mA range. An internal current-switching network, in combination with external 50Ω termination resistors, converts the differential output currents into a differential output voltage with a 0.
PAGE 10
MAX5891 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Data-Timing Relationship AVDD3.3 Figure 3 shows the timing relationship between digital LVDS data, clock, and output signals. The MAX5891 features a 2.6ns hold, a -1.5ns setup, and a 2.5ns propagation delay time. There is a 5.5 clock-cycle latency between data write operation and the corresponding analog output transition.
PAGE 11
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Clock Interface Use a pair of transformers (Figure 5) or a differential amplifier configuration to convert the differential voltage existing between OUTP and OUTN to a single-ended voltage. Optimize the dynamic performance by using a differential transformer-coupled output and limit the output power to < 0dBm full scale. To achieve the best dynamic performance, use the differential transformer configuration.
PAGE 12
MAX5891 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs 25Ω OUTP D0–D15 LVDS DATA INPUTS OUTP 50Ω MAX5891 OUTN OUTN 25Ω AGND Figure 6. Differential Output Configuration Grounding, Bypassing, and Power-Supply Considerations Grounding and power-supply decoupling strongly influence the MAX5891 performance. Unwanted digital crosstalk coupling through the input, reference, power supply, and ground connections affects dynamic performance.
PAGE 13
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.
PAGE 14
MAX5891 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs D4P D5N D5P D6N D6P D7N D7P DVDD1.8 D8N D8P D9N D9P D10N D10P D11N D11P D12N Pin Configuration 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 D4N 1 51 D12P D3P 2 50 D13N D3N 3 49 D13P D2P 4 48 D14N D2N 5 47 D14P D1P 6 46 D15N D1N 7 45 D15P D0P 8 D0N 44 N.C. MAX5891 9 43 N.C. 42 N.C. DGND 10 DVDD3.3 11 41 AVCLK PD 12 40 CGND N.C. 13 39 CLKP 38 CLKN AVDD3.
PAGE 15
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs 68L QFN.EPS ______________________________________________________________________________________ 15 MAX5891 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
PAGE 16
MAX5891 16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Revision History Pages changed at Rev 4: 2–5, 12, 13 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.