9-3631; Rev 2; 10/08 KIT ATION EVALU LE B A IL A AV 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Features The MAX5894 programmable interpolating, modulating, 500Msps, dual digital-to-analog converter (DAC) offers superior dynamic performance and is optimized for highperformance wideband, single-carrier transmit applications.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs ABSOLUTE MAXIMUM RATINGS DVDD1.8, AVDD1.8 to GND, DACREF ..................-0.3V to +2.16V AVDD3.3, AVCLK, DVDD3.3 to GND, DACREF ........-0.3V to +3.9V DATACLK, A0–A13, B0–B11, SELIQ/B13, DATACLK/B12, CS, RESET, SCLK, DIN and DOUT to GND, DACREF ...-0.3V to (DVDD3.3 + 0.3V) CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V) REFIO, FSADJ to GND, DACREF ........-0.3V to (AVDD3.3 + 0.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50Ω double-terminated outputs, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50Ω double-terminated outputs, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50Ω double-terminated outputs, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs ELECTRICAL CHARACTERISTICS (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port mode, 50Ω double-terminated outputs, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs -6dBFS 80 -12dBFS 40 -6dBFS -12dBFS 50 40 0 10 20 30 40 50 40 0 10 20 UPPER SIDEBAND MODULATION SPURS MEASURED BETWEEN 62.5MHz AND 125MHz 10 SPURS MEASURED BETWEEN 62.5MHz AND 125MHz 10 0 0 -0.1dBFS 20 20 SPURS MEASURED BETWEEN 0MHz AND 62.5MHz -12dBFS 50 30 30 20 0 30 62.5 50 40 72.5 82.5 92.5 102.5 112.5 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) IN-BAND SFDR vs.
Typical Operating Characteristics (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, output is transformer-coupled to 50Ω load, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE DNL (LSB) 0.075 0.050 0.025 1.5 0.50 1.0 0.25 0.5 0 -40 -15 10 35 60 0 -0.25 -0.5 -0.50 -1.0 -0.75 -1.5 -1.00 0 -2.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs 50 TWO-CARRIER ALTERNATE CHANNEL MAX5894 toc18 -60 -70 -80 -90 -100 50 ACLR2 = 77dB 60 TWO-CARRIER ALTERNATE CHANNEL -50 ACLR1 = 75dB TWO-CARRIER ADJACENT CHANNEL 70 TWO-CARRIER ADJACENT CHANNEL -40 CARRIER = -11dBm ACLR (dB) ACLR (dB) 70 -30 ACLR1 = 76dB 80 80 60 ONE-CARRIER ALTERNATE CHANNEL ACLR2 = 78dB 90 -20 OUTPUT POWER (dBm) ONE-CARRIER ALTERNATE CHANNEL ONE-CARRIER ADJACENT CHANNEL MAX5894 toc17 ON
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Pin Description PIN NAME FUNCTION 1 CLKP Noninverting Differential Clock Input. Internally biased to AVCLK/2. 2 CLKN Inverting Differential Clock Input. Internally biased to AVCLK/2. 3, 4, 5, 24, 25, 42, 43 N.C. 6, 21, 30, 37 DVDD1.8 Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a 0.1µF capacitor as close to the pin as possible.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs PIN NAME FUNCTION 53, 67 AVDD1.8 54, 56, 59, 61, 64, 66 GND 55, 60, 65 AVDD3.3 Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a 0.1µF capacitor as close to the pin as possible.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Detailed Description The MAX5894 dual, 500Msps, high-speed, 14-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5894 combines two DAC cores with 8x/4x/2x/1x programmable digital interpolation filters, a digital quadrature modulator, an SPIcompatible serial interface for programming the device, and an on-chip 1.20V reference.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs read operation. The most significant bit (MSB) is shifted in first in default mode. If the serial port is set to LSB-first mode, both the control byte and data byte are shifted LSB in first. Figures 1 and 2 show the SPI serial-interface operation in the default write and read mode, respectively. Figure 3 is a timing diagram for the SPI serial interface.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs tSS CS SCLK tSDH tSDS DIN tSDV DOUT Figure 3.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs of the registers. The following are descriptions of each register. Table 2.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs e -jw (default), cancelling the upper image when used with an external quadrature modulator. A logic 1 sets the complex modulation to be e+jw, cancelling the lower image when used with an external quadrature modulator. Address 00h Bit 6 Logic 0 (default) causes the serial port to use MSB first address/data format. When set to a logic 1, the serial port uses LSB first address/ data format.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Address 09h Bits 3–0 These four bits define the binary number for the coarse-gain adjustment of the QDAC fullscale current (see the Gain Adjustment section). Bit 3 is the MSB. Default is all ones. Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0 These 10 bits represent a binary number that defines the magnitude of the offset added to the QDAC output (see the Offset Adjustment section). Default is all zeros.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs tionship and detects if the phase drifts more than ±1 data clock cycle. If this occurs, the synchronizer automatically re-establishes synchronization. However, during the resynchronization phase, up to 8 data words may be lost or repeated. Bit 2 of register 02h disables or enables (default) the automatic data clock phase detection.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs 0 0 -20 -20 PASSBAND DETAIL -40 0 GAIN (dBFS) GAIN (dBFS) ter is located after the modulator. In the 8x interpolation mode, the last filter (FIR3) can be configured as lowpass or highpass (bit 5, address 01h) to select the lower or upper sideband from the modulation output. The frequency responses of these three filters are plotted in Figures 5–8. -0.0002 -60 -0.0004 0.4 0.3 0.2 0.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs The programmable interpolation filters multiply the MAX5894 input data rate by a factor of 2x, 4x, or 8x to separate the reconstructed waveform spectrum and the DAC image. The original spectral images, appearing at around multiples of the input data rate, are attenuated by the internal digital filters. This feature provides three benefits: 1) Image separation reduces complexity of analog reconstruction filters.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL FILTER RESPONSE IMAGE 2fS fS OUTPUT SPECTRUM OF THE FIRST FILTER SIGNAL SIGNAL FILTER RESPONSE 4fS 2x INTERPOLATION 3fS 4fS 3fS 4fS IMAGE 2fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 3fS 2fS fS OUTPUT SPECTRUM OF THE SECOND FILTER NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RESPONSE 10fS, etc.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL fS OUTPUT SPECTRUM OF THE FIRST FILTER 2fS SIGNAL SIGNAL 4fS 5fS 6fS 7fS 8fS 2x INTERPOLATION 3fS 4fS 2fS 5fS 6fS 7fS 8fS 5fS 6fS 7fS 8fS FILTER RESPONSE IMAGE 3fS 4fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 3fS 2fS fS OUTPUT SPECTRUM OF THE SECOND FILTER NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RE
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs fS OUTPUT SPECTRUM OF THE FIRST FILTER 2fS SIGNAL 2fS SIGNAL 2fS 5fS 6fS 7fS 8fS 2x INTERPOLATION 3fS 4fS 5fS 6fS 7fS 8fS 6fS 7fS 8fS FILTER RESPONSE 3fS 4fS 5fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 4fS IMAGE fS OUTPUT SPECTRUM OF THE SECOND FILTER 3fS NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RESPONSE FILTER RESPONSE IMAGE LOWER SIDEBAND 2fS 3fS
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Digital Modulator The MAX5894 features digital modulation at frequencies of fIM/2 and fIM/4, where fIM is the data rate at the input to the modulator. fIM equals fDAC in 1x, 2x, and 4x interpolation modes. In 8x interpolation mode, fIM equals fDAC/2. The output rate of the modulator is always the same as the input data rate to the modulator.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Data Clock The MAX5894 features synchronizers that allow for arbitrary phase alignment between DATACLK and CLKP/CLKN. The DATACLK causes internal switching in the MAX5894 and the phase between DATACLK (input mode) to CLKP/CLKN influences the images at DATACLK. Optimum image rejection is achieved when DATACLK transitions are aligned with the falling edge of CLKP.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs sources directly to the device without external resistors to define the DC level. The input resistance of CLKP and CLKN is 5kΩ. A convenient way to apply a differential signal is with a balun transformer as shown in Figure 15. Alternatively, these inputs may be driven from a CMOS-compatible 100nF CLKP SINGLE-ENDED IINPUT MINI-CIRCUITS ADTL1-12 24.9Ω MAX5894 1:1 RATIO 24.9Ω 100nF CLKN Figure 15.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Reference Input/Output The MAX5894 supports operation with the on-chip 1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the DAC is operating with the internal reference. For stable operation with the internal reference, REFIO should be decoupled to GND with a 1µF capacitor.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs REFIO must be buffered with an external amplifier, if heavy loading is required, due to its 10kΩ output resistance. Alternatively, apply a temperature-stable external reference to REFIO (Figure 18). The internal reference is overdriven by the external reference. For improved accuracy and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Grounding and power-supply decoupling strongly influence the MAX5894 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5894.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset.
14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs 63 62 61 60 59 58 AVDD1.8 FSADJ GND AVDD3.3 GND OUTQN OUTQP GND AVDD3.3 GND OUTIN GND 67 66 65 64 OUTIP AVDD3.3 AVDD1.8 68 GND AVCLK TOP VIEW 57 56 55 54 53 52 EXPOSED PAD CLKP 1 CLKN 2 50 REFIO N.C. 3 49 RESET N.C. 4 48 CS N.C. 5 47 SCLK DVDD1.8 6 46 DIN A13 7 45 DOUT A12 8 A11 9 51 DACREF 44 DVDD3.3 MAX5894 43 N.C. A10 10 42 N.C. A9 11 41 B0 A8 12 DVDD3.
MAX5894 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 — Initial release — 1 4/07 — — 2 10/08 Add note to setup and hold specifications. 5, 6 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
