Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) QFN 68 Exposed Pad

General Description

The MAX5898 programmable interpolating, modulating,

500Msps, dual digital-to-analog converter (DAC) offers

superior dynamic performance and is optimized for high-

performance wideband, single- and multicarrier transmit

applications. The device integrates a selectable 2x/4x/8x

interpolating filter, a digital quadrature modulator, and

dual 16-bit, high-speed DACs on a single integrated cir-

cuit. At 30MHz output frequency and 500Msps update

rate, the in-band SFDR is 81dBc, while only consuming

1.2W. The device also delivers 71dB ACLR for four-

carrier WCDMA at a 61.44MHz output frequency.

The selectable interpolating filters allow lower input data

rates while taking advantage of the high DAC update

rates. These linear-phase interpolation filters ease recon-

struction filter requirements and enhance the passband

dynamic performance. Each channel includes offset and

gain programmability, allowing the user to calibrate out

local oscillator (LO) feedthrough and sideband suppres-

sion errors generated by analog quadrature modulators.

The MAX5898 features a f

/ 4 digital image-reject

modulator. This modulator generates a quadrature-mod-

ulated IF signal that can be presented to an analog I/Q

modulator to complete the upconversion process. A

second digital modulation mode allows the signal to be

frequency-translated with image pairs at f

/ 2 or f

/ 4.

The MAX5898 features a standard LVDS interface for

low electromagnetic interference (EMI). Interleaved

data is applied through a single 16-bit bus. A 3.3V

SPI™ port is provided for mode configuration. The pro-

grammable modes include the selection of 2x/4x/8x

interpolating filters, f

/ 2, f

/ 4 or no digital quadra-

ture modulation with image rejection, individual channel

gain and offset adjustment, and offset binary or two’s-

complement data interface.

Compatible versions with CMOS interfaces and 12-, 14-,

and 16-bit resolutions are also available. Refer to the

MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14-

bit CMOS, and the MAX5895 for 16-bit CMOS versions.

Applications

Base Stations: 3G Multicarrier UMTS, CDMA, and GSM

Broadband Wireless Transmitters

Broadband Cable Infrastructure

Instrumentation and Automatic Test Equipment (ATE)

Analog Quadrature Modulation Architectures

Features

o 71dB ACLR at f

OUT

= 61.44MHz (Four-Carrier

WCDMA)

o Meets Multicarrier UMTS, cdma2000

, GSM

Spectral Masks (f

OUT

= 122MHz)

o Noise Spectral Density = -160dBFS/Hz at

OUT

= 16MHz

o 90dBc SFDR at Low-IF Frequency (10MHz)

o 88dBc SFDR at High-IF Frequency (50MHz)

o Low Power: 831mW (f

CLK

= 250MHz)

o User Programmable

Selectable 2x, 4x, or 8x Interpolating Filters

< 0.01dB Passband Ripple

> 95dB Stopband Rejection

Selectable Real or Complex Modulator Operation

Selectable Modulator LO Frequency: OFF, f

/ 2,

or f

/ 4

Selectable Output Filter: Lowpass or Highpass

Per Channel Gain and Offset Adjustment

o EV Kit Available (Order the MAX5898EVKIT)

MAX5898

16-Bit, 500Msps, Interpolating and Modulating

Dual DAC with Interleaved LVDS Inputs

________________________________________________________________

Maxim Integrated Products

PART

RESOLUTION

(BITS)

DAC UPDATE

RATE (Msps)

INPUT

LOGIC

MAX5893 12 500 CMOS

MAX5894 14 500 CMOS

MAX5895 16 500 CMOS

MAX5898 16 500 LVDS

PART TEMP RANGE PIN-PACKAGE

M AX 5898E GK+ D -40°C to +85°C

68 QFN-EP*

(10mm x 10mm)

M AX 5898E GK- D -40°C to +85°C

68 QFN-EP*

(10mm x 10mm)

Selector Guide

Ordering Information

DATA SYNCH

AND DEMUX

DAC

DATA PORT

DATACLK

OUTI

OUTQ

MODULATOR

INTERPOLATING

FILTERS

1x/2x/4x

INTERPOLATING

FILTERS

DAC

Simplified Diagram

19-3756; Rev 2; 8/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.

cdma2000 is a registered trademark of Telecommunications

Industry Association.

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed paddle.

D = Dry pack

EVALUATION KIT

AVAILABLE

Summary of content (33 pages)

PAGE 1
9-3756; Rev 2; 8/10 KIT ATION EVALU LE B A IL A AV 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Features The MAX5898 programmable interpolating, modulating, 500Msps, dual digital-to-analog converter (DAC) offers superior dynamic performance and is optimized for highperformance wideband, single- and multicarrier transmit applications.
PAGE 2
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs ABSOLUTE MAXIMUM RATINGS DOUT, DATACLKP, DATACLKN Continuous Current ..........8mA Continuous Power Dissipation (TA = +70°C) 68-Pin QFN (derate 41.7mW/°C above +70°C) (Note 1) ...................................................................3333.3mW Junction Temperature ......................................................+150°C Operating Temperature Range ...........................
PAGE 3
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is 50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER In-Band SFDR (DC to fDATA / 2) SYMBOL SFDR CONDITIONS Four-Tone IMD TTIMD FTIMD fDATA = 125Mwps, interpolation off, -0.
PAGE 4
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is 50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
PAGE 5
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is 50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL Rise/Fall Time CONDITIONS MIN CLOAD = 10pF, 20% to 80% TYP MAX 1.
PAGE 6
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs ELECTRICAL CHARACTERISTICS (continued) (DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is 50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.
PAGE 7
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs -6dBFS -0.1dBFS 100 -12dBFS -0.1dBFS 40 20 20 0 10 20 30 40 50 60 60 -0.1dBFS 50 40 30 20 SPURS MEASURED BETWEEN 0MHz AND 62.5MHz 0 10 20 SPURS MEASURED BETWEEN 62.5MHz AND 125MHz 10 0 30 40 0 50 10 20 30 40 50 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) IN-BAND SFDR vs. OUTPUT FREQUENCY fDATA = 125Mwps, 2x INTERPOLATION IN-BAND SFDR vs.
PAGE 8
Typical Operating Characteristics (continued) -6dBFS -60 -12dBFS -80 MAX5898 toc11 0.100 GAIN MISMATCH (dB) -40 -6dBFS -60 -12dBFS -80 -6dBFS -6dBFS -120 -120 10 25 40 55 70 85 0 10 35 60 85 110 135 160 -40 -15 10 35 60 CENTER FREQUENCY (MHz) TEMPERATURE (°C) EIGHT-TONE POWER RATIO PLOT fDATA = 125Mwps, 2x INTERPOLATION DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 2.5 4.0 3.0 2.0 -60 -70 -80 2.0 1.
PAGE 9
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs -120 -140 8x INTERPOLATION -150 70 FOUR-CARRIER ALTERNATE CHANNEL 60 50 -170 100 200 300 400 500 61.44 92.16 122.88 0 153.60 15.36 30.72 46.08 61.44 76.80 92.16 107.50 fCENTER (MHz) WCDMA ACLR SPECTRAL PLOT fDATA = 61.44Mwps, 8x INTERPOLATION FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT fDATA = 61.44Mwps, 8x INTERPOLATION WCDMA ACLR SPECTRAL PLOT fDATA = 122.
PAGE 10
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs MAX5898 Pin Description PIN NAME 1 CLKP 2 CLKN 3 N.C. 4 DATACLKP 5 DATACLKN FUNCTION Noninverting Differential Clock Input. Internally biased to AVCLK / 2. Inverting Differential Clock Input. Internally biased to AVCLK / 2. Internally Connected. Do not connect. LVDS Data Clock Input/Output. External 100Ω termination to DATACLKN required. Complementary LVDS Data Clock Input/Output.
PAGE 11
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs PIN NAME 35 D3N Complementary LVDS Data Bit 3. Internal 110Ω termination to D3P. 36 D3P LVDS Data Bit 3. Internal 110Ω termination to D3N. 38 D2N Complementary LVDS Data Bit 2. Internal 110Ω termination to D2P. 39 D2P LVDS Data Bit 2. Internal 110Ω termination to D2N. 40 D1N Complementary LVDS Data Bit 1. Internal 110Ω termination to D1P. 41 D1P LVDS Data Bit 1. Internal 110Ω termination to D1N.
PAGE 12
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs MAX5898 Functional Diagram MODULATOR MUX MUX 2x INTERPOLATING FILTER MUX 2x INTERPOLATING FILTER 2x INTERPOLATING FILTER ∑ DIGITAL OFFSET ADJUST DIGITAL GAIN ADJUST OUTIP ∑ IDAC OUTIN D0–D15 fDAC DATA SYNCH AND DEMUX DATACLK I Q fIM / 2, fIM / 4 I Q DIGITAL OFFSET ADJUST MUX MUX MUX ∑ 2x INTERPOLATING FILTER 2x INTERPOLATING FILTER 2x INTERPOLATING FILTER SELIQ MAX5898 DIGITAL GAIN ADJUST OUTQP ∑
PAGE 13
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Serial Interface The SPI-compatible serial interface programs the MAX5898 registers. The serial interface consists of CS, DIN, SCLK, and DOUT. Data is shifted into DIN on the rising edge of SCLK when CS is low. When CS is high, data presented at DIN is ignored and DOUT is in highimpedance mode. Note: CS must transition high after each read/write operation.
PAGE 14
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs CS READ CYCLE N - 1 READ CYCLE N READ CYCLE N + 1 SCLK DIN DOUT ADDRESS 1 0 0 0 3 2 1 0 HIGH IMPEDANCE DATA IGNORED ADDRESS 1 0 0 0 3 2 1 0 HIGH IMPEDANCE DATA N - 2 DATA IGNORED DATA N - 1 ADDRESS 1 0 0 0 3 2 1 0 HIGH IMPEDANCE DATA IGNORED DATA N Figure 2. SPI Serial-Interface Read Cycle, MSB-First Mode tSS CS SCLK tSDH tSDS DIN tSDV DOUT Figure 3.
PAGE 15
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs of the registers. The following are descriptions of each register. Table 2.
PAGE 16
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Address 00h Bit 6 Logic 0 (default) causes the serial port to use MSB first address/data format. When set to a logic 1, the serial port uses LSB first address/ data format. Bit 5 When set to a logic 1 (default = 0), all registers reset to their default state (this bit included). Bit 4 Logic 1 (default = 0) stops the clock to the digital interpolators. DAC outputs hold last value prior to interpolator power-down.
PAGE 17
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Address 09h Bits 3–0 These four bits define the binary number for the coarse-gain adjustment of the QDAC fullscale current (see the Gain Adjustment section). Bit 3 is the MSB. Default is all ones. Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0 These 10 bits represent a binary number that defines the magnitude of the offset added to the QDAC output (see the Offset Adjustment section). Default is all zeros.
PAGE 18
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs DATACLK Modes The MAX5898 employs a differential LVDS DATACLK located at pins 4 and 5. The DATACLK can be configured as either an input or as an output (bit 3, address 02h). If DATACLK is configured as an output, it is frequency-divided from the CLKP/CLKN input, depending on the operating mode, see Table 4.
PAGE 19
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs ter is located after the modulator. In the 8x interpolation mode, the last filter (FIR3) can be configured as lowpass or highpass (bit 5, address 01h) to select the lower or upper sideband from the modulation output. The frequency responses of these three filters are plotted in Figures 5–8. 0 0 -20 -20 PASSBAND DETAIL 0 -0.0002 -60 -0.0004 0.3 0.2 0.1 0 0.
PAGE 20
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs The programmable interpolation filters multiply the MAX5898 input data rate by a factor of 2x, 4x, or 8x to separate the reconstructed waveform spectrum and the DAC image. The original spectral images, appearing at around multiples of the input data rate, are attenuated by the internal digital filters. This feature provides three benefits: 1) Image separation reduces complexity of analog reconstruction filters.
PAGE 21
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL FILTER RESPONSE IMAGE 2fS fS OUTPUT SPECTRUM OF THE FIRST FILTER SIGNAL SIGNAL FILTER RESPONSE 4fS 2x INTERPOLATION 3fS 4fS 3fS 4fS IMAGE 2fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 3fS 2fS fS OUTPUT SPECTRUM OF THE SECOND FILTER NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RESPONSE 10fS, etc.
PAGE 22
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs INPUT SPECTRUM AND FIRST FILTER RESPONSE SIGNAL fS OUTPUT SPECTRUM OF THE FIRST FILTER 2fS SIGNAL SIGNAL 4fS 5fS 6fS 7fS 8fS 2x INTERPOLATION 3fS 4fS 2fS 5fS 6fS 7fS 8fS 5fS 6fS 7fS 8fS FILTER RESPONSE IMAGE 3fS 4fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 3fS 2fS fS OUTPUT SPECTRUM OF THE SECOND FILTER NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SEC
PAGE 23
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs IMAGE fS OUTPUT SPECTRUM OF THE FIRST FILTER 2fS SIGNAL 2fS SIGNAL 2fS 5fS 6fS 7fS 8fS 2x INTERPOLATION 3fS 4fS 5fS 6fS 7fS 8fS 6fS 7fS 8fS FILTER RESPONSE 3fS 4fS 5fS SIGNAL 4x INTERPOLATION IMAGE fS OUTPUT SPECTRUM OF THE MODULATOR 4fS IMAGE fS OUTPUT SPECTRUM OF THE SECOND FILTER 3fS NO INTERPOLATION IMAGE fS INPUT SPECTRUM AND SECOND FILTER RESPONSE FILTER RESPONSE LOWER SIDEBAND
PAGE 24
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Digital Modulator The MAX5898 features digital modulation at frequencies of fIM / 2 and fIM / 4, where fIM is the data rate at the input to the modulator. fIM equals fDAC in 1x, 2x, and 4x interpolation modes. In 8x interpolation mode, fIM equals fDAC / 2. The output rate of the modulator is always the same as the input data rate to the modulator, fIM.
PAGE 25
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Data Clock The MAX5898 features synchronizers that allow for arbitrary phase alignment between DATACLK and CLKP/CLKN. The DATACLK causes internal switching in the MAX5898 and the phase between DATACLK (input mode) to CLKP/CLKN influences the images at DATACLK.
PAGE 26
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs sources directly to the device without external resistors to define the DC level. The input resistance of CLKP and CLKN is 5kΩ. A convenient way to apply a differential signal is with a balun transformer as shown in Figure 15.
PAGE 27
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs 25Ω OUTIP IDAC 50Ω 16 OUTIN 25Ω MAX5898 25Ω OUTQP QDAC 50Ω 16 OUTQN 25Ω Reference Input/Output The MAX5898 supports operation with the on-chip 1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the DAC is operating with the internal reference.
PAGE 28
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs 1.2V REFERENCE 1.2V REFERENCE MAX5898 MAX5898 10kΩ 10kΩ EXTERNAL 1.25V REFERENCE REFIO REFIO 1µF 1µF FSADJ FSADJ CURRENTSOURCE ARRAY DAC IREF RSET CURRENTSOURCE ARRAY DAC IREF RSET DACREF DACREF Figure 18. Typical External Reference Circuit Figure 19. Internal Reference Architecture Table 5. IOUTFS and RSET Selection Matrix Based on a Typical 1.
PAGE 29
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.
PAGE 30
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Pin Configuration 63 62 61 60 59 58 AVDD1.8 FSADJ GND AVDD3.3 GND OUTQN OUTQP GND AVDD3.3 GND OUTIN GND 67 66 65 64 OUTIP AVDD3.3 AVDD1.8 68 GND AVCLK TOP VIEW 57 56 55 54 53 52 EXPOSED PADDLE CLKP 1 CLKN 2 50 REFIO N.C. 3 49 RESET DATACLKP 4 48 CS DATACLKN DVDD1.8 5 47 SCLK 6 46 DIN SELIQN 7 45 DOUT SELIQP 8 D15N 9 51 DACREF 44 DVDD3.
PAGE 31
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 68 QFN (10mm x 10mm) G6800+4 21-0122 — ______________________________________________________________________________________ 31 MAX5898 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
PAGE 32
MAX5898 16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PAGE 33
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs REVISION NUMBER REVISION DATE 0 8/05 Initial release 1 7/07 Add note to EC Table, style edits 2 8/10 Update Absolute Maximum Ratings DESCRIPTION PAGES CHANGED — 1, 2, 4, 5, 27, 28, 31 1, 2, 32 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.