9-5568; Rev 1; 9/11 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Features The MAX5980 is a quad, power-sourcing equipment (PSE) power controller designed for use in IEEE® 802.3at/af-compliant PSE. This device provides powered device (PD) discovery, classification, current limit, and load disconnect detection. The device supports both fully automatic operation and software programmability.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VEE, unless otherwise noted.) AGND.....................................................................-0.3V to +80V DGND, SVEE_.......................................................-0.3V to +0.3V VDD. ....................... -0.3V to the lower (VAGND + 0.3V) and +4V OUT_.....................................................-0.3V to (VAGND + 0.3V) GATE_, SENSE_..............................
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet (VAGND = 32V to 60V, VEE = VDGND = 0V, TA = -40NC to +105NC. All voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = 54V, TA = +25NC, and default register settings. Currents are positive when entering the pin, and negative otherwise.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued) (VAGND = 32V to 60V, VEE = VDGND = 0V, TA = -40NC to +105NC. All voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = 54V, TA = +25NC, and default register settings. Currents are positive when entering the pin, and negative otherwise.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet (VAGND = 32V to 60V, VEE = VDGND = 0V, TA = -40NC to +105NC. All voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = 54V, TA = +25NC, and default register settings. Currents are positive when entering the pin, and negative otherwise.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued) (VAGND = 32V to 60V, VEE = VDGND = 0V, TA = -40NC to +105NC. All voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = 54V, TA = +25NC, and default register settings. Currents are positive when entering the pin, and negative otherwise.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet TA = +25°C 2.8 2.4 TA = -40°C 40 44 48 52 56 3.1 29.0 28.5 0 5 10 -40 20 15 -15 10 35 60 85 TOTAL CURRENT LOAD (mA) TEMPERATURE (°C) ANALOG SUPPLY OVERVOLTAGE LOCKOUT vs. TEMPERATURE GATE OVERDRIVE VOLTAGE vs. ANALOG SUPPLY VOLTAGE GATE OVERDRIVE VOLTAGE vs. TEMPERATURE 62.0 61.5 9.3 9.2 9.1 10 35 60 85 MAX5980 toc05b 9.3 9.2 9.1 32 110 36 40 44 48 52 56 60 8.
Typical Operating Characteristics (continued) (VAGND = 32V to 60V, VEE = VDGND = 0V, TA = -40NC to +105NC. All voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = 54V, TA = +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless otherwise noted.) DC LOAD DISCONNECT SENSE_ THRESHOLD vs. TEMPERATURE OVERCURRENT TIMEOUT (RLOAD = 240I TO 140I) MAX5980 toc09 MAX5980 toc08 2.4 DISCONNECT THRESHOLD (mV) MAX5980 Quad, IEEE 802.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet EN TO HARDWARE POWER-DOWN DELAY ZERO CURRENT DETECTION MAX5980 toc14 MAX5980 toc15 VAGND - VOUT_ 50V/div 0V VAGND - VOUT_ 20V/div 0V VGATE_ 5V/div 0V IOUT_ 100mA/div 0mA VEN 2V/div 0V VGATE_ 10V/div 0V 100µs/div 100ms/div STARTUP WITH VALID PD (25kI, 0.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Typical Operating Characteristics (continued) (VAGND = 32V to 60V, VEE = VDGND = 0V, TA = -40NC to +105NC. All voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = 54V, TA = +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless otherwise noted.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet DETECTION IN MIDSPAN MODE WITH INVALID PD (33kI AND 0.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Pin Configuration SENSE1 OUT2 GATE2 SENSE2 OUT3 GATE3 SENSE3 OUT4 TOP VIEW 24 23 22 21 20 19 18 17 GATE1 25 16 GATE4 OUT1 26 15 SENSE4 N.C. 27 14 AGND SVEE1 28 13 N.C.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet PIN NAME FUNCTION 11 VEE Analog Low-Side Supply Input. Bypass with an external 100V, 0.1FF ceramic capacitor between AGND and VEE. 12 VDD Digital High-Side Supply Output. Bypass with an external RC network; see the VDD Power Supply section for details. 13, 27 N.C. No Connection. Not internally connected. Leave N.C. unconnected. 14 AGND 15, 18, 21, 24 SENSE4, SENSE3, SENSE2, SENSE1 Current-Sense Positive Terminal Inputs.
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet The MAX5980 is a quad PSE power controller designed for use in IEEE 802.3at/af-compliant PSE. This device provides PD discovery, classification, current limit, and load disconnect detections. The device supports both fully automatic operation and software programmability. The device also supports new 2-event classification and Class 5 for detection and classification of high-power PDs.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Semiautomatic (Semi) Mode Enter semiautomatic mode by setting the port operating mode (R12h, Table 19) to [10]. When entering semi mode, the DET_EN_ and CLASS_EN_ bits retain their previous states. When the DET_EN_ and/or CLASS_EN_ bits are set to 1, the MAX5980 performs detection and/or classification repeatedly, but do not power up the port(s) automatically.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet If EN_CL5 is left unconnected, the device will classify the PD based on Table 33-9 of the IEEE 802.3at standard (see Table 2). If the measured current exceeds 51mA, the device will not power the PD, but will report an overcurrent classification result and will return to IDLE state before attempting a new detection cycle. High-Capacitance Detection High-capacitance detection for legacy PDs is software programmable.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet 80ms 150ms 150ms 19ms tDET(1) tDET(2) tCLASS t 0V -4V -9.1V -18V -54V VOUT_ - VAGND Figure 1. Detection, Classification, and Port Power-Up Sequence 2-Event PD Classification If the result of the first classification event is Class 0 to 3, then only a single classification event occurs as shown in Figure 1.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet 9ms 150ms 150ms 19ms 19ms tDET(1) tDET(2) tCLASS(1) tCLASS(2) t 0V -4V -9.1V -18V -54V VOUT_ - VAGND Figure 2. Detection, 2-Event Classification, and Port Power-Up Sequence VRSENSE_ exceeds VCUT and decreases at a slower pace when VRSENSE_ drops below VCUT. A slower decrement for the tFAULT counter allows for detecting repeated short-duration overcurrent conditions.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet VSENSE_ - VEE VSU_LIM 212.5mV CLASS 4 VSU_LIM 106.25mV CLASS 0 –3 VTH_FB 35mV VFLBK_ST 18V VFLBK_ST 32V VFLBK_END 46V VOUT_ - VEE Figure 3. Foldback Current Characteristics Foldback Current During startup and normal operation, an internal circuit senses the voltage at OUT_ and when necessary reduces the current-limit clamp voltage (VSU_LIM) to help reduce the power dissipation through the external FET.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet DC Disconnect Monitoring The DC disconnect monitoring settings are found in the Disconnect Enable register (R13h, Table 21). To enable DC disconnect, set either the ACD_EN_ or DCD_EN_ bit for the corresponding port to 1. To disable the DC disconnect monitoring, both the ACD_EN_ and DCD_EN_ bit for that port must be set to 0.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet SDA/SDAIN tBUF tSU, DAT tSU, STA tLOW tHD, DAT tHD, STA tSU, STO SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. Serial Interface Timing Details Table 3. Programmable Device Address Settings DEVICE ADDRESS B7 B6 B5 B4 B3 B2 B1 0 1 0 A3 A2 A1 A0 Device Address (AD0) The MAX5980 is programmable to 1 of 16 unique slave device addresses.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Acknowledge The acknowledge bit is a clocked 9th bit (Figure 8) that the recipient uses to handshake receipt of each byte of data. Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, so the SDA line is stable low during the high period of the clock pulse.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Slave Address The device has a 7-bit long slave address (Figure 9). The bit following the 7-bit slave address (bit eight) is the R/W bit, which is low for a write command and high for a read command. The upper five bits of the slave address cannot be changed and are always [01000]. Using the AD0 input, the lowest two bits can be programmed to assign the device one of four unique slave addresses (see Table 3).
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet MAX5980 ACKNOWLEDGE FROM THE MAX5980 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 CONTROL BYTE STORED ON STOP CONDITION D7 D6 D5 D4 D3 D2 D1 D0 ACKNOWLEDGE FROM THE MAX5980 S 0 SLAVE ADDRESS ACK CONTROL BYTE ACK DATA BYTE (1 BYTE) R/W ACK P ACK P WORD ADDRESS AUTOINCREMENT Figure 11.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Operation with Multiple Masters When the device operates on a 3-wire interface with multiple masters, a master reading the device should use repeated starts between the write that sets the device’s address pointer, and the read(s) that take the data from the location(s). It is possible for master 2 to take over the bus after master 1 has set up the device’s address pointer but before master 1 has read the data.
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MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Table 5.
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MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Register Map and Description The device contains a bank of volatile registers that store its settings and status. The device features an I2Ccompatible, 3-wire serial interface, allowing the registers to be fully software configurable and programmable. In addition, several registers are also pin-programmable to allow the device to operate in auto mode and still be partially configurable even without the assistance of software.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Power Event Register (R02h/R03h) The Power Event register (R02h/R03h, Table 8) records changes in the power status of the port. On powerup or after a reset condition, the Power Event register is set to a default value of 00h. Any change in PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change in PWR_EN_ (R10h[3:0]) sets PE_CHG_ to 1.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Detect Event Register (R04h/R05h) The Detect Event register (R04h/R05h, Table 9) records detection/classification events for the port. On power-up or after a reset condition, the Detect Event register is set to a default value of 00h. DET_ and CLS_ are set high whenever detection/classification is completed on the corresponding port. As with the other event registers, the Detect Event register has two addresses.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Supply Event Register (R0Ah/R0Bh) The device monitors die temperature, external FET status, and the analog and digital power supplies, and sets the appropriate bits in the Supply Event register (R0Ah/ R0Bh, Table 12). On power-up or after a reset condition, the Supply Event register is set to a default value of 02h (but may immediately change depending on the cause of the reset).
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Status Registers (R0Ch–R11h) Port Status Registers (R0Ch–R0Fh) The Port Status registers (R0Ch–R0Fh, Table 13) record the results of the port detection and classification at the end of each phase in three encoded bits. On powerup or after a reset condition, the Port Status register is set to a default value of 00h. Tables 14 and 15 are the detection and classification result decoding tables respectively.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Pin Status Register (R11h) The Pin Status register (R11h, Table 17) records the state of the A3, A2, A1, A0, and AUTO pins. The states of A3 and A2 (into ID[1:0]), A1 and A0 (into SLAVE[1:0]), and AUTO are latched into their corresponding bits after a power-up or reset condition clears. Therefore, the default state of the Pin Status register depends on those inputs (00XX–XX0X).
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Configuration Registers (R12h–R17h) Operating Mode Register (R12h) The Operating Mode register in the device (R12h, Table 19) contains 2 bits per port that set the port mode of operation. Table 20 details how to set the mode of operation for the device. On a power-up or after a reset condition, if AUTO = 1, the Operating Mode register is set to a default value of FFh. If AUTO = 0, the Operating Mode register is set to 00h.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet While in Auto and Semiautomatic mode, setting DET_EN_ (R14h[3:0]) and CLASS_EN_ (R14h[7:4]) to 1 enables load detection, and classification (upon successful detection) respectively. In manual mode, R14h works like a pushbutton register. Setting a bit high launches a single detection or classification cycle, and at the conclusion of the cycle the bit then clears. In SHDN mode, programming this register has no effect.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Miscellaneous Configuration 1 Register (R17h) The Miscellaneous Configuration 1 register (R17h, Table 24) is used for several functions that do not cleanly fit within one of the other configuration categories. On a power-up or after a reset condition, this register is set to a default value of A0h. Therefore, by default, INT_EN (R17h[7]) is set to 1 enabling INT functionality.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Power-Enable Pushbutton Register (R19h) The Power-Enable Pushbutton register (R19h, Table 26) is used to manually power a port on or off. On a power-up or after a reset condition, this register is set to a default value of 00h. Setting PWR_OFF_ (R19h[7:4]) to 1 turns off power to the corresponding port. PWR_OFF_ commands are ignored when the port is already off and during shutdown.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet General Registers (R1Bh–R1Fh) ID Register (R1Bh) The ID register (R1Bh, Table 28) keeps track of the device ID number and revision. The device’s ID code is stored in ID_CODE[4:0] (R1Bh[7:3]) and is 11010. Contact the factory for the value of the revision code stored in REV[2:0] (R1Bh[2:0]) that corresponds to the device lot number.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Maxim Reserved Registers (R20h–R2Fh) Maxim Reserved Registers (R20h–R28h, R2Ah–R2Fh) These registers are reserved. Writing to these registers is not recommended as they are internally connected. If the software needs to do a large batch write command using the address autoincrement function, write a code of 0x00h to these registers to safely autoincrement past them, and then continue the write commands as normal.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Current/Voltage Readout Registers (R30h–R3Fh) Port Current Registers (R30h, R31h, R34h, R35h, R38h, R39h, and R3Ch, R3Dh) The Port Current registers (Tables 32 and 33) provide port current readout when a port is powered on. On a power-up or after a reset condition, these registers are both set to a default value of 00h.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet reading the MSB, the register contents are frozen if addressing byte points to either of the Voltage Readout registers. During normal operation, the port output voltage can be calculated as: VOUT_ = NVP_ x 5.835mV/count where NVP_ is the decimal value of the 16-bit port voltage readout. The ADC saturates both at full scale and at zero, resulting in poor voltage readout accuracy near the top and bottom codes. Table 34.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Other Functions Registers (R00h, R01h) Reserved Registers (R40h, R45h, R4Ah, R4Fh, R54h, R59h, R5Ah, R5Bh, R5Ch, R5Dh, R5Eh, R5Fh) These registers are at this time reserved. Writing to these registers will have no effect (the address autoincrement will still update) and any attempt to read these registers will return all zeroes. Firmware Register (R41h) The Firmware register (R41h) is at this time set by default set to 00h.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Port GPMD Register (R46h, R4Bh, R50h, and R55h) The Port GPMD registers (Table 39) are used to enable the legacy high-capacitance PD detection and to enable 2-event classification for the corresponding port. On a power-up or after a reset condition, these registers are set to a default value of 94h. The status of the LEGACY input on power-up or reset is latched into the LEG_EN_ bit.
MAX5980 Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Port Current-Limit Register (R48h, R4Dh, R52h, and R57h) The Port Current-Limit registers (Table 41) are used to set the current-limit SENSE_ voltage threshold for the corresponding port. On a power-up or after a reset condition, these registers are set to a default value of 80h. Bit 7 is hardwired to 1, while bits 5 to 0 are hardwired to 0. ILIM_ (bit 6) is set to 0 for a Class 0–3 PD, and to 1 for a Class 4 or 5 PD.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet be done from the end of the high-side sense resistor pad, and the SVEE_ pairs should be routed from the end of the low-side sense resistor pads. To minimize the impact from additional series resistance, the two end points should be as close as possible, and sense trace length should be minimized (see Figure 14 for a layout diagram, and refer to the MAX5980 Evaluation Kit for a design example).
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet MAX5980 Typical Operating Circuit 0.1µF 100V -54V 50I CURRENT SHARING WITH OTHER MAX5980 33nF INTERNAL PULLUP TO VDD AGND A0 A1 A2 A3 VDD 0.1µF 100V 1.8kI -54V 200I 3.3V 200I GATE1 3kI HPCL063L SENSE1 FDMC3612 100V, 110mI EXTERNAL ISOLATED SERIAL INTERFACE 0.
Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet REVISION NUMBER REVISION DATE 0 12/10 Initial release 1 8/11 Globally changed operating temperature range to -40°C to +105°C throughout data sheet. Added conditions to Offset Error and Gain Error in the Electrical Characteristics Table. Replaced TOCs 1, 3, 4, 5, 8, and added TOC 5b.
