Datasheet

MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
20 ______________________________________________________________________________________
CS
DIO
SCLK
CS
DIO
SCLK
0 0 0 0 0 0 0 0
A3 A2
A1 A0
READ
COMMAND
READ
COMMAND
ADDRESS
DATA
R7 R6 R5 R4 R3 R2 R1 R0 R0R7
REGISTER DATA
REGISTER
DATA
0 0 0 0 0 0 0 0A3 A2 A1 A0
ADDRESS
DATA
R7 R6 R5 R4 R3 R2 R1
REGISTER DATA
A3
16 BITS OF DATA
8 BITS OF DATA
1 0 A5 A4
1 0 A5 A4
Figure 9. Read Command on a 3-Wire Serial Interface
C1 C0 A5 A4 A3 A2 A1 A0 D3 D2 D1 D0D7 D6 D5 D4
COMMAND ADDRESS
DATA
CS
DIO
SCLK
Figure 8. Data Input Diagram
DIO is selected as an output of the MAX7032 for the fol-
lowing CS cycle whenever a READ command is
received. The CPU must tri-state the DIO line on the
cycle of CS that follows a read command, so the
MAX7032 can drive the data output line. Figure 9
shows the diagram of the 3-wire interface. Note that the
user can choose to send either 16 cycles of SLCK or
just eight cycles as all the registers are 8-bits wide. The
user must drive DIO low at the end of the read
sequence.
The MASTER RESET command (0x3) (see Table 2)
sends a reset signal to all the internal registers of the
MAX7032 just like a power-off and power-on sequence
would do. The reset signal remains active for as long as
CS is high after the command is sent.