Datasheet

The AGC dwell time is dependent on the crystal fre-
quency and the bit settings of the AGC dwell timer. To
calculate the dwell time, use the following equation:
where K is an odd integer in decimal from 9 to 23; see
Table 11.
To calculate the value of K, use the following equation
and use the next odd integer higher than the calculated
result:
K ≥ 3.3 x log
10
(Dwell Time x f
XTAL
)
For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For NRZ data, set
the dwell to greater than the period of the longest string
of zeros or ones. For example, using Manchester Code
at 315MHz (f
XTAL
= 12.679MHz) with a data rate of
4kbps (bit period = 125µs), the dwell time needs to be
greater than 250µs:
K ≥ 3.3 x log
10
(250µs x 12.679MHz) ≈ 11.553
Choose the register value to be the next odd integer value
higher than 11.553, which is K = 13. The default value of
the AGC dwell timer on power-up or rest is zero (K = 9).
Calibration
The MAX7032 must be calibrated to ensure accurate
timing of the off timer in discontinuous receive mode or
when receiving FSK signals. The first step in calibration
is ensuring that the oscillator frequency register (regis-
ter: 0x05) has been programmed with the correct divi-
sor value (see the Oscillator Frequency Register
(Address 0x05) section). Next, enable the mixer to turn
the crystal driver on.
Calibrate the polling timer by setting PCAL = 1 in the
control register (register 0x01, bit 3). Upon completion,
the PCALD bit in the status register (register 0x1A,
bit 1) is 1 and the PCAL bit is reset to zero. If using the
MAX7032 in continuous receive mode, polling timer
calibration is not needed.
To calibrate the FSK receiver, set FCAL = 1. Upon
completion, the FCALD bit in the status register (regis-
ter 0x1A) is one, and the FCAL bit is reset to zero.
When in continuous receive mode and receiving FSK
data, recalibrate the FSK receiver after a significant
change in temperature or supply voltage. When in dis-
continuous receive mode, the polling timer and FSK
receiver (if enabled) are automatically calibrated every
wake-up cycle.
Off Timer (t
OFF
)
The off timer, t
OFF
(see Figure 10), is a 16-bit timer that
is configured using register 0x06 for the upper byte,
register 0x07 for the lower byte, and bits OFPS1 and
OFPS0 in the configuration 0 register (register 0x02, bit
3 and bit 2, respectively). Table 12 summarizes the
configuration of the t
OFF
timer. The OFPS1 and OFPS0
bits set the size of the shortest time possible (t
OFF
time
base). The data written to the t
OFF
registers (register
0x06 and register 0x07) are multiplied by the time base
to give the total t
OFF
time. See the example below. On
power-up, the off-timer registers are reset to zero and
must be written before using DRX mode.
Dwell Time
f
K
XTAL
=
2
MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
______________________________________________________________________________________ 25
DT2 DT1 DT0 DESCRIPTION
0 0 0 K = 9
001 K = 11
010 K = 13
011 K = 15
100 K = 17
101 K = 19
110 K = 21
111 K = 23
Table 11. AGC Dwell Timer Configuration
(Address 0x03)
OFPS1 OFPS0
t
OFF
TIME BASE
MIN t
OFF
REG 0x06 = 0x00
REG 0x07 = 0x01
MAX t
OFF
REG 0x06 = 0xFF
REG 0x07 = 0xFF
0 0 120µs 120µs 7.86s
0 1 480µs 480µs 31.46s
1 0 1920µs 1.92ms 2min 6s
1 1 7680µs 7.68ms 8min 23s
Table 12. Off-Timer (t
OFF
) Configuration