Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX7033EUI+

General Description

The MAX7033 fully integrated low-power CMOS super-

heterodyne receiver is ideal for receiving amplitude shift-

keyed (ASK) data in the 300MHz to 450MHz frequency

range. The receiver has an RF input signal range of

-114dBm to 0dBm. With few external components and a

low-current power-down mode, it is ideal for cost-sensitive

and power-sensitive applications typical in consumer

markets. The MAX7033 consists of a low-noise ampli-

fier (LNA), a fully differential image-rejection mixer, an

on-chip phase-locked loop (PLL) with integrated voltage-

controlled oscillator (VCO), a 10.7MHz IF limiting amplifier

stage with received-signal-strength indicator (RSSI), and

analog baseband data-recovery circuitry. The MAX7033

also has a discrete one-step automatic gain control

(AGC) that reduces the LNA gain by 35dB when the RF

input signal exceeds -62dBm. The AGC circuitry offers an

externally controlled hold feature.

The MAX7033 is available in 28-pin TSSOP and 32-pin

TQFN packages and is specified over the extended

(-40°C to +105°C) temperature range.

Applications

Features

● Optimized for 315MHz or 433MHz Band

● Operates from Single +3.3V or +5.0V Supplies

● High Dynamic Range with On-Chip AGC

● AGC Hold Circuit

● 1ms AGC Release Time

● Selectable Image-Rejection Center Frequency

● Selectable x64 or x32 f

XTAL

Ratio

● Low 5.2mA Operating Supply Current

● < 3.5μA Low-Current Power-Down Mode for Efficient

Power Cycling

● 250μs Startup Time

● Built-In 44dB RF Image Rejection

● Better than -114dBm Receive Sensitivity

● -40°C to +105°C Operation

Typical Application Circuit appears at end of data sheet.

19-3273; Rev 4; 4/14

● Security Systems

● Garage Door Openers

● Home Automation

● Remote Controls

● Local Telemetry

● Wireless Sensors

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

MAX7033EUI+ -40°C to +105°C 28 TSSOP

MAX7033ETJ+ -40°C to +105°C 32 TQFN-EP*

XTAL2

SHDN

PDOUT

DATAOUT

DD5

DSP

DFFB

OPP

DSN

DFO

IFIN2

IFIN1

XTALSEL

DVDD

DGND

MIXOUT

IRSEL

AGND

MIXIN2

MIXIN1

AVDD

LNAOUT

AGND

LNASRC

LNAIN

AVDD

XTAL1

TSSOP

TQFN

TOP VIEW

MAX7033

LNASRC

LNAIN

AVDD

XTAL1

XTAL2

SHDN

PDOUT

25 N.C.

MIXOUT

DGND

DVDD

N.C.

XTALSEL

IFIN1

16IFIN2

DFO

DSN

OPP

DFFB

N.C.

DSP

DD5

IRSEL

AGND

MIXIN2

MIXIN1

AVDD

LNAOUT

AGND

MAX7033

1N.C.

24 DATAOUT

MAX7033 315MHz/433MHz ASK Superheterodyne

Receiver with AGC Lock

Ordering Information

Pin Congurations

Summary of content (16 pages)

PAGE 1
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock General Description The MAX7033 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitude shiftkeyed (ASK) data in the 300MHz to 450MHz frequency range. The receiver has an RF input signal range of -114dBm to 0dBm. With few external components and a low-current power-down mode, it is ideal for cost-sensitive and power-sensitive applications typical in consumer markets.
PAGE 2
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Absolute Maximum Ratings VDD5 to AGND......................................................-0.3V to +6.0V AVDD to AGND.....................................................-0.3V to +4.0V DVDD to DGND.....................................................-0.3V to +4.0V AGND to DGND....................................................-0.1V to +0.1V IRSEL, DATAOUT, XTALSEL, AC, SHDN to AGND............................ -0.3V to (VDD5 + 0.
PAGE 3
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Electrical Characteristics (continued) (Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Input-Voltage High VIH Input Logic Current High IIH CONDITIONS TYP MAX fRF = 375MHz, VIRSEL = VDD5/2 µA VDD5 - 0.4 1.1 VDD5 - 1.
PAGE 4
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Electrical Characteristics (continued) (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.
PAGE 5
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Electrical Characteristics (continued) (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.
PAGE 6
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Typical Operating Characteristics (continued) (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) 35 SYSTEM GAIN (dB) 85 -140 -120 -100 -80 -60 -40 RF INPUT POWER (dBm) LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY IMAGE REJECTION vs. RF FREQUENCY 45 35 49dB IMAGE REJECTION 25 15 LOWER SIDEBAND FROM RFIN TO MIXOUT fRF = 315MHz 5 5 10 15 20 IF FREQUENCY (MHz) www.
PAGE 7
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Typical Operating Characteristics (continued) (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) 40 30 -10 -15 -20 10 1 200MHz -20 315MHz -36dB FREQUENCY (MHz) REGULATOR VOLTAGE vs. REGULATOR CURRENT PHASE NOISE vs. OFFSET FREQUENCY 0 MAX7033 toc13 2.9 -40°C 2.7 +25°C 2.5 2.3 +85°C 2.1 +105°C 1.9 10 20 30 40 50 REGULATOR CURRENT (mA) www.maximintegrated.
PAGE 8
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Pin Description PIN TSSOP TQFN 1 29 NAME FUNCTION XTAL1 Crystal Input 1 (see the Phase-Locked Loop section) 2, 7 4, 30 AVDD Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V low-dropout regulator, and should be bypassed to AGND with a 0.1µF capacitor as close as possible to the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed to AGND with a 0.
PAGE 9
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Pin Description (continued) PIN NAME TSSOP TQFN 28 28 XTAL2 — 1, 13, 21, 25 N.C. — — EP FUNCTION Crystal Input 2. Can also be driven with an external reference oscillator (see the Crystal Oscillator section). No Connection Exposed Pad (TQFN Only). Connect EP to GND. Functional Diagram LNASRC 4 LNAIN AVDD VDD5 AVDD DVDD DGND AGND 3 AC 15 IRSEL 11 LNAOUT MIXIN1 MIXIN2 6 8 9 AUTOMATIC GAIN CONTROL LNA Q 3.
PAGE 10
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a typical PCB trace antenna. A nominal value for this inductor with a 50Ω input impedance is 15nH, but is affected by PCB trace.
PAGE 11
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock is required due to the on-chip image-rejection architecture. The IF output is driven by a source follower biased to create a driving-point impedance of 330Ω; this provides a good match to the off-chip 330Ω ceramic IF filter. The IRSEL pin is a logic input that selects one of the three possible image-rejection frequencies. When VIRSEL = 0V, the image rejection is tuned to 315MHz.
PAGE 12
MAX7033 Intermediate Frequency and RSSI The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The six internal AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass-filter-type response centered near the 10.7MHz IF frequency 1 with a 3dB bandwidth of approximately 10MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.
PAGE 13
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock For example, to choose a Butterworth filter response with a corner frequency of 5kHz: C5 C6 = MAX7033 1.000 ≈ 450pF 1.414 100k Ω)(3.14)(5kHz) ( )( DATA SLICER 1.414 ≈ 225pF (4)(100kΩ)(3.14)(5kHz) 20 DSN 25 DATAOUT Choosing standard capacitor values changes C5 to 470pF and C6 to 220pF, as shown in the Typical Application Circuit. The data slicer takes the analog output of the data filter and converts it to a digital signal.
PAGE 14
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Layout Considerations A properly designed PCB is an essential part of any RF/ microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance.
PAGE 15
MAX7033 Chip Information PROCESS: CMOS www.maximintegrated.com 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO.
PAGE 16
MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Revision History REVISION NUMBER REVISION DATE 0 7/04 Initial release 1/11 Updated Ordering Information, Pin Configurations, Absolute Maximum Ratings, DC Electrical Characteristics, AC Electrical Characteristics, Typical Operating Characteristics, Pin Description, Functional Diagram, Voltage Regulator and Layout Considerations sections, Typical Application Circuit, Chip Information, and Package Information 1–9, 13, 14, 15 2 9/11 Up