Datasheet

DESIGNATION QTY DESCRIPTION
JP1 1 6-pin (2 x 3) straight male header
LED1–LED4 4 Red LEDs (1206)
R1, R2, R3 3
150I Q5% resistors (0603)
R4, R5 2
4.7kI Q5% resistors (0603)
R6 1
10kI Q5% resistor (0603)
U1 1
16-port, level-translating GPIO
and LED driver (24 TQFN-EP*)
Maxim MAX7304ETG+
— 1 Shorting jumper
— 1 PCB: EPCB7304PM1
SUPPLIER PHONE WEBSITE
Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com
TDK Corp. 847-803-6100 www.component.tdk.com
DESIGNATION QTY DESCRIPTION
C1, C3 2
1FF Q10%, 10V X7R ceramic
capacitors (0603)
TDK C1608X7R1A105K
C2 1
0.1FF Q10%, 16V X7R ceramic
capacitor (0603)
Murata GRM188R71C104KA01D
J1 1 6-pin right-angle male header
J2 1
18-pin (2 x 9) straight male
header
J3 1 8-pin (2 x 4) straight male header
PIN SIGNAL DESCRIPTION
1 N.C. Not connected
2 INT Interrupt
3 SCL I
2
C serial clock
4 SDA I
2
C serial data
5 GND Ground
6 VCC Power supply
MAX7304PMB1 Peripheral Module
2Maxim Integrated
Component Suppliers
Note: Indicate that you are using the MAX7304PMB1 when contacting these component suppliers.
Component List
Detailed Description
UART Interface
The MAX7304PMB1 peripheral module can interface to
the host by plugging directly into a Pmod-compatible port
(configured for I
2
C) through connector J1. See Table 1.
The J2 connector provides the connection to the push-
pull and open-drain outputs. See Table 2.
The J3 connector allows the module to be connected
through a daisy-chain from another I
2
C module and/or
provide I
2
C and power connections to other I
2
C modules
on the same bus. See Table 3.
Jumper JP1 provides the ability to set the I
2
C address.
This is accomplished by connecting the AD0 pin to GND,
VCC, SDA, or SCL. See Table 4.
Software and FPGA Code
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module function-
ality and uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions
within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download at
www.maximintegrated.com. Quick start instructions are
also available as a separate document.
Table 1. Connector J1 (I
2
C Communication)
*EP = Exposed pad.