Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsPMICsPMIC - power management - special purpose QSOP 28

________________General Description

The MAX769 is a complete buck/boost power supply

and monitoring system for two-way pagers or other low-

power digital communications devices. Few external

components are required. Included on-chip are:

• An 80mA output, synchronous-rectified, buck/boost

DC-DC converter with a digitally controlled +1.8V to

+4.9V output. The DC-DC converter is unique, since

it provides a regulated output for battery inputs that

are both less than and greater than the output volt-

age, without using transformers.

• Three low-noise linear-regulator outputs

• Three DAC-controlled comparators for software-

driven, 3-channel A/D conversion

• SPI™-compatible serial interface

• Reset and low-battery (LBO) warning outputs

• Charger for NiCd/NiMH, lithium battery, or storage

capacitor for RF PA power or system backup

• Two 1.8Ω (typical), serial-controlled, open-drain

MOSFET switches for beeper or vibrator drive

An evaluation kit for the MAX769 (MAX769EVKIT) is

available to aid in design and prototyping.

____________________________Features

♦ Regulated Step-Up/Step-Down Operation

♦ 80mA Output from 3 Cells

♦ 85% Efficiency

♦ 13µA Idle Mode™ (coast) Current

♦ Selectable Low-Noise PWM or Low-Current PFM

Operation

♦ PWM Operating Frequency Synchronized to

Seven Times an External Clock Source

♦ Operates at 270kHz with No External Clock

♦ Automatic Backup-Battery Switchover

________________________Applications

Two-Way Pagers

GPS Receivers

2 or 3-Cell Powered, Hand-Held Equipment

MAX769

2 or 3-Cell, Step-Up/Down,

Two-Way Pager System IC

________________________________________________________________

Maxim Integrated Products

MAX769

INPUT

2 OR 3 AA ALKALINE BATTERIES

1.5V TO 5.5V

BATT

LX2

OUT

PGND

REG2IN

OFS

REG2

OUTPUT 2

2.85V ANALOG

LOW-BATTERY

IN/OUT

REJECT

IN/OUT

SERIAL

I/O

1.8Ω

DRIVERS

A/D

INPUT

OPTIONAL

OUTPUT 1

3V LOGIC

OUTPUT 3

1V RECEIVER

TO RF PA

NiCd

BATTERY OR

STACK

REG1

REG3

NICD

AGNDREFFILT

LBI

LBO

RSIN

RSO

SCL

SD1

SD03

DR1

DR2

DR2IN

DRGND

CH0

SYNC

LX1

STORAGE

CAPACITOR

___________________________________________________Typical Operating Circuit

19-4771; Rev 1; 10/98

PART

MAX769EEI -40°C to +85°C

TEMP. RANGE PIN-PACKAGE

28 QSOP

Ordering Information

Idle Mode is a trademark of Maxim Integrated Products. SPI is a trademark of Motorola, Inc.

Pin Configuration appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

EVALUATION KIT MANUAL

FOLLOWS DATA SHEET

Summary of content (16 pages)

PAGE 1
9-4771; Rev 1; 10/98 ANUAL N KIT M EET IO T A U EVAL TA SH WS DA FOLLO 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC ____________________________Features ♦ Regulated Step-Up/Step-Down Operation ♦ 80mA Output from 3 Cells ♦ 85% Efficiency ♦ 13µA Idle Mode™ (coast) Current ♦ Selectable Low-Noise PWM or Low-Current PFM Operation ♦ PWM Operating Frequency Synchronized to Seven Times an External Clock Source ♦ Operates at 270kHz with No External Clock ♦ Automatic Backup-Battery Switchover Ordering Infor
PAGE 2
MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC ABSOLUTE MAXIMUM RATINGS BATT, OUT, NICD, LBO, RSO to AGND...................-0.3V to +6V REG1, REG2, OFS, REF, R2IN to AGND .....-0.3V to (OUT + 0.3V) SCL, SDO, SDI, CS, SYNC, FILT, DR2IN, CH0, LBI, RSIN to AGND......................-0.3V to (REG1 + 0.3V) REG3 .......................................................-0.3V to (REG2 + 0.3V) DR1, DR2 to DRGND ...............................-0.3V to (BATT + 0.3V) PGND, DRGND to AGND .....................
PAGE 3
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769 ELECTRICAL CHARACTERISTICS (continued) (OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC ELECTRICAL CHARACTERISTICS (continued) (OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 1.5 3.1 Ω LINEAR REGULATORS REG1 PMOS On-Resistance OUT = 3.0V, IREG1 = 65mA REG1 Supply Rejection (Note 16) f = 268.8kHz, CREG1 = 10µF ceramic REG1 Clamp Voltage IOUT = 1mA, OUT = 4.
PAGE 5
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC (OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CONDITIONS CH2 Input Hysteresis (Note 16) CH0 Input Current CH0 = 0.2V to 1.27V CH Comparator Response Time (Note 16) 10mV overdrive Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: MIN TYP MAX UNITS 4 8 16 mV 100 nA 1.
PAGE 6
Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) START-UP BATTERY VOLTAGE vs. LOAD CURRENT MAXIMUM LOAD CURRENT vs. BATTERY VOLTAGE VOUT = 3.0V 140 120 RUN MODE 100 80 COAST MODE 60 40 6 MAX769-06 160 MAX769-05 VOUT = 3.0V COAST MODE MAXIMUM LOAD CURRENT (mA) MAX769-04 100 VOUT = 3.0V COAST MODE START-UP BATTERY VOLTAGE (V) NO-LOAD BATTERY CURRENT vs.
PAGE 7
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC PIN NAME FUNCTION LX1 Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET that switches to OUT. 2 SDI Serial Data Input for SPI Interface 3 SDO Serial Data Output for SPI Interface 4 PGND 1 Power Ground. Source of LX1 and LX2 NFETs. 5 SCL Serial Clock for SPI Interface 6 LBO Open-Drain Output for LBI Comparator 7 RSO Reset Output. Open drain goes low when RSIN drops below 0.6V.
PAGE 8
MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC 2- OR 3-CELL BATTERY IN SCL SDI SDO CS 5 2 3 27 22µF 26 BATT P 28 N LBO 6 11 – 0.6V CPLB + CH0 9 + CP0 – FROM NICD S1 X7 PLL TO S1 AND S2 SERIAL I/O 12 5 FILT OUT 25 CH2 3.
PAGE 9
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC The MAX769 contains several functional blocks that simplify the integration of power-supply and monitoring functions within a 2 or 3-cell powered system. They are described in the following subsections. Voltage Regulators Regulator outputs include the following: • OUT: Main switch-mode buck/boost output • REG1: 1.5Ω switch and output voltage clamp. Switches REG1 to OUT and clamps REG1 at 3.3V when OUT is set to 3.4V or more.
PAGE 10
MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC 2 OR 3-CELL AA ALKALINE BATTERY C5 22µF R1 1M 11 REG1 L1 68µH 26 1 BATT LX1 LX2 OUT LBI R2 250k R5 270k PGND 6 9 A/D IN SERIAL I/O 27 5 2 3 1.8Ω DRIVERS 17 19 18 16 38.4kHz C10 22nF CH0 13 12 C9 1nF 10k LBO 8 REG1 MAX769 CS SCL SDI SDO R2IN DR1 DR2 DR2IN DRGND REG2 OFS 28 25 C1 47µF 4 REG3 RSIN RSO NICD REF AGND 15 C6 0.1µF 3.0V LOGIC 24 C2 10µF 22 14 COFS 0.1µF ROFS, 15k 21 2.
PAGE 11
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC The A/D circuitry can be invoked in both Run and Coast Modes. Open-Drain Drivers Two open-drain drivers (DR1 and DR2) are activated via the serial interface. DR1 and DR2 are grounded 1.8Ω (typical) NFETs that can sink up to 120mA. The maximum sink current is limited by on-resistance and package dissipation to about 240mA total sink current for both switches.
PAGE 12
MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC Table 1. Serial-Bit Assignments R2 (MSB) R1 R0 D4 D3 D2 D1 D0 0 0 0 DR2_ON DR1_ON REG3_ON REG2_ON RUN/ COAST 0 0 1 X LBO_Sets_ BACKUP BACKUP 15mA_CHG 1mA_CHG 0 1 0 OV4 OV3 OV2 OV1 OV0 0 1 1 X X X X X 1 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 Table 2.
PAGE 13
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC SERIAL-DATA BIT VOUT (V) All DC-DC converter and charging circuitry is disabled when the backup regulator is turned on, but all other functions remain active. Activate BACKUP manually or by serial command, or set it to trigger automatically via LBO. OV4 OV3 OV2 OV1 OV0 0 0 0 0 0 1.8 0 0 0 0 1 1.9 0 0 0 1 0 2.0 0 0 0 1 1 2.1 0 0 1 0 0 2.2 0 0 1 0 1 2.3 0 0 1 1 0 2.4 0 0 1 1 1 2.5 0 1 0 0 0 2.
PAGE 14
MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC Serial data is clocked in and out MSB first. Input data is latched on the CLK rising edge, and output data is shifted out on the CLK falling edge. When CS goes low, DO immediately contains the MSB output bit (D7). D6 is not clocked out until the falling clock edge that follows the first rising clock edge after a Chip Select. See the timing diagrams in Figures 4 and 5.
PAGE 15
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC from external logic (or a µP) powered from REG1, or by open-drain logic devices that are pulled up to REG1. Component Selection The MAX769 requires minimal design calculation and is optimized for the component values shown in Figure 2. However, some flexibility in component selection is still allowed, as described in the following text. A list of suitable components is provided in Table 6.
PAGE 16
2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769 Pin Configuration TOP VIEW LX1 1 28 LX2 SDI 2 27 CS SDO 3 26 BATT PGND 4 25 OUT SCL 5 LBO 6 24 REG1 MAX769 23 NICD RSO 7 22 R2IN REF 8 21 REG2 CH0 9 20 REG3 RSIN 10 19 DR2 LBI 11 18 DR2IN FILT 12 17 DR1 SYNC 13 16 DRGND 15 AGND OFS 14 QSOP QSOP.