Datasheet

MAX8632
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
10 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
11 PGND2 Power Ground for VTT and VTTR. Connect PGND2 externally to the underside of the exposed pad.
12 VTT Termination Power-Supply Output. Connect VTT to VTTS to regulate to V
REFIN
/ 2.
13 VTTI
Power-Supply Input Voltage for VTT and VTTR. Normally connected to the output of the buck regulator
for DDR application.
14 REFIN External Reference Input. This is used to regulate the VTT and VTTR outputs to V
REFIN
/ 2.
15 FB
Feedback Input for Buck Output. Connect to AV
DD
for a +1.8V fixed output or to GND for a +2.5V fixed
output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output
voltage. FB regulates to +0.7V.
16 OUT
Output-Voltage Sense Connection. Connect to the positive terminal of the buck output filter capacitor.
OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in
Figure 8). OUT also serves as the buck output’s feedback input in fixed-output modes. When discharge
mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10Ω resistor
connected between OUT and GND. OUT also acts as the input to the VTT and VTTR UVLO detector.
17 V
IN
Input-Voltage Sense Connection. Connect to input power source. V
IN
is used only to set the PWM’s on-
time one-shot timer. IN voltage range is from 2V to 28V.
18 DH High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.
19 LX
External Inductor Connection. Connect LX to the input side of the inductor. LX is used for both current
limit and the return supply of the DH driver.
20 BST
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to Figure 8.
See the Boost-Supply Diode and Capacitor Selection (Buck) section.
21 DL Synchronous-Rectifier Gate-Driver Output. Swings from PGND to V
DD
.
22 V
DD
Supply Input for the DL Gate Drive. Connect to the +4.5V to +5.5V system supply voltage. Bypass to
PGND1 with a 1µF (min) ceramic capacitor.
23 PGND1 Power Ground for Buck Controller. Connect PGND1 externally to the low-side FET’s source.
24 GND
Analog Ground for Both Buck and LDO. Connect GND externally to the underside of the exposed pad.
25 SKIP
Pulse-Skipping Control Input. Connect to AV
DD
for low-noise, forced-PWM mode. Connect to GND to
enable pulse-skipping operation.
26 AV
DD
Analog Supply Input for Both Buck and LDO. Connect to the +4.5V to +5.5V system supply voltage
with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor.
27 SHDN
Shutdown Control Input. Use to control buck output. A rising edge on SHDN clears the overvoltage-
and undervoltage-protection fault latches (see Tables 2 and 3). Connect to AV
DD
for normal operation.
28 TP0 This is a test pin. Must connect to GND externally.
—EP
Exposed pad. The exposed pad must be star-connected to GND and PGND2. See Special Layout
Considerations for LDO Section for more details.