Datasheet

MAX8819A/MAX8819B/MAX8819C
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
______________________________________________________________________________________ 25
input of the system μP, the processor can begin its
boot-up sequence up at this time.
4) During the μP’s boot-up sequence, it asserts EN123
to keep the step-down converters enabled, even if
DC is removed.
5) After the μP has booted, it asserts EN4 to turn on the
display’s backlight.
6) CEN is asserted by the μP to start a charge cycle.
7) The external supply is removed from DC and V
SYS
falls. The converters remain enabled because the μP
has asserted EN123 and EN4, but the battery charg-
ing current drops to zero even though CEN is still
asserted. CHG goes high impedance.
8) System is turned off by deasserting EN123, EN4, and
CEN; RST1 goes low to reset the μP.
Figure 7 notes:
1) The MAX8819C is off with no external power applied
to DC. The system voltage (V
SYS
) is equal to the bat-
tery voltage (V
BAT
).
2) An external supply is applied to DC that causes the
step-down regulator to power up after the DC-to-
SYS soft-start time (t
SS-D-S
). When the DC input is
valid and DC is not suspended, V
SYS
rises.
3) EN123 is pulled high to start the OUT3, OUT2, and
OUT1 power-up sequence. When OUT1 reaches the
reset trip threshold (V
THRST
), the reset deassert
delay timer starts. When the reset deassert delay
timer expires (t
DRST1
200ms typ.), RST1 goes high-
impedance. If RST1 is connected to the RESET input
of the system μP, the processor can begin its boot-
up sequence at this time.
V
EN123
V
OUT3
V
OUT2
V
OUT1
V
DC
t
SS-D-S
V
SYS
V
SYS
- V
D
V
BAT
t
SS3
NOTES
12
t
SS2
t
SS1
V
RST1
34
V
EN4
5
t
SS4
V
OUT4
V
BAT
7
t
SS_CHG
6
V
SYS
- V
D
V
CEN
V
CHG
V
BAT
< V
SYS
< V
DC
t
DRST1
HIGH IMPEDANCE
Figure 7. MAX8819C Enable/Disable Waveforms Example