Datasheet

MAX8819A/MAX8819B/MAX8819C
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
constant is R x C = 100μs, and the output voltage
decays to within 1% of final value in about 500μs.
PCB Layout and Routing
Good printed circuit board (PCB) layout is necessary to
achieve optimal performance. Refer to the MAX8819A
Evaluation Kit for Maxim’s recommended layout.
Use the following guidelines for the best results:
• The LX_ rapidly switches between PV_ and PG_.
Minimize stray capacitance on LX_ to maintain high
efficiency.
• Keep the FB_ node away from noise sources such
as the inductor.
• The exposed pad (EP) is the main path for heat to
exit the IC. Connect EP to the ground plane with
thermal vias to allow heat to dissipate from the
device.
• Use short and wide traces for high-current and dis-
continuous current paths.
• The step-down converter power inputs are critical
discontinuous current paths that require careful
bypassing. Place the step-down converter input
bypass capacitor as close as possible to the PV_
and PG_ pins.
• Minimize the area of the loops formed by the step-
down converters’ dynamic switching currents.
Package Marking
The top of the MAX8819_ package is laser etched as
shown in Figure 11:
“8819_ETI” is the product identification code. The full
part number is MAX8819_ETI; however, in this case, the
“MAX” prefix is omitted due to space limitations. The “_”
corresponds to the “A” or “B” version.
“yww” is a date code. “y” is the last number in the
Gregorian calendar year. “ww” is the week number in
the Gregorian calendar. For example:
• “801” is the first week of 2008; the week of
January 1st, 2008.
• “052” is the fifty-second week of 2010; the week of
December 27th, 2010.
• “aaaa” is an assembly code and lot code.
• “+” denotes lead-free packaging and marks the
pin 1 location.
8819_ETI
TIyww
+ aaaa
Figure 11. Package Marking Example
MAX8819A
MAX8819B
MAX8819C
TOP VIEW
26
27
25
24
10
9
11
FB4
PG4
LX4
GND
EN4
12
COMP4
PG3 PV13 LX1 DLIM1 PG1 CHG
12
PV2
4567
2021 19 17 16 15
LX2
PG2
CEN
DC
SYS
BAT
OVP4
LX3
3
18
28
8
DLIM2
RST1
EN123
23
13
FB1
FB3
22
14
CISET
FB2
+
EXPOSED PAD (EP)
Pin Configuration
Chip Information
PROCESS: S45T
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP T2844+1
21-0139
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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