Datasheet

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General Description

The MAX9121/MAX9122 quad low-voltage differential sig-

naling (LVDS) differential line receivers are ideal for appli-

cations requiring high data rates, low power, and low

noise. The MAX9121/MAX9122 are guaranteed to receive

data at speeds up to 500Mbps (250MHz) over controlled-

impedance media of approximately 100Ω. The transmis-

sion media may be printed circuit (PC) board traces or

cables.

The MAX9121/MAX9122 accept four LVDS differential

inputs and translate them to LVCMOS outputs. The

MAX9122 features integrated parallel termination resis-

tors (nominally 107Ω), which eliminate the requirement

for four discrete termination resistors and reduce stub

lengths. The MAX9121 inputs are high impedance and

require an external termination resistor when used in a

point-to-point connection.

The devices support a wide common-mode input range of

0.05V to 2.35V, allowing for ground potential differences

and common-mode noise between the driver and the

receiver. A fail-safe feature sets the output high when the

inputs are open, or when the inputs are undriven and

shorted or parallel terminated. The EN and EN inputs con-

trol the high-impedance output. The enables are common

to all four receivers. Inputs conform to the ANSI TIA/EIA-

644 LVDS standard. Flow-through pinout simplifies PC

board layout and reduces crosstalk by separating the

LVDS inputs and LVCMOS outputs. The MAX9121/

MAX9122 operate from a single +3.3V supply, and are

specified for operation from -40°C to +85°C. These

devices are available in 16-pin TSSOP and SO packages.

Refer to the MAX9123 data sheet for a quad LVDS line dri-

ver with flow-through pinout.

Applications

Digital Copiers

Laser Printers

Cellular Phone Base Stations

Add/Drop Muxes

Digital Cross-Connects

DSLAMs

Network Switches/Routers

Backplane Interconnect

Clock Distribution

____________________________Features

♦ Integrated Termination Eliminates Four External

Resistors (MAX9122)

♦ Flow-Through Pinout

Simplifies PC Board Layout

Reduces Crosstalk

♦ Pin Compatible with DS90LV048A

♦ Guaranteed 500Mbps Data Rate

♦ 300ps Pulse Skew (max)

♦ Conform to ANSI TIA/EIA-644 LVDS Standard

♦ Single +3.3V Supply

♦ Fail-Safe Circuit

MAX9121/MAX9122

Quad LVDS Line Receivers with

Integrated Termination and Flow-Through Pinout

________________________________________________________________ Maxim Integrated Products 1

Typical Application Circuit

19-1909; Rev 0; 6/01

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX9121EUE -40°C to +85°C 16 TSSOP

MAX9121ESE -40°C to +85°C 16 SO

MAX9122EUE -40°C to +85°C 16 TSSOP

MAX9122ESE -40°C to +85°C 16 SO

Pin Configuration appears at end of data sheet.

MAX9123

MAX9122

107Ω

100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES

LVDS SIGNALS

LVTTL/LVCMOS

DATA OUTPUT

LVTTL/LVCMOS

DATA INPUT

Summary of content (12 pages)

PAGE 1
9-1909; Rev 0; 6/01 KIT ATION EVALU LE B A IL A AV Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout ____________________________Features ♦ Integrated Termination Eliminates Four External Resistors (MAX9122) ♦ Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk ♦ Pin Compatible with DS90LV048A ♦ Guaranteed 500Mbps Data Rate ♦ 300ps Pulse Skew (max) ♦ Conform to ANSI TIA/EIA-644 LVDS Standard ♦ Single +3.
PAGE 2
MAX9121/MAX9122 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V EN, EN to GND ...........................................-0.3V to (VCC + 0.3V) OUT_ to GND .............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 9.
PAGE 3
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout (V CC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V LOGIC INPUTS (EN, EN) Input High Voltage VIH 2.0 VCC Input Low Voltage VIL 0 0.
PAGE 4
AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25°C, unless otherwise noted.) (Notes 3, 4) Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative.
PAGE 5
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE 96 95 94 93 2.00 tPHLD 1.90 1.80 1.70 92 3.3 2.10 tPHLD 1.90 tPLHD 1.70 1.50 1.60 3.6 3.0 3.3 -40 3.6 -15 10 35 60 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C) DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE tPHLD 2.00 1.75 tPLHD 1.50 2.0 1.
PAGE 6
MAX9121/MAX9122 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout Pin Description PIN NAME FUNCTION 1, 4, 5, 8 IN_- Inverting Differential Receiver Inputs 2, 3, 6, 7 IN_+ Noninverting Differential Receiver Inputs 9, 16 EN, EN 10, 11, 14, 15 OUT_ LVCMOS/LVTTL Receiver Outputs 12 GND Ground 13 VCC Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active.
PAGE 7
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122 VCC VCC RIN2 RIN2 VCC - 0.3V VCC - 0.3V IN_+ IN_+ RIN1 RIN1 OUT_ OUT_ RDIFF RIN1 RIN1 IN_- IN_MAX9121 MAX9122 Figure 1. Input with Fail-Safe Network received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the LVDS driver outputs are high impedance. A short condition can occur because of a cable failure.
PAGE 8
MAX9121/MAX9122 Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout IN_+ PULSE GENERATOR** OUT_ CL IN_50Ω* 50Ω* RECEIVER ENABLED 1/4 MAX9121/MAX9122 *50Ω REQUIRED FOR PULSE GENERATOR. **WHEN TESTING THE MAX9122, ADJUST THE PULSE GENERATOR OUTPUT TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR. Figure 2.
PAGE 9
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout 50Ω DEVICE UNDER TEST IN_- EN S1 RL IN_+ GENERATOR MAX9121/MAX9122 VCC OUT_ CL EN 1/4 MAX9121/MAX9122 CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS. Figure 4. High-Impedance Delay Test Circuit 3V EN WHEN EN = GND OR OPEN 1.5V 1.5V 0 3V 1.5V 1.5V 0 EN WHEN EN = VCC tPZL VCC tPLZ OUTPUT WHEN VID = -100mV 50% 0.
PAGE 10
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122 Functional Diagram VCC VCC IN1+ IN1+ OUT1 IN1- 107Ω OUT1 107Ω OUT2 107Ω OUT3 107Ω OUT4 IN1- IN2+ IN2+ OUT2 IN2- IN2- IN3+ IN3+ OUT3 IN3- IN3- IN4+ IN4+ OUT4 IN4- IN4- EN EN EN EN MAX9121 MAX9122 GND GND Pin Configuration TOP VIEW IN1- 1 16 EN IN1+ 2 15 OUT1 IN2+ 3 14 OUT2 IN2- 4 IN3- 5 MAX9121 MAX9122 13 VCC 12 GND IN3+ 6 11 OUT3 IN4+ 7 10 OUT4 IN4- 8 9 EN TSSOP/SO
PAGE 11
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout TSSOP,NO PADS.
PAGE 12
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout SOICN.EPS MAX9121/MAX9122 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.