Datasheet

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General Description

The MAX9123 quad low-voltage differential signaling

(LVDS) differential line driver is ideal for applications

requiring high data rates, low power, and low noise. The

MAX9123 is guaranteed to transmit data at speeds up to

800Mbps (400MHz) over controlled impedance media of

approximately 100Ω. The transmission media may be

printed circuit (PC) board traces, backplanes, or cables.

The MAX9123 accepts four LVTTL/LVCMOS input levels

and translates them to LVDS output signals. Moreover,

the MAX9123 is capable of setting all four outputs to a

high-impedance state through two enable inputs, EN and

EN, thus dropping the device to an ultra-low-power state

of 16mW (typ) during high impedance. The enables are

common to all four transmitters. Outputs conform to the

ANSI TIA/EIA-644 LVDS standard. Flow-through pinout

simplifies PC board layout and reduces crosstalk by sep-

arating the LVTTL/LVCMOS inputs and LVDS outputs.

The MAX9123 operates from a single +3.3V supply and is

specified for operation from -40°C to +85°C. It is available

in 16-pin TSSOP and SO packages. Refer to the MAX9121/

MAX9122* data sheet for quad LVDS line receivers with

integrated termination and flow-through pinout.

Applications

Features

♦ Flow-Through Pinout

Simplifies PC Board Layout

Reduces Crosstalk

♦ Pin Compatible with DS90LV047A

♦ Guaranteed 800Mbps Data Rate

♦ 250ps Maximum Pulse Skew

♦ Conforms to TIA/EIA-644 LVDS Standard

♦ Single +3.3V Supply

♦ 16-Pin TSSOP and SO Packages

MAX9123

Quad LVDS Line Driver with

Flow-Through Pinout

________________________________________________________________ Maxim Integrated Products 1

EN OUT1-

OUT1+

OUT2+

OUT2-

OUT3-

OUT3+

OUT4+

OUT4-

TOP VIEW

MAX9123

TSSOP/SO

IN1

IN2

IN3

GND

IN4

Pin Configuration

Ordering Information

107Ω

MAX9123

MAX9122*

107Ω

LVDS SIGNALS

100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES

LVTTL/CMOS

DATA INPUT

LVTTL/CMOS

DATA OUTPUT

Typical Applications Circuit

19-1927; Rev 0; 2/01

For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PART TEMP. RANGE PIN-PACKAGE

MAX9123EUE -40°C to +85°C 16 TSSOP

MAX9123ESE -40°C to +85°C 16 SO

* Future product—contact factory for availability.

Digital Copiers

Laser Printers

Cell Phone Base

Stations

Add Drop Muxes

Digital Cross-Connects

DSLAMs

Network

Switches/Routers

Backplane

Interconnect

Clock Distribution

Summary of content (10 pages)

PAGE 1
9-1927; Rev 0; 2/01 Quad LVDS Line Driver with Flow-Through Pinout The MAX9123 operates from a single +3.3V supply and is specified for operation from -40°C to +85°C. It is available in 16-pin TSSOP and SO packages. Refer to the MAX9121/ MAX9122* data sheet for quad LVDS line receivers with integrated termination and flow-through pinout.
PAGE 2
MAX9123 Quad LVDS Line Driver with Flow-Through Pinout ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-0.3V to (VCC + 0.3V) OUT_+, OUT_- to GND..........................................-0.3V to +3.9V Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW 16-Pin SO (derate 8.
PAGE 3
Quad LVDS Line Driver with Flow-Through Pinout (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 15pF, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 4, 5, 6) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Propagation Delay High to Low tPHLD Figures 2 and 3 0.7 1.7 ns Differential Propagation Delay Low to High tPLHD Figures 2 and 3 0.7 1.7 ns Differential Pulse Skew (Note 7) tSKD1 Figures 2 and 3 0.04 0.
PAGE 4
Typical Operating Characteristics (VCC = +3.3V, RL = 100Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) OUTPUT LOW VOLTAGE vs. POWER-SUPPLY VOLTAGE 1.094 1.092 1.090 1.090 3.3 POWER-SUPPLY VOLTAGE (V) OUTPUT HIGH-IMPEDANCE STATE CURRENT vs. POWER-SUPPLY VOLTAGE DIFFERENTIAL OUTPUT VOLTAGE vs. POWER SUPPLY -100 -150 -200 -250 -3.670 -3.665 -3.660 -3.655 385 3.0 380 375 370 365 360 355 OFFSET VOLTAGE vs. POWER-SUPPLY VOLTAGE 1.252 1.248 1.244 3.3 500 450 400 350 3.
PAGE 5
Quad LVDS Line Driver with Flow-Through Pinout 22.0 21.0 20.0 1.550 1.500 1.600 MAX9123 toc11 FREQ = 1MHz DIFFERENTIAL PROPAGATION DELAY (ns) 23.0 1.600 DIFFERENTIAL PROPAGATION DELAY (ns) tPLHD 1.450 1.400 tPHLD 1.350 1.300 1.250 -15 10 35 60 85 3.0 AMBIENT TEMPERATURE (°C) 3.3 1.400 1.300 tPHLD FREQ = 1MHz 1.200 -40 3.6 -15 FREQ = 1MHz 200 60 40 FREQ = 1MHz 175 DIFFERENTIAL SKEW (ps) 80 35 60 85 DIFFERENTIAL SKEW vs.
PAGE 6
Quad LVDS Line Driver with Flow-Through Pinout MAX9123 Pin Description PIN NAME FUNCTION 1 EN Driver Enable Input. The driver is disabled when EN is low. EN is internally pulled down. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and are high impedance. 2, 3, 6, 7 IN_ LVTTL/LVCMOS Driver Inputs 4 VCC Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
PAGE 7
Quad LVDS Line Driver with Flow-Through Pinout OUT_ + RL/2 IN_ IN_ S VOS GND VOD VO VCC MAX9123 CL OUT_+ GENERATOR RL/2 RL OUT_ - 50Ω CL OUT_- Figure 2. Driver Propagation Delay and Transition Time Test Circuit Figure 1. Driver VOD and VOS Test Circuit 3V IN_ 1.5V 1.5V tPLHD tPHLD 0 OUT_ - VOH 0 DIFFERENTIAL 0 OUT_+ VOL 80% 0 VDIFF 80% VDIFF = (VOUT_+) - (VOUT_-) 0 20% 20% tTLH tTHL Figure 3.
PAGE 8
MAX9123 Quad LVDS Line Driver with Flow-Through Pinout Functional Diagram CL OUT1+ OUT_+ VCC IN_ IN1 RL/2 OUT1- GND +1.2V EN GENERATOR RL/2 EN 50Ω OUT2+ OUT_- 1/4 MAX9123 IN2 CL OUT2- Figure 4. Driver High-Impedance Delay Test Circuit OUT3+ IN3 OUT3- OUT4+ IN4 OUT4- EN EN EN WHEN EN = 0 OR OPEN 3V 1.5V 1.5V 0 3V 1.5V 1.5V EN WHEN EN = VCC 0 tPZH tPHZ OUT_+ WHEN IN_ = VCC OUT_- WHEN IN_ = 0 VOH 50% 50% 1.2V 1.
PAGE 9
Quad LVDS Line Driver with Flow-Through Pinout TSSOP,NO PADS.
PAGE 10
Quad LVDS Line Driver with Flow-Through Pinout SOICN.EPS MAX9123 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.