Datasheet

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MAX9150

Low-Jitter, 10-Port LVDS Repeater

________________________________________________________________

Maxim Integrated Products

19-1815; Rev 1; 3/09

EVALUATION KIT

AVAILABLE

Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX9150EUI -40°C to +85°C 28 TSSOP

100Ω

LVDS

BACKPLANE

OR CABLE

100Ω

MAX9150

MAX9111

MAX9110

Typical Application Circuit

DO3+

DO3-

DO4+

DO4-

DO5+

DO5-

DO8-

GND

DO6+

DO6-

DO7+

DO7-

DO8+

DO9-

DO9+

DO10-

DO10+

GND

RIN-

RIN+

GND

DO1-

DO1+

DO2-

DO2+

TOP VIEW

MAX9150

PWRDN

TSSOP

Pin Configuration

General Description

The MAX9150 low-jitter, 10-port, low-voltage differential

signaling (LVDS) repeater is designed for applications

that require high-speed data or clock distribution while

minimizing power, space, and noise. The device

accepts a single LVDS input and repeats the signal at

10 LVDS outputs. Each differential output drives a total

of 50Ω, allowing point-to-point distribution of signals on

transmission lines with 100Ω terminations on each end.

Ultra-low 120ps (max) peak-to-peak jitter (deterministic

and random) ensures reliable communication in high-

speed links that are highly sensitive to timing error,

especially those incorporating clock-and-data recovery,

or serializers and deserializers. The high-speed switch-

ing performance guarantees 400Mbps data rate and

less than 100ps skew between channels while operat-

ing from a single +3.3V supply.

Supply current at 400Mbps is 160mA (max) and is

reduced to 60µA (max) in low-power shutdown mode.

Inputs and outputs conform to the EIA/TIA-644 LVDS

standard. A fail-safe feature sets the outputs high when

the input is undriven and open, terminated, or shorted.

The MAX9150 is available in a 28-pin TSSOP package.

Refer to the MAX9110/MAX9112 and MAX9111/MAX9113

data sheets for LVDS line drivers and receivers.

________________________Applications

Cellular Phone Base Stations

Add/Drop Muxes

Digital Crossconnects

Network Switches/Routers

Backplane Interconnect

Clock Distribution

Features

♦ Ultra-Low 120ps

p-p

(max) Total Jitter

(Deterministic and Random)

♦ 100ps (max) Skew Between Channels

♦ Guaranteed 400Mbps Data Rate

♦ 60µA Shutdown Supply Current

♦ Conforms to EIA/TIA-644 LVDS Standard

♦ Single +3.3V Supply

♦ Fail-Safe Circuit Sets Output High for Undriven

Inputs

♦ High-Impedance LVDS Input when V

= 0V

For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Summary of content (10 pages)

PAGE 1
9-1815; Rev 1; 3/09 KIT ATION EVALU E L B AVAILA Low-Jitter, 10-Port LVDS Repeater The MAX9150 low-jitter, 10-port, low-voltage differential signaling (LVDS) repeater is designed for applications that require high-speed data or clock distribution while minimizing power, space, and noise. The device accepts a single LVDS input and repeats the signal at 10 LVDS outputs.
PAGE 2
MAX9150 Low-Jitter, 10-Port LVDS Repeater ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V RIN+, RIN- to GND ................................................-0.3V to +4.0V PWRDN to GND..........................................-0.3V to (VCC + 0.3V) DO_+, DO_- to GND..............................................-0.3V to +4.0V Short-Circuit Duration (DO_+, DO_-) .........................
PAGE 3
Low-Jitter, 10-Port LVDS Repeater (VCC = +3.0V to +3.6V, RL = 50Ω ±1%, |VID| = 0.1V to 1.0V, VCM = |VID / 2| to 2.4V - |VID / 2|, PWRDN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1) PARAMETER Single-Ended Output HighImpedance Current SYMBOL IOZ CONDITIONS MIN TYP MAX UNITS VCC = 0V, PWRDN = GND; VDO_+ = 3.6V or 0V, DO_- = open; or VDO_- = 3.6V or 0V, DO_+ = open -1 +1 µA PWRDN = GND; VDO_+ = 3.6V or 0V, DO_- = open; or VDO_- = 3.
PAGE 4
AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, RL = 50Ω ±1%, CL = 5pF, |VID| = 0.2V to 1.0V, VCM = |VID / 2| to 2.4V - |VID / 2|, PWRDN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Notes 2–5) PARAMETER SYMBOL Power-Down Time tPD Power-Up Time tPU CONDITIONS MIN TYP Figures 4, 5 MAX UNITS 100 ns 100 µs Note 1: Current-into-device pins is defined as positive. Current-out-of-device pins is defined as negative.
PAGE 5
Low-Jitter, 10-Port LVDS Repeater (Figure 2, VCC = +3.3V, RL = 50Ω, CL = 5pF, IVIDI = 200 mV, VCM = 1.2V, fIN = 50MHz, TA = +25°C, unless otherwise noted.) 2.35 tPLHD 2.30 2.25 tPHLD 2.20 2.15 TRANSITION TIME vs. SUPPLY VOLTAGE H 30 G 20 215 210 TRANSITION TIME (ps) 2.40 40 MAX9150 toc05 DIFFERENTIAL OUTPUT-TO-OUTPUT SKEW (ps) MAX9150 toc04 2.45 B A, E 10 F, I D 0 C -10 1.0 1.5 2.0 2.5 205 200 195 tTHL 185 3.0 3.1 3.2 VCM (V) 3.3 3.4 3.5 3.0 3.6 3.1 3.
PAGE 6
Low-Jitter, 10-Port LVDS Repeater MAX9150 Pin Description PIN NAME FUNCTION 1, 3, 11, 13, 16, 18, 20, 24, 26, 28 DO2+, DO1+, DO10+, DO9+, DO8+, DO7+, DO6+, DO5+, DO4+, DO3+ 2, 4, 12, 14, 15, 17, 19, 23, 25, 27 DO2-, DO1-, DO10-, DO9-, DO8-, DO7-, DO6-, DO5-, DO4-, DO3- 5 PWRDN 6, 9, 21 GND Ground 10, 22 VCC Power. Bypass each VCC pin to GND with 0.1µF and 1nF ceramic capacitors. 7 RIN+ 8 RIN- LVDS Receiver Inputs. RIN+ and RIN- are high-impedance inputs.
PAGE 7
Low-Jitter, 10-Port LVDS Repeater Supply Bypassing Bypass each of the VCC pins with high-frequency surface-mount ceramic 0.1µF and 1nF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to the VCC pins. Differential Traces Output trace characteristics affect the performance of the MAX9150. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor.
PAGE 8
Low-Jitter, 10-Port LVDS Repeater MAX9150 Test Circuits and Timing Diagrams (continued) CL 5pF MAX9150 DO1+ RL 50Ω DO1- CL 5pF 50Ω CL 5pF RIN+ GENERATOR DO10+ RINRL 50Ω 50Ω DO10- CL 5pF Figure 2. Repeater Propagation Delay and Transition Time Test Circuit RIN0 VCM DIFFERENTIAL VID VCM RIN+ tPLHD tPHLD 80% 50% O 80% VDIFF = (VDO_+) - (VDO_-) O 50% 20% 20% tTLH tTHL Figure 3.
PAGE 9
Low-Jitter, 10-Port LVDS Repeater CL 5pF DO1+ RL 25Ω MAX9150 RL 25Ω DO1- CL 5pF 1.2V 1.1V CL 5pF RIN+ 1.0V 1.1V DO10+ RL 25Ω RIN- 1.0V GENERATOR RL 25Ω DO10- CL 5pF PWRDN 1.2V 50Ω Figure 4. Power-Up/Down Delay Test Circuit 3.0V PWRDN 1.5V 1.5V tPD tPU O VOH 50% VDO_+ WHEN VID = +100mV VDO_- WHEN VID = -100mV 50% 1.2V 1.2V VDO_+ WHEN VID = -100mV VDO_- WHEN VID = +100mV 50% 50% tPU tPD VOL Figure 5.
PAGE 10
MAX9150 Low-Jitter, 10-Port LVDS Repeater Revision History REVISION NUMBER REVISION DATE 0 10/00 Initial release — 1 3/09 Replaced the obsolete Rev C package outline drawing with the Package Information table 9 DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.