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19-2029; Rev 2; 10/12

MAX9205/MAX9207

10-Bit Bus LVDS Serializers

EVALUATION KIT AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

General Description

The MAX9205/MAX9207 serializers transform 10-bit-

wide parallel LVCMOS/LVTTL data into a serial high-

speed bus low-voltage differential signaling (LVDS)

data stream. The serializers typically pair with deserial-

izers like the MAX9206/MAX9208, which receive the

serial output and transform it back to 10-bit-wide paral-

lel data.

The MAX9205/MAX9207 transmit serial data at speeds

up to 400Mbps and 660Mbps, respectively, over PCB

traces or twisted-pair cables. Since the clock is recov-

ered from the serial data stream, clock-to-data and

data-to-data skew that would be present with a parallel

bus are eliminated.

The serializers require no external components and few

control signals. The input data strobe edge is selected

by TCLK_R/F. PWRDN is used to save power when the

devices are not in use. Upon power-up, a synchroniza-

tion mode is activated, which is controlled by two SYNC

inputs, SYNC1 and SYNC2.

The MAX9205 can lock to a 16MHz to 40MHz system

clock, while the MAX9207 can lock to a 40MHz to

66MHz system clock. The serializer output is held in

high impedance until the device is fully locked to the

local system clock, or when the device is in power-

down mode.

Both the devices operate from a single +3.3V supply,

are specified for operation from -40°C to +85°C, and

are available in 28-pin SSOP packages.

Applications

Features

o Standalone Serializer (vs. SERDES) Ideal for

Unidirectional Links

o Framing Bits for Deserializer Resync Allow Hot

Insertion Without System Interruption

o LVDS Serial Output Rated for Point-to-Point and

Bus Applications

o Wide Reference Clock Input Range

16MHz to 40MHz (MAX9205)

40MHz to 66MHz (MAX9207)

o Low 140ps (pk-pk) Deterministic Jitter (MAX9207)

o Low 34mA Supply Current (MAX9205)

o 10-Bit Parallel LVCMOS/LVTTL Interface

o Up to 660Mbps Payload Data Rate (MAX9207)

o Programmable Active Edge on Input Latch

o Pin-Compatible Upgrades to DS92LV1021 and

DS92LV1023

PCB OR

TWISTED PAIR

TCLK

PLL

PWRDN

INPUT LATCH

PARALLEL-TO-SERIAL

OUTPUT LATCH

SERIAL-TO-PARALLEL

TIMING AND

CONTROL

TIMING AND

CONTROL

CLOCK

RECOVERY

RCLK

LOCK

SYNC 1

SYNC 2

OUT+

OUT-

IN+

IN-

100Ω 100Ω

TCLK_R/F

RCLK_R/F

REFCLK

OUT_

IN_

BUS

LVDS

MAX9205

MAX9207

MAX9206

MAX9208

Ordering Information

PART

TEMP

RANGE

PIN-

PACKAGE

REF CLOCK

RANGE

(MHz)

MAX9205EAI+ -40°C to +85°C 28 SSOP 16 to 40

M AX 9205E AI/V + -40°C to +85°C 28 SSOP 16 to 40

MAX9207EAI+ -40°C to +85°C 28 SSOP 40 to 66

Pin Configuration and Functional Diagram appear at end of

data sheet.

Typical Application Circuit

Cellular Phone Base

Stations

Add Drop Muxes

Digital Cross-Connects

DSLAMs

Network Switches and

Routers

Backplane Interconnect

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

Summary of content (13 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX9205/MAX9207 10-Bit Bus LVDS Serializers General Description The MAX9205/MAX9207 serializers transform 10-bitwide parallel LVCMOS/LVTTL data into a serial highspeed bus low-voltage differential signaling (LVDS) data stream. The serializers typically pair with deserializers like the MAX9206/MAX9208, which receive the serial output and transform it back to 10-bit-wide parallel data.
PAGE 2
MAX9205/MAX9207 10-Bit Bus LVDS Serializers ABSOLUTE MAXIMUM RATINGS Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Operating Temperature Range ...........................-40°C to +85°C ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................
PAGE 3
MAX9205/MAX9207 10-Bit Bus LVDS Serializers AC ELECTRICAL CHARACTERISTICS (VAVCC = VDVCC = +3.0V to +3.6V, RL = 27Ω ±1% or 50Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VAVCC = VDVCC = +3.3V and TA = +25°C, unless otherwise noted.
PAGE 4
MAX9205/MAX9207 10-Bit Bus LVDS Serializers AC ELECTRICAL CHARACTERISTICS (continued) (VAVCC = VDVCC = +3.0V to +3.6V, RL = 27Ω ±1% or 50Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VAVCC = VDVCC = +3.3V and TA = +25°C, unless otherwise noted.
PAGE 5
MAX9205/MAX9207 10-Bit Bus LVDS Serializers Pin Description PIN NAME 1, 2 SYNC 1, SYNC 2 3–12 IN0–IN9 FUNCTION LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024 SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns continue to be sent until the SYNC pin is asserted low.
PAGE 6
MAX9205/MAX9207 10-Bit Bus LVDS Serializers Initialization Mode When V CC is applied, the outputs are held in high impedance and internal circuitry is disabled by on-chip power-on-reset circuitry. When the supply voltage reaches 2.35V, the PLL starts to lock to a local reference clock (16MHz to 40MHz for MAX9205 and 40MHz to 66MHz for MAX9207). The reference clock, TCLK, is provided by the system. A serializer locks within 2049 cycles of TCLK.
PAGE 7
MAX9205/MAX9207 10-Bit Bus LVDS Serializers Applications Information Power-Supply Bypassing Bypass AVCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to AVCC. Bypass DVCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to DVCC.
PAGE 8
MAX9205/MAX9207 10-Bit Bus LVDS Serializers 10pF OUT+ 80% 80% VDIFF = 0 RL 20% VDIFF 20% OUT10pF tLHT tHLT VDIFF = (OUT+) - (OUT-) Figure 4. Output Load and Transition Times tTCP 1.5V TCLK 1.5V tS tH 1.5V IN_ 1.5V 1.5V TIMING SHOWN FOR TCLK_R/F = LOW Figure 5. Data Input Setup and Hold Times PARASITIC PACKAGE AND TRACE CAPACITANCE 10pF OUT+ 13.5Ω +1.1V OUT- 13.5Ω EN 10pF 3V 1.5V EN 1.5V 0 tZH tHZ VOH 50% 50% 1.1V OUT± tZL tLZ 1.1V 50% 50% VOL Figure 6.
PAGE 9
MAX9205/MAX9207 10-Bit Bus LVDS Serializers 2.0V PWRDN 0.8V tPL tHZ OR tLZ TCLK 1.5V tZH OR tZL OUT± ACTIVE HIGH IMPEDANCE HIGH IMPEDANCE SYNC 1 = SYNC 2 = LOW EN = HIGH TCLK_R/F = HIGH Figure 7. PLL Lock Time and PWRDN High-Impedance Delays IN IN0 - IN9 SYMBOL N + 1 IN0 - IN9 SYMBOL N tSD TCLK 1.5V TIMING SHOWN FOR TCLK_R/F = HIGH START BIT OUT0 - OUT9 SYMBOL N STOP BIT START BIT OUT0 - OUT9 SYMBOL N+1 STOP BIT OUT± TCLK_ R/F = HIGH VDIFF = 0 VDIFF = (OUT+) - (OUT-) Figure 8.
PAGE 10
MAX9205/MAX9207 10-Bit Bus LVDS Serializers Topologies reduces reflections compared to a single 100Ω termination. A single 100Ω termination at the deserializer input is feasible and will make the differential signal swing larger. A serializer located at one end of a backplane bus driving multiple deserializers in a multidrop configuration is shown in Figure 12. A 54Ω resistor at the far end terminates the bus. This topology allows “broadcast” of data with a minimum of interconnect.
PAGE 11
MAX9205/MAX9207 10-Bit Bus LVDS Serializers A point-to-point version of the multidrop bus is shown in Figure 13. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Compared to the multidrop bus, more interconnect is traded for more robust hot-plug capability. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections.
PAGE 12
MAX9205/MAX9207 10-Bit Bus LVDS Serializers ASIC ASIC MAX9205 MAX9207 MAX9205 MAX9207 ASIC ASIC MAX9206 MAX9208 ASIC MAX9206 MAX9208 MAX9206 MAX9208 54Ω 54Ω Figure 14.
PAGE 13
MAX9205/MAX9207 10-Bit Bus LVDS Serializers Revision History REVISION REVISION NUMBER DATE DESCRIPTION Initial release PAGES CHANGED 0 5/01 1 11/10 Updated Ordering Information, Absolute Maximum Ratings, and Package 1, 2, 13 — 2 10/12 Added Package Thermal Characteristics section and updated the Electrical Characteristics and the Power-Down sections 2–4, 6 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product