Datasheet

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General Description

The MAX9206/MAX9208 deserializers transform a high-

speed serial bus low-voltage differential signaling

(BLVDS) data stream into 10-bit-wide parallel LVCMOS/

LVTTL data and clock. The deserializers pair with seri-

alizers such as the MAX9205/MAX9207, which gener-

ate a serial BLVDS signal from 10-bit-wide parallel

data. The serializer/deserializer combination reduces

interconnect, simplifies PCB layout, and reduces board

size.

The MAX9206/MAX9208 receive serial data at

450Mbps and 600Mbps, respectively, over board

traces or twisted-pair cables. These devices combine

frequency lock, bit lock, and frame lock to produce a

parallel-rate clock and word-aligned 10-bit data.

Serialization eliminates parallel bus clock-to-data and

data-to-data skew.

A power-down mode reduces typical supply current to

less than 600µA. Upon power-up (applying power or

driving PWRDN high), the MAX9206/MAX9208 estab-

lish lock after receiving synchronization signals or serial

data from the MAX9205/MAX9207. An output enable

allows the outputs to be disabled, putting the parallel

data outputs and recovered output clock into a high-

impedance state without losing lock.

The MAX9206/MAX9208 operate from a single +3.3V

supply and are specified for operation from -40°C to

+85°C. The MAX9206/MAX9208 are available in 28-pin

SSOP packages.

Applications

Features

o Stand-Alone Deserializer (vs. SerDes) Ideal for

Unidirectional Links

o Automatic Clock Recovery

o Allow Hot Insertion and Synchronization Without

System Interruption

o BLVDS Serial Input Rated for Point-to-Point and

Bus Applications

o Fast Pseudorandom Lock

o Wide Reference Clock Input Range

16MHz to 45MHz (MAX9206)

40MHz to 60MHz (MAX9208)

o High 720ps (p-p) Jitter Tolerance (MAX9206)

o Low 30mA Supply Current (MAX9206 at 16MHz)

o 10-Bit Parallel LVCMOS/LVTTL Output

o Up to 600Mbps Throughput (MAX9208)

o Programmable Output Strobe Edge

o Pin Compatible to DS92LV1212A and

DS92LV1224

MAX9206/MAX9208

10-Bit Bus LVDS Deserializers

________________________________________________________________

Maxim Integrated Products

19-2130; Rev 2; 11/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART

TEMP

RANGE

PIN-

PACKAGE

REF CLOCK

RANGE

(MHz)

MAX9206EAI+ -40°C to +85°C 28 SSOP 16 to 40

MAX9206EAI/V+ -40°C to +85°C 28 SSOP 16 to 40

MAX9208EAI+ -40°C to +85°C 28 SSOP 40 to 66

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

PCB OR TWISTED PAIR

TCLK

PLL

REN

PWRDN

INPUT LATCH

PARALLEL-TO-SERIAL

OUTPUT LATCH

SERIAL-TO-PARALLEL

TIMING AND

CONTROL

TIMING AND

CONTROL

CLOCK

RECOVERY

RCLK

LOCK

SYNC 1

SYNC 2

OUT+

OUT-

RI+

RI-

100Ω 100Ω

TCLK_R/F

RCLK_R/F

REFCLK

ROUT_

IN_

BUS

LVDS

MAX9205

MAX9207

MAX9206

MAX9208

Typical Operating Circuit

Cellular Phone Base

Stations

Add/Drop Muxes

Digital Cross-Connects

DSLAMs

Network Switches and

Routers

Backplane Interconnect

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

Summary of content (12 pages)

PAGE 1
9-2130; Rev 2; 11/10 KIT ATION EVALU ABLE AVAIL 10-Bit Bus LVDS Deserializers The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling (BLVDS) data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel data. The serializer/deserializer combination reduces interconnect, simplifies PCB layout, and reduces board size.
PAGE 2
MAX9206/MAX9208 10-Bit Bus LVDS Deserializers ABSOLUTE MAXIMUM RATINGS AVCC, DVCC to AGND, DGND................................-0.3V to +4V RI+, RI- to AGND, DGND .........................................-0.3V to +4V All Other Pins to DGND ..............................-0.3V to DVCC + 0.3V ROUT_ Short-Circuit Duration (Note 1) ......................Continuous Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW Operating Temperature Range ....................
PAGE 3
10-Bit Bus LVDS Deserializers (VAVCC = VDVCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC = VDVCC = +3.3V, VCM = 1.1V, |VID| = 0.2V, TA = +25°C.
PAGE 4
MAX9206/MAX9208 10-Bit Bus LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (continued) (VAVCC = VDVCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC = VDVCC = +3.3V, VCM = 1.1V, |VID| = 0.2V, TA = +25°C.
PAGE 5
10-Bit Bus LVDS Deserializers PIN NAME FUNCTION 1, 12, 13 AGND 2 RCLK_R/F 3 REFCLK 4, 11 AVCC 5 RI+ Serial Data Input. Noninverting BLVDS differential input. 6 RI- Serial Data Input. Inverting BLVDS differential input. 7 PWRDN 8 REN Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high impedance. LOCK remains active, indicating the status of the serial input. 9 RCLK Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
PAGE 6
10-Bit Bus LVDS Deserializers MAX9206/MAX9208 Test Circuits/Timing Diagrams (continued) VCC LVCMOS/LVTTL OUTPUT RIN2 CL 15pF TO DESERIALIZING CIRCUITRY VCC - 0.3V RI+ RIN1 80% 80% 20% 20% RIN1 tCHL tCLH RI- Figure 3. LVCMOS/LVTTL Output Load and Transition Times Figure 2. Input Fail-Safe Circuit START BIT 0 RI START SYMBOL N 1 2 3 4 5 6 7 8 END BIT 9 BIT 0 tDD 1 2 SYMBOL N+1 3 4 5 6 7 8 START END BIT 9 BIT 0 1 2 RCLK RCLK_R/F = HIGH SYMBOL N-1 ROUT_ SYMBOL N Figure 4.
PAGE 7
10-Bit Bus LVDS Deserializers tDSR1 ≤ (2048 + 42)tRFCP PWRDN REFCLK tRFCP SYNC PATTERNS DATA 111111 RI DON'T CARE 000000 tZHLK tDD LOCK HIGH-Z RCLK HIGH-Z ROUT_ HIGH-Z HIGH-Z HIGH-Z tHZR OR tLZR tRCP SYNC HIGH-Z DATA RCLK_R/F = LOW ≤42 x tRFCP 2048 x tRFCP Figure 7. PLL Lock Time from PWRDN REFCLK tRFCP DATA SYNC PATTERNS 111111 RI 000000 tDD LOCK tDSR2 ≤42tRFCP RCLK tRCP SYNC ROUT_ DATA DATA DATA RCLK_R/F = LOW Figure 8.
PAGE 8
MAX9206/MAX9208 10-Bit Bus LVDS Deserializers Detailed Description The MAX9206/MAX9208 deserialize a BLVDS serializer's output into 10-bit wide parallel LVCMOS/LVTTL data and a parallel rate clock. The MAX9206/MAX9208 include a PLL that locks to the frequency and phase of the serial input, and digital circuits that deserialize and deframe the data. The MAX9206/MAX9208 have highinput jitter tolerance while receiving data at speeds from 160Mbps to 600Mbps.
PAGE 9
10-Bit Bus LVDS Deserializers MAX9206/MAX9208 Table 1. Typical Lock Times REFCLK FREQUENCY 16MHz 35MHz 40MHz 40MHz DATA PATTERN PSEUDORANDOM DATA PSEUDORANDOM DATA PSEUDORANDOM DATA SYNC PATTERNS 0.749μs 0.375μs 0.354μs 0.134μs 11.99 13.14 14.18 5.37 0.318μs 0.158μs 0.144μs 0.103μs 5.09 5.52 5.76 4.11 0.13μs 0.068μs 0.061μs 0.061μs 2.08 2.37 2.44 2.
PAGE 10
MAX9206/MAX9208 10-Bit Bus LVDS Deserializers t RCP /12 t JT t JT V ID = 150mV Figure 9. Input Jitter Tolerance Applications Information simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. Eliminate reflections and ensure that noise couples as common mode by running differential traces close together.
PAGE 11
10-Bit Bus LVDS Deserializers LOGIC INPUTS CONDITIONS OUTPUTS Low Power applied and stable Power-down mode. PLL is stopped. Current consumption is reduced to 400μA (typ). ROUT_, RCLK, and LOCK are high impedance. Low High Deserializer initialized RCLK and ROUT_ are high impedance. LOCK is active, indicating the serial input status. High High Deserializer initialized RCLK and ROUT_ are active. LOCK is active, indicating the serial input status. REN PWRDN X X = Don’t care.
PAGE 12
MAX9206/MAX9208 10-Bit Bus LVDS Deserializers Revision History REVISION NUMBER REVISION DATE 0 8/01 Initial release 1 12/07 Max clock frequency increased to 45MHz; min values decreased for REFCLK and RCLK period; updated package outline; updated names for pins 2 and 3.