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General Description

The MAX9217 digital video parallel-to-serial converter

serializes 27 bits of parallel data into a serial data stream.

Eighteen bits of video data and 9 bits of control data are

encoded and multiplexed onto the serial interface, reduc-

ing the serial data rate. The data enable input determines

when the video or control data is serialized.

The MAX9217 pairs with the MAX9218 deserializer to

form a complete digital video serial link. Interconnect

can be controlled-impedance PCB traces or twisted-pair

cable. Proprietary data encoding reduces EMI and pro-

vides DC balance. DC balance allows AC-coupling,

providing isolation between the transmitting and receiv-

ing ends of the interface. The LVDS output is internally

terminated with 100Ω.

ESD tolerance is specified for ISO 10605 with ±10kV

contact discharge and ±30kV air discharge.

The MAX9217 operates from a +3.3V core supply and

features a separate input supply for interfacing to 1.8V

to 3.3V logic levels. This device is available in 48-lead

Thin QFN and LQFP packages and is specified from

-40°C to +85°C.

Applications

Navigation System Display

In-Vehicle Entertainment System

Video Camera

LCD Displays

Features

♦ Proprietary Data Encoding for DC Balance and

Reduced EMI

♦ Control Data Sent During Video Blanking

♦ Five Control Data Inputs Are Single-Bit-Error

Tolerant

♦ Output Common-Mode Filter Reduces EMI

♦ Greater than 10m STP Cable Drive

♦ Wide ±2% Reference Clock Tolerance

♦ ISO 10605 ESD Protection

♦ Separate Input Supply Allows Interface to 1.8V to

3.3V Logic

♦ +3.3V Core Supply

♦ Space-Saving Thin QFN and LQFP Packages

♦ -40°C to +85°C Operating Temperature

MAX9217

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Serializer

________________________________________________________________

Maxim Integrated Products

RNG0

RNG1

CCLVDS

OUT+

OUT-

LVDS GND

CMF

PWRDWN

CCPLL

PLL GND

I.C.

GND

CCIN

RGB_IN10

RGB_IN11

RGB_IN12

RGB_IN13

RGB_IN14

RGB_IN15

RGB_IN16

RGB_IN17

CNTL_IN0

CNTL_IN1

RNG0

RNG1

CCLVDS

OUT+

OUT-

LVDS GND

CMF

PWRDWN

CCPLL

PLL GND

I.C.

TOP VIEW

I.C.

PCLK_IN

DE_IN

CNTL_IN8

CNTL_IN7

CNTL_IN6

CNTL_IN5

CNTL_IN4

CNTL_IN3

CNTL_IN2

GND

RGB_IN0

RGB_IN1

RGB_IN2

RGB_IN3

RGB_IN4

RGB_IN5

RGB_IN6

RGB_IN7

RGB_IN8

RGB_IN9

GND

CCIN

RGB_IN10

RGB_IN11

RGB_IN12

RGB_IN13

RGB_IN14

RGB_IN15

RGB_IN16

RGB_IN17

CNTL_IN0

CNTL_IN1

LQFP

MAX9217

I.C

PCLK_IN

DE_IN

CNTL_IN8

CNTL_IN7

CNTL_IN6

CNTL_IN5

CNTL_IN4

CNTL_IN3

CNTL_IN2

GND

RGB_IN0

RGB_IN1

RGB_IN2

RGB_IN3

RGB_IN4

RGB_IN5

RGB_IN6

RGB_IN7

RGB_IN8

RGB_IN9

THIN QFN-EP

PART TEMP RANGE

PIN-

PACKAGE

MAX9217ECM+ -40°C to +85°C 48 LQFP

MAX9217ECM/V+ -40°C to +85°C 48 LQFP

MAX9217ETM+ -40°C to +85°C 48 Thin QFN-EP*

Pin Configurations

Ordering Information

19-3558; Rev 4; 8/09

EVALUATION KIT

AVAILABLE

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

EP = Exposed pad.

Summary of content (15 pages)

PAGE 1
9-3558; Rev 4; 8/09 KIT ATION EVALU E L B A AVAIL 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines when the video or control data is serialized.
PAGE 2
MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer ABSOLUTE MAXIMUM RATINGS VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V OUT+, OUT- Short Circuit to LVDS GND or VCCLVDS .............................................................Continuous OUT+, OUT- Short Through 0.125µF (or smaller), 25V Series Capacitor...........
PAGE 3
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, PWRDWN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.
PAGE 4
AC ELECTRICAL CHARACTERISTICS (continued) (VCC_ = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, PWRDWN = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, TA = +25°C.) (Note 4) PARAMETER Peak-to-Peak Output Offset Voltage SYMBOL VOSp-p CONDITIONS MIN TYP MAX 700Mbps data rate, CMF open, Figure 8 22 70 700Mbps data rate, CMF 0.1µF to ground, Figure 8 12 50 UNITS mV Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative.
PAGE 5
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer PIN NAME 1, 13, 37 GND Input Buffer Supply and Digital Supply Ground 2 VCCIN Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 3–10, 39–48 RGB_IN[17:0] LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded into the input latch on the rising edge of PCLK_IN when DE_IN is high.
PAGE 6
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer MAX9217 Functional Diagram RGB_IN 1 INPUT LATCH CNTL_IN 0 OUT+ DC BALANCE/ ENCODE PAR-TO-SER CMF DE_IN PCLK_IN RNG0 RNG1 OUT- PLL TIMING AND CONTROL MAX9217 PWRDWN RL / 2 OUT+ VOD OUT- VOS RL / 2 GND ((OUT+) + (OUT-)) / 2 OUTVOS(-) VOS(+) VOS(-) OUT+ ΔVOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) ΔVOD = |VOD(+) - VOD(-)| (OUT+) - (OUT-) Figure 1.
PAGE 7
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer MAX9217 tT VIHmin tHIGH PCLK_IN VILmax tR tF tLOW Figure 2. Parallel Clock Requirements OUT+ RL OUTCL CL 80% 80% 20% 20% (OUT+) - (OUT-) tFALL tRISE Figure 3. Output Rise and Fall Times VIHmin PCLK_IN VILmax tSET tHOLD RGB_IN[17:0] VIHmin VIHmin VILmax VILmax CNTL_IN[8:0] DE_IN Figure 4.
PAGE 8
MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer EXPANDED TIME SCALE RGB_IN CNTL_IN N N+1 N+3 N+2 N+4 PCLK_IN N-1 N OUT_ tSD BIT 0 BIT 19 Figure 5. Serializer Delay VILmax PWRDWN tLOCK (OUT+) - (OUT-) VOD = 0V HIGH-Z PCLK_IN Figure 6. PLL Lock Time PWRDWN VILmax tPD (OUT+) - (OUT-) HIGH-Z PCLK_IN Figure 7.
PAGE 9
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer MAX9217 OUT- OUT+ ((OUT+) + (OUT-)) / 2 VOS(P-P) VOS(P-P) Figure 8. Peak-to-Peak Output Offset Voltage Detailed Description The MAX9217 DC-balanced serializer operates at a parallel clock frequency of 3MHz to 35MHz, serializing 18 bits of parallel video data RGB_IN[17:0] when the data enable input DE_IN is high, or 9 bits of parallel control data CNTL_IN[8:0] when DE_IN is low.
PAGE 10
MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer CONTROL PHASE TRANSITION PHASE VIDEO PHASE TRANSITION PHASE CONTROL PHASE PCLK_IN CNTL_IN DE_IN RGB_IN = NOT SAMPLED BY PCLK_IN Figure 9. Transition Timing Transition Timing The transition words require interconnect bandwidth and displace control data. Therefore, control data is not sampled (see Figure 9): • Two clock cycles before DE_IN goes high. • During the video phase. • Two clock cycles after DE_IN goes low.
PAGE 11
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer MAX9217 VCC 130Ω CMF DE_IN IN * 82Ω PLL 1 CNTL_OUT 0 DE_OUT PCLK_OUT PLL RNG1 TIMING AND CONTROL R/F OUTEN RGB_OUT 82Ω RNG0 PCLK_IN RNG0 RNG1 SER-TO-PAR OUT DC BALANCE/ DECODE 0 * PAR-TO-SER CNTL_IN 1 INPUT LATCH RGB_IN DC BALANCE/ ENCODE 130Ω REF_IN PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9217 MAX9218 CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPACITORS CAN BE AT EITHER END. Figure 10.
PAGE 12
MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Table 3. Parallel Clock Frequency Range Select AC-COUPLING CAPACITOR VALUE vs.
PAGE 13
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Power-Supply Circuits and Bypassing The MAX9217 has isolated on-chip power domains. The digital core supply (VCC) and single-ended input supply (VCCIN) are isolated but have a common ground (GND). The PLL has separate power and ground (VCCPLL and VCCPLL GND) and the LVDS input also has separate power and ground (VCCLVDS and VCCLVDS GND). The grounds are isolated by diode connections.
PAGE 14
MAX9217 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Board Layout Separate the LVTTL/LVCMOS inputs and LVDS output to prevent crosstalk. A four-layer PCB with separate layers for power, ground, and signals is recommended. ESD Protection The MAX9217 ESD tolerance is rated for Human Body Model, Machine Model, and ISO 10605. ISO 10605 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 0Ω RD 1.
PAGE 15
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer REVISION NUMBER REVISION DATE 3 5/08 Corrected LQFP package, removed MOD function pins, added Machine Model ESD, and corrected diagrams 4 8/09 Added automotive qualified part to Ordering Information DESCRIPTION PAGES CHANGED 1, 2, 5, 6, 10–15 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.