Datasheet

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General Description

The MAX9218 digital video serial-to-parallel converter

deserializes a total of 27 bits during data and control

phases. In the data phase, the LVDS serial input is con-

verted to 18 bits of parallel video data and in the control

phase, the input is converted to 9 bits of parallel control

data. The separate video and control phases take

advantage of video timing to reduce the serial data rate.

The MAX9218 pairs with the MAX9217 serializer to form

a complete digital video transmission system.

Proprietary data decoding reduces EMI and provides

DC balance. The DC balance allows AC-coupling, pro-

viding isolation between the transmitting and receiving

ends of the interface. The MAX9218 features a selec-

table rising or falling output latch edge.

ESD tolerance is specified for ISO 10605 with ±10kV

contact discharge and ±30kV air discharge.

The MAX9218 operates from a +3.3V core supply and

features a separate output supply for interfacing to 1.8V

to 3.3V logic-level inputs. This device is available in 48-

lead Thin QFN and LQFP packages and is specified

from -40°C to +85°C.

Applications

Navigation System Display

In-Vehicle Entertainment System

Video Camera

LCD Displays

Features

♦ Proprietary Data Decoding for DC Balance and

Reduced EMI

♦ Control Data Deserialized During Video Blanking

♦ Five Control Data Inputs Are Single Bit-Error

Tolerant

♦ Output Transition Time Is Scaled to Operating

Frequency for Reduced EMI

♦ Staggered Output Switching Reduces EMI

♦ Output Enable Allows Busing of Outputs

♦ Clock Pulse Stretch on Lock

♦ Wide ±2% Reference Clock Tolerance

♦ Synchronizes to MAX9217 Serializer Without

External Control

♦ ISO 10605 ESD Protection

♦ Separate Output Supply Allows Interface to 1.8V

to 3.3V Logic

♦ +3.3V Core Power Supply

♦ Space-Saving Thin QFN and LQFP Packages

♦ -40°C to +85°C Operating Temperature

MAX9218

27-Bit, 3MHz-to-35MHz

DC-Balanced LVDS Deserializer

________________________________________________________________

Maxim Integrated Products

DE_OUT

CNTL_OUT8

CNTL_OUT7

CNTL_OUT6

CNTL_OUT5

CNTL_OUT4

CNTL_OUT3

CNTL_OUT2

CNTL_OUT1T

CNTL_OUT0

OUTEN

PWRDWN

CCO

GND

CCO

RGB_OUT8

RGB_OUT9

RGB_OUT10

RGB_OUT11

RGB_OUT12

RGB_OUT13

RGB_OUT14

RGB_OUT15

RGB_OUT16

RGB_OUT17

LQFP

MAX9218

RGB_OUT7

RGB_OUT6

RGB_OUT5

RGB_OUT4

RGB_OUT3

RGB_OUT2

RGB_OUT1

RGB_OUT0

PCLK_OUT

LOCK

CCO

GND

R/F

RNG1

CCLVDS

IN+

IN-

LVDS GND

PLL GND

CCPLL

RNG0

GND

REFCLK

RGB_OUT7

RGB_OUT6

RGB_OUT4

RGB_OUT3

RGB_OUT0

PCLK_OUT

LOCK

CCO

GND

CCO

RGB_OUT2

RGB_OUT1

RGB_OUT5

TOP VIEW

CCLVDS

IN+

IN-

LVDS GND

PLL GND

CCPLL

RNG0

REFCLK

GND

RNG1

R/F

DE_OUT

CNTL_OUT8

CNTL_OUT6

CNTL_OUT5

CNTL_OUT2

CNTL_OUT1

CNTL_OUT0

PWRDWN

OUTEN

CNTL_OUT4

CNTL_OUT3

CNTL_OUT7

RGB_OUT8

RGB_OUT9

RGB_OUT10

RGB_OUT11

RGB_OUT12

RGB_OUT13

RGB_OUT14

RGB_OUT17

RGB_OUT15

CCO

GND

THIN QFN-EP

MAX9218

RGB_OUT16

PART TEMP RANGE PIN-PACKAGE

MAX9218ECM+ -40°C to +85°C 48 LQFP

MAX9218ECM/V+ -40°C to +85°C 48 LQFP

MAX9218ETM+ -40°C to +85°C 48 Thin QFN-EP*

Pin Configurations

Ordering Information

19-3557; Rev 5; 8/09

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

EP = Exposed pad.

EVALUATION KIT

AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim's website at www.maxim-ic.com.

Summary of content (15 pages)

PAGE 1
9-3557; Rev 5; 8/09 KIT ATION EVALU E L B A AVAIL 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial data rate.
PAGE 2
MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer ABSOLUTE MAXIMUM RATINGS VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V IN+, IN- to LVDS GND...........................................-0.5V to +4.0V IN+, IN- Short Circuit to LVDS GND or VCCLVDS ......Continuous IN+, IN- Short Through 0.125µF (or smaller), 25V Series Capacitor..........................................-0.
PAGE 3
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer (VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input common-mode voltage VCM = ⏐VID/2⏐ to VCC - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.
PAGE 4
MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer AC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to 3.6V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.1V to 1.2V, input common-mode voltage VCM = ⏐VID/2⏐ to VCC - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.
PAGE 5
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) 60 50 40 30 20 MAX9218 toc02 tR 5 4 tF 3 2 10 1 0 0 RNG1 = RNG0 = HIGH 3 7 11 15 19 23 27 31 35 1.8 2.1 2.4 2.7 3.0 FREQUENCY (MHz) OUTPUT SUPPLY VOLTAGE (V) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) BIT-ERROR RATE vs. CABLE LENGTH 6 10 -14 MAX9218 toc03 7 tR CAT5e 3.
PAGE 6
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218 Pin Description 6 PIN NAME FUNCTION 1 R/F Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch edge. Internally pulled down to GND. 2 RNG1 LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internally pulled down to GND.
PAGE 7
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer IN+ DC BALANCE/ DECODE IN- SER-TO-PAR 1 R/F OUTEN RGB_OUT[17:0] 0 CNTL_OUT[8:0] DE_OUT PCLK_OUT RNG0 RNG1 PLL REFCLK PWRDWN TIMING AND CONTROL LOCK MAX9218 IN+ 0.9VCCO DE_OUT RIB 1.2V LVDS RECEIVER LOCK PCLK_OUT 0.1VCCO RGB_OUT[17:0] RIB CNTL_OUT[8:0] tR tF IN- Figure 1. LVDS Input Bias Figure 3. Output Rise and Fall Times PCLK_OUT PCLK_OUT 2.0V tHIGH ODD RGB_OUT CNTL_OUT 0.
PAGE 8
MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer 2.0V PCLK_OUT 0.8V PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE) tDVB tDVA DE_OUT LOCK RGB_OUT[17:0] 2.0V 2.0V 0.8V 0.8V CNTL_OUT[8:0] Figure 5. Synchronous Output Timing 20 SERIAL BITS SERIAL-WORD N IN+, IN- PCLK_OUT SHOWN FOR R/F = HIGH SERIAL-WORD N + 1 tDELAY PCLK_OUT CNTL_OUT RGB_OUT PARALLEL-WORD N - 1 PARALLEL-WORD N Figure 6.
PAGE 9
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218 2.0V 0.8V PWRDWN tPLLREF TRANSITION WORD FOUND tPDD REFCLK RECOVERED CLOCK PCLK_OUT HIGH IMPEDANCE HIGH IMPEDANCE CLOCK STRETCH VALID DATA RGB_OUT CNTL_OUT DE_OUT HIGH IMPEDANCE HIGH IMPEDANCE LOCK HIGH IMPEDANCE HIGH IMPEDANCE NOTE: R/F = HIGH Figure 7. PLL Lock to REFCLK and Power-Down Delay OUTEN OUTEN 2.0V 0.
PAGE 10
MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer Detailed Description The MAX9218 DC-balanced deserializer operates at a parallel clock frequency of 3MHz to 35MHz, deserializing video data to the RGB_OUT[17:0] outputs when the data enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The video phase words are decoded using 2 overhead bits, EN0 and EN1. Control phase words are decoded with 1 overhead bit, EN0.
PAGE 11
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer OUT IN * CMF DE_IN 82Ω PLL 1 R/F OUTEN RGB_OUT 0 CNTL_OUT DE_OUT 82Ω PCLK_OUT RNG0 PCLK_IN RNG0 RNG1 DC BALANCE/ DECODE PAR-TO-SER 0 CNTL_IN DC BALANCE/ ENCODE 1 INPUT LATCH RGB_IN * SER-TO-PAR 130Ω 130Ω PLL RNG1 TIMING AND CONTROL REFCLK PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9217 MAX9218 CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPS CAN BE AT EITHER END. Figure 10.
PAGE 12
Input Frequency Detection A frequency-detection circuit detects when the LVDS input is not switching. When not switching, all outputs except LOCK are low, LOCK is high, and PCLK_OUT follows REFCLK. This condition occurs, for example, if the serializer is not driving the interconnect or if the interconnect is open. Frequency Range Setting (RNG[1:0]) The RNG[1:0] inputs select the operating frequency range of the MAX9218 and the transition time of the outputs.
PAGE 13
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer RGB_OUT[17:0] are grouped into three groups of six, with each group switching about 1ns apart in the video phase to reduce EMI and ground bounce. CNTL_OUT[8:0] switch during the control phase. Output transition times are slower in the 3MHz-to-7MHz and 7MHz-to-15MHz ranges and faster in the 15MHz-to35MHz range. (VCCLVDS supply and VCCLVDS GND). The grounds are isolated by diode connections.
PAGE 14
MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer ESD Protection The MAX9218 ESD tolerance is rated for the Human Body Model, Machine Model, and ISO 10605. ISO 10605 specifies ESD tolerance for electronic systems. 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1.5kΩ RD 0Ω CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 14.
PAGE 15
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer REVISION NUMBER REVISION DATE 3 2/08 Corrected typo (REF_IN should be REFCLK) in Figure 11 4 5/08 Corrected LQFP package, added Machine Model ESD, and corrected diagrams 5 8/09 Added automotive qualified part to Ordering Information DESCRIPTION PAGES CHANGED 11 1, 2, 6, 7, 10, 11, 14–18 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.