Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - deserialisers LVCMOS, LVTTL TSSOP 48

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MAX9234/MAX9236/

MAX9238

Hot-Swappable, 21-Bit, DC-Balanced LVDS

Deserializers

General Description

The MAX9234/MAX9236/MAX9238 deserialize three

LVDS serial-data inputs into 21 single-ended

LVCMOS/LVTTL outputs. A parallel-rate LVDS clock

received with the LVDS data streams provides timing for

deserialization. The outputs have a separate supply,

allowing 1.8V to 5V output logic levels. All these devices

are hot-swappable and allow “on-the-fly” frequency

programming.

The MAX9234/MAX9236/MAX9238 feature DC balance,

which allows isolation between a serializer and deseri-

alizer using AC-coupling. Each deserializer decodes

data transmitted by one of the MAX9209/MAX9211/

MAX9213/MAX9215 serializers.

The MAX9234 has a rising-edge output strobe. The

MAX9236/MAX9238 have a falling-edge output strobe.

The MAX9234/MAX9236/MAX9238 operate in DC-

balanced mode only.

The MAX9234/MAX9236 operate with a parallel input

clock of 8MHz to 34MHz, while the MAX9238 operates

from 16MHz to 66MHz. The transition time of the single-

ended outputs is increased on the low-frequency version

parts (MAX9234/MAX9236) for reduced EMI. The LVDS

inputs meet ISO 10605 ESD specification, ±25kV for Air-

Gap Discharge and ±8kV Contact Discharge.

The MAX9234/MAX9236/MAX9238 are available in 48-pin

TSSOP packages and operate over the -40°C to +85°C

temperature range.

Applications

Automotive Navigation Systems

Automotive DVD Entertainment Systems

Digital Copiers

Laser Printers

Features

o DC Balance Allows AC-Coupling for Wider Input

Common-Mode Voltage Range

o On-the-Fly Frequency Programming

o Operating Frequency Range

8MHz to 34MHz (MAX9234/MAX9236)

16MHz to 66MHz (MAX9238)

o Falling-Edge Output Strobe (MAX9236/MAX9238)

o Slower Output Transitions for Reduced EMI

(MAX9234/MAX9236)

o High-Impedance Outputs when PWRDWN Is Low

Allow Output Busing

o 5V-Tolerant PWRDWN Input

o PLL Requires No External Components

o Up to 1.386Gbps Throughput

o Separate Output Supply Pins Allow Interface to

1.8V, 2.5V, 3.3V, and 5V Logic

o LVDS Inputs Meet ISO 10605 ESD Requirements

o LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS

Standard

o Low-Profile, 48-Lead TSSOP Package

o +3.3V Main Power Supply

o -40°C to +85°C Operating Temperature Range

Ordering Information

19-3641; Rev 2; 9/12

Functional Diagram and Pin Configuration appear at end of

data sheet.

PART TEMP RANGE

PIN-

PACKAGE

MAX9234EUM+ -40°C to +85°C 48 TSSOP

MAX9234EUM/V+ -40°C to +85°C 48 TSSOP

MAX9236EUM+ -40°C to +85°C 48 TSSOP

MAX9238EUM+ -40°C to +85°C 48 TSSOP

Denotes a lead(Pb)-free/RoHS-compliant package.

/V Denotes an automotive qualified part.

Note: Devices are also available in a tape-and-reel packaging.

Specify tape and reel by adding “T” to the part number when

ordering.

Summary of content (15 pages)

PAGE 1
MAX9234/MAX9236/ MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels. All these devices are hot-swappable and allow “on-the-fly” frequency programming.
PAGE 2
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.5V to +4.0V VCCO to GND.........................................................-0.5V to +6.0V RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V PWRDWN to GND....................................................-0.5V to 6.0V RxOUT_, RxCLK OUT to GND ................-0.5V to (VCCO + 0.
PAGE 3
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input commonmode voltage VCM = ⏐VID/2⏐ to 2.4V - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.25V, TA = +25°C.
PAGE 4
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (VCC = VCCO = +3.0V to +3.6V, 100mVP-P at 200kHz supply noise, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.1V to 1.2V, input common mode voltage VCM = ⏐VID/2⏐ to 2.4V - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.25V, TA = +25°C.
PAGE 5
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Typical Operating Characteristics (VCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless otherwise noted.) MAX9234/MAX9236 WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY MAX9238 WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs.
PAGE 6
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Pin Description PIN 1, 2, 4, 5, 45, 46, 47 FUNCTION RxOUT14–RxOUT20 Channel 2 Single-Ended Outputs 3, 25, 32, 38, 44 GND Ground 6 N.C.
PAGE 7
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Table 1. Part Equivalent Table PART EQUIVALENT WITH DCB/NC = HIGH OR OPEN OPERATING FREQUENCY (MHz) MAX9234 MAX9210 8 to 34 Rising edge MAX9236 MAX9220 8 to 34 Falling edge MAX9238 MAX9222 16 to 66 Falling edge Detailed Description The MAX9234/MAX9236 operate at a parallel clock frequency of 8MHz to 34MHz. The MAX9238 operates at a parallel clock frequency of 16MHz to 66MHz.
PAGE 8
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 90% RxOUT_ OR RxCLK OUT 90% 10% RxOUT_ OR RxCLK OUT 10% 8pF CLHT CHLT Figure 3. Output Load and Transition Times IDEAL SERIAL BIT TIME 1.3V RxCLK IN VID = 0 RCCD 1.5V 1.1V RSKM RxCLK OUT RSKM IDEAL MIN IDEAL Figure 6a. MAX9234 Clock-IN to Clock-OUT Delay MAX INTERNAL STROBE + RxCLK IN Figure 4. LVDS Receiver Input Skew Margin VID = 0 RCCD RCIP 1.5V RxCLK OUT RxCLK OUT 2.0V 0.8V 0.
PAGE 9
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Applications Information PWRDWN Selection of AC-Coupling Capacitors Voltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. 0.
PAGE 10
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers MAX9209 MAX9211 MAX9213 MAX9215 HIGH-FREQUENCY, CERAMIC SURFACE-MOUNT CAPACITORS CAN ALSO BE PLACED AT THE SERIALIZER INSTEAD OF THE DESERIALIZER. TxOUT MAX9234 MAX9236 MAX9238 RxIN 7 7 (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) PLL 100Ω PLL 7 7 TxIN RxOUT 7 7 PWRDWN PWRDWN RxCLK OUT TxCLK IN TxCLK OUT RxCLK IN 21:3 SERIALIZER 3:21 DESERIALIZER Figure 10.
PAGE 11
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers In the following example, the capacitor value for a droop of 2% is calculated. Jitter due to this droop is then calculated assuming a 1ns transition time: C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1) where: C = AC-coupling capacitor (F). tB = bit time (s). DSV = digital sum variation (integer). ln = natural log. D = droop (% of signal amplitude). RT = termination resistor (Ω). RO = output resistance (Ω).
PAGE 12
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Board Layout Keep the LVTTL/LVCMOS outputs and LVDS input signals separated to prevent crosstalk. A four-layer PC board with separate layers for power, ground, LVDS inputs, and digital signals is recommended. ESD Protection The MAX9234/MAX9236/MAX9238 ESD tolerance is rated for IEC 61000-4-2 Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specifiy ESD tolerance for electronic systems.
PAGE 13
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers where: II = CTVI 0.5FC x 21 (data outputs) + CTVIfC x 1 (clock output). II = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x 34MHz). the package power-dissipation rating. Do not exceed the maximum package power-dissipation rating. See the Absolute Maximum Ratings for maximum package power-dissipation capacity and temperature derating. II = 9.5mA + 0.9mA = 10.4mA.
PAGE 14
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Pin Configuration Chip Information PROCESS: CMOS TOP VIEW RxOUT17 1 + 48 VCCO RxOUT18 2 47 RxOUT16 GND 3 46 RxOUT15 RxOUT19 4 45 RxOUT14 RxOUT20 5 44 GND N.C.
PAGE 15
MAX9234/MAX9236/MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers Revision History REVISION NUMBER REVISION DATE 0 4/05 Initial release 1 10/07 Added IEC 61000-4-2 ESD Performance; various style changes 2 9/12 Added the MAX9234EUM/V+ to Ordering Information DESCRIPTION PAGES CHANGED — 1, 2, 4, 5, 6, 12 1 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied.