Datasheet

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General Description

The MAX9235 serializer transforms 10-bit-wide parallel

LVCMOS/LVTTL data into a serial high-speed, low-volt-

age differential signaling (LVDS) data stream. The seri-

alizer typically pairs with deserializers like the

MAX9206, which receives the serial output and trans-

forms it back to 10-bit-wide parallel data.

The MAX9235 transmits serial data at speeds up to

450Mbps over PCB traces or twisted-pair cables. Since

the clock is recovered from the serial data stream,

clock-to-data and data-to-data skew that would be pre-

sent with a parallel bus are eliminated.

The MAX9235 serializer requires no external compo-

nents and no control signals and can lock to a 16MHz

to 45MHz system clock. The serializer output is held in

high impedance until the device is fully locked to the

local system clock.

The MAX9235 operates from a single +3.3V supply, is

specified for operation from -40°C to +105°C, and is

available in a 16-pin TQFN (3mm x 3mm) package.

Applications

Features

♦ Stand-Alone Serializer (vs. SERDES) Ideal for

Unidirectional Links

♦ Framing Bits for Deserializer Resync Allow Hot

Insertion Without System Interruption

♦ LVDS Serial Output Rated for Point-to-Point

Applications

♦ Wide Reference Clock Input Range

16MHz to 45MHz

♦ Low 31mA Supply Current

♦ 10-Bit Parallel LVCMOS/LVTTL Interface

♦ Up to 450Mbps Payload Data Rate

♦ Small 16-Pin TQFN (3mm x 3mm) Package

MAX9235

10-Bit LVDS Serializer

________________________________________________________________ Maxim Integrated Products 1

PCB OR

TWISTED PAIR

TCLK

PLL

INPUT LATCH

PARALLEL-TO-SERIAL

OUTPUT LATCH

SERIAL-TO-PARALLEL

TIMING AND

CONTROL

TIMING AND

CONTROL

CLOCK

RECOVERY

RCLK

LOCK

OUT+

OUT-

IN+

IN-

100Ω 100Ω

RCLK_R/F

REFCLK

OUT_

IN_

LVDS

MAX9235 MAX9206

Ordering Information

19-0849; Rev 1; 12/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PART

PIN-

PACKAGE

REF CLOCK

RANGE (MHz)

PKG

CODE

M AX 9235E TE +

16 TQFN-EP*

16 to 45

TI633-5

Pin Configuration and Functional Diagram appear at end of

data sheet.

Typical Application Circuit

Lane Departures

Security Cameras

Rear View Cameras

Production Line Monitoring

+Denotes a lead-free package.

Note: The device is specified over the -40°C to +105°C temper-

ature range.

*EP = Exposed pad.

Summary of content (12 pages)

PAGE 1
9-0849; Rev 1; 12/07 10-Bit LVDS Serializer The MAX9235 serializer transforms 10-bit-wide parallel LVCMOS/LVTTL data into a serial high-speed, low-voltage differential signaling (LVDS) data stream. The serializer typically pairs with deserializers like the MAX9206, which receives the serial output and transforms it back to 10-bit-wide parallel data. The MAX9235 transmits serial data at speeds up to 450Mbps over PCB traces or twisted-pair cables.
PAGE 2
MAX9235 10-Bit LVDS Serializer ABSOLUTE MAXIMUM RATINGS Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Operating Temperature Range .........................-40°C to +105°C Lead Temperature (soldering, 10s) .................................+300°C ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV ESD Protection (Human Body Model, IN_, TCLK) ...............±2kV VCC to GND ....................
PAGE 3
10-Bit LVDS Serializer (VCC = +3.0V to +3.6V, RL = 50Ω ±1%, CL = 5pF, TA = -40°C to +105°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS TCLK Center Frequency fTCCF 16 45 MHz TCLK Frequency Variation TCFV -200 +200 ppm ns TCLK Period tTCP 22.2 62.
PAGE 4
MAX9235 10-Bit LVDS Serializer RL 2 OUT+ TCLK VOD VOS ODD IN_ RL 2 OUT- EVEN IN_ Figure 1. Output Voltage Definitions Figure 2. Worst-Case ICC Test Pattern 3V 90% 90% TCLK 10% 10% tCLKT 0 tCLKT Figure 3. Input Clock Transition Time Requirement 5pF OUT+ 80% 80% VDIFF = 0 RL 20% VDIFF 20% OUT5pF tLHT tHLT VDIFF = (OUT+) - (OUT-) Figure 4. Output Load and Transition Times tTCP 1.5V TCLK tS IN_ 1.5V 1.5V 1.5V tH 1.5V Figure 5.
PAGE 5
10-Bit LVDS Serializer 2.5V MAX9235 VCC 2.5V tPL TCLK OUT± ACTIVE HIGH IMPEDANCE HIGH IMPEDANCE Figure 6. PLL Lock Time IN IN0–IN9 SYMBOL N + 1 IN0–IN9 SYMBOL N tSD TCLK 1.5V START BIT OUT0–OUT9 SYMBOL N STOP BIT START BIT OUT0–OUT9 SYMBOL N + 1 STOP BIT OUT± VDIFF = 0 VDIFF = (OUT+) - (OUT-) Figure 7.
PAGE 6
Typical Operating Characteristics (VCC = +3.3V, RL = 50Ω, CL = 5pF, TA = +25°C, unless otherwise noted.) WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9205 toc01 34 33 SUPPLY CURRENT (mA) MAX9235 10-Bit LVDS Serializer 32 31 30 29 TCLK = 40MHz 28 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) Pin Description PIN NAME 1–7, 14, 15, 16 IN3–IN9, IN0, IN1, IN2 8 TCLK LVCMOS/LVTTL Reference Clock Input. Accepts a 16MHz to 45MHz clock.
PAGE 7
10-Bit LVDS Serializer The MAX9235 10-bit serializer transmits data over balanced media that may be a standard twisted-pair cable or PCB traces at 100Mbps to 450Mbps. The interface may be single- or double-terminated point-to-point. A double-terminated point-to-point interface uses a 100Ωtermination resistor at each end of the interface, resulting in a 50Ω load. The serializer requires a deserializer such as the MAX9206 for a complete data transmission application.
PAGE 8
MAX9235 10-Bit LVDS Serializer Topologies used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. The MAX9235 can operate in point-to-point or broadcast topologies. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections. Since repeater jitter subtracts from the serializer-deserializer timing margin, a low-jitter repeater is essential in most high data rate applications.
PAGE 9
10-Bit LVDS Serializer 10 OUT+ GND OUT+ OUT- GND PARALLEL-TO-SERIAL IN_ INPUT LATCH TOP VIEW 12 11 10 9 VCC 13 8 TCLK 7 IN9 6 IN8 5 IN7 OUTIN0 14 MAX9235 IN1 15 TCLK IN3 1 MAX9235 2 3 4 IN6 + IN5 TIMING AND CONTROL IN4 IN2 16 PLL THIN QFN 3mm x 3mm Chip Information PROCESS: CMOS _______________________________________________________________________________________ 9 MAX9235 Pin Configuration Functional Diagram
PAGE 10
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) (NE - 1) X e E MARKING 12x16L QFN THIN.EPS MAX9235 10-Bit LVDS Serializer E/2 D2/2 (ND - 1) X e D/2 AAAA e CL D D2 k CL b 0.10 M C A B E2/2 L E2 0.10 C C L C L 0.08 C A A2 A1 L L e e PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.
PAGE 11
10-Bit LVDS Serializer PKG 8L 3x3 12L 3x3 16L 3x3 REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 b 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 D 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 E 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 0.75 0.45 0.65 0.30 e L 0.65 BSC. 0.35 0.55 0.50 BSC. 0.50 BSC. 0.55 0.40 N 8 12 16 ND 2 3 4 NE 2 3 4 0 A1 A2 k 0.02 0.05 0 0.25 - 0.02 0.
PAGE 12
MAX9235 10-Bit LVDS Serializer Revision History REVISION NUMBER REVISION DATE 0 7/07 Initial release 1 12/07 Max clock frequency increased to 45MHz; min value decreased for TCLK period; changed conditions for Output Short-Circuit and Power-Off Output Current; various style edits. REVISION DESCRIPTION PAGES CHANGED — 1, 2, 3, 6, 7 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.