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Gigabit Multimedia Serial Link with Spread

Spectrum and Full-Duplex Control Channel

MAX9259/MAX9260

EVALUATION KIT AVAILABLE

19-4968; Rev 4; 10/14

Typical Applications Circuit appears at end of data sheet.

General Description

The MAX9259 serializer pairs with the MAX9260 deseri-

alizer for joint transmission of high-speed video, audio,

and control data.

The MAX9259/MAX9260 operate up to 3.125Gbps for a

15m shielded twisted-pair (STP) cable. This serial link

supports display panels from QVGA (320 x 240) up to

XGA (1280 x 768), or dual-view WVGA (2 x 854 x 480).

The embedded audio channel supports I

S up to 32 bits

per sample and at a 192kHz sample rate. The embed-

ded control channel forms a full-duplex, differential

100kbps to 1Mbps UART link between the serializer and

deserializer. The host electronic control unit (ECU) or

microcontroller (FC) resides either on the MAX9259 or on

the MAX9260. In addition, the control channel enables

ECU/FC control of peripherals in the remote side of the

serial link through I

C/UART.

Preemphasis and channel equalization extend the link

length and enhance the link reliability. Spread spectrum

is available to reduce EMI on the serial and parallel out-

put data signals. The differential link complies with the

ISO 10605 and IEC 61000-4-2 ESD-protection standards.

The core supplies for the MAX9259/MAX9260 are 1.8V

and 3.3V, respectively. Both devices use an I/O sup-

ply from 1.8V to 3.3V. These devices are available in

a 64-pin TQFP package (10mm x 10mm) and a 56-pin

TQFN/QFND package (8mm x 8mm x 0.75mm) with an

exposed pad. Electrical performance is guaranteed over

the -40NC to +105NC automotive temperature range.

Applications

High-Resolution Automotive Navigation

Rear-Seat Infotainment

Megapixel Camera Systems

Features

S Ideal for Digital Video Applications

Up to XGA (1280 x 768) or Dual-View WVGA

(2 x 854 x 480) Panels with 18- or 24-Bit Color

Pre/Deemphasis Allows 15m Cable at Full Speed

Up to 192kHz, 32-Bit Sample I

S Multiple Data Rates for System Flexibility

Up to 3.12Gbps Serial-Bit Rate

6.25MHz to 104MHz Pixel Clock

Up to 1Mbps UART/UART-to-I

C Control Channel

S Reduces EMI and Shielding Requirements

Serial Output Programmable for 100mV to 400mV

Programmable Spread Spectrum Reduces EMI

Bypasses Input PLL for Jitter Attenuation

S Peripheral Features for System Verification

Built-In Serial Link PRBS BER Tester

Interrupt Transmission from Deserializer to

Serializer

Meets AEC-Q100 Requirements

-40NC to +105NC Operating Temperature Range

±10kV Contact and 25kV Air ISO 10605 and

±10kV IEC 61000-4-2 ESD Protection

Ordering Information

/V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

T = Tape and reel.

Simplified Diagram

µC MAX9259 MAX9260

VIDEO/AUDIO

720

DISPLAY

VIDEO/AUDIO

PART TEMP RANGE PIN-PACKAGE

MAX9259GCB/V+

-40NC to +105NC

64 TQFP-EP*

MAX9259GCB/V+T

-40NC to +105NC

64 TQFP-EP*

MAX9259GTN/V+T

-40NC to +105NC

56 TQFN-EP*

MAX9259GGN/VY+

-40NC to +105NC

56 QFND-EP*

MAX9260GCB/V+

-40NC to +105NC

64 TQFP-EP*

MAX9260GCB/V+T

-40NC to +105NC

64 TQFP-EP*

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

Summary of content (51 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel General Description The MAX9259 serializer pairs with the MAX9260 deserializer for joint transmission of high-speed video, audio, and control data. The MAX9259/MAX9260 operate up to 3.125Gbps for a 15m shielded twisted-pair (STP) cable. This serial link supports display panels from QVGA (320 x 240) up to XGA (1280 x 768), or dual-view WVGA (2 x 854 x 480).
PAGE 2
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel ABSOLUTE MAXIMUM RATINGS AVDD to AGND MAX9259............................................................-0.5V to +1.9V MAX9260............................................................-0.5V to +3.9V DVDD to GND (MAX9259)....................................-0.5V to +1.9V DVDD to DGND (MAX9260)..................................-0.5V to +3.9V IOVDD to GND (MAX9259)...................................-0.
PAGE 3
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.
PAGE 4
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.) ESD PROTECTION OUT+, OUT- (Pin to EP) All Other Pins (to EP or Supply) 4 VESD VESD Human Body Model, RD = 1.
PAGE 5
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 AC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.
PAGE 6
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.
PAGE 7
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.
PAGE 8
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) ESD PROTECTION Human Body Model, RD = 1.
PAGE 9
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 AC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PARALLEL CLOCK OUTPUT (PCLKOUT) Clock Frequency Clock Duty Cycle fPCLKOUT DC VBWS = VIOGND, VDRS = VIOVDD 8.
PAGE 10
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 AC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I2S OUTPUT TIMING fWS = 48kHz or 44.
PAGE 11
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Typical Operating Characteristics (continued) (VDVDD = VAVDD = VIOVDD = 1.8V (MAX9259), VDVDD = VAVDD = VIOVDD = 3.3V (MAX9260), TA = +25NC, unless otherwise noted.) 140 135 130 125 120 170 115 160 2%, 4% SPREAD 150 140 130 120 110 110 MAX9260 SUPPLY CURRENT vs.
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MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel DOUT23 DOUT22 DOUT21 DOUT19 DOUT20 DOUT18 DOUT17 DOUT16 DOUT15 DOUT14 DOUT13 DOUT12 DOUT11 DOUT9 CDS PWDN RX/SDA SSEN TX/SCL LMN1 AGND OUT- OUT+ AVDD LMN0 LFLT INT DRS BWS ES DOUT10 TOP VIEW TOP VIEW PCLKOUT Pin Configurations 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DIN0 49 32 MS DOUT8 49 32 DOUT24 GND 50 31 GND
PAGE 13
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 Pin Description PIN NAME FUNCTION TQFP TQFN/QFND 1–5, 11–17, 21–25, 49, 52–60, 63, 64 1–5, 9–15, 17–21, 43, 45–53, 55, 56 DIN0– DIN28 Data Input[0:28]. Parallel data inputs. All pins internally pulled down to GND. Selected edge of PCLKIN latches input data. Set BWS = low (24-bit mode) to use DIN0–DIN20 (RGB and SYNC). DIN21–DIN28 are not used in 24-bit mode.
PAGE 14
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 Pin Description (continued) PIN TQFP TQFN/QFND 36 31 NAME FUNCTION TX/SCL Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I2C mode, TX/SCL is the SCL output of the MAX9259’s I2C master. 37 32 SSEN Spread-Spectrum Enable.
PAGE 15
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 Pin Description PIN NAME FUNCTION 1 ENABLE Enable. Active-low parallel output-enable input requires external pulldown or pullup resistors. Set ENABLE = low to enable PCLKOUT, SD, SCK, WS, and the parallel outputs, DOUT_. Set ENABLE = high to put PCLKOUT, SD, SCK, WS, and DOUT_ to high impedance. 2 BWS Bus-Width Select.
PAGE 16
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 Pin Description (continued) PIN NAME FUNCTION 18 TX/SCL Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I2C mode, TX/SCL is the SCL output of the MAX9260’s I2C master. 19 PWDN Power-Down. Active-low power-down input requires external pulldown or pullup resistors. Error.
PAGE 17
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Functional Diagram LFLT PCLKIN FILTER PLL SPREAD PLL LINEFAULT DET CLKDIV DIN[N:0] 8B/10B ENCODE PARITY FIFO P S LMN0 LMN1 CML Tx OUT+ WS, SD, SCK AUDIO FIFO PRBS GEN TX/SCL RX/SDA TERM MAX9259 OUT- REV CH Rx UART/I2C SERIALIZER SPREAD PLL CDR PLL PCLKOUT STP CABLE (Z0 = 50) EQ CLKDIV DOUT[N:0] 8B/10B DECODE PARITY FIFO P S CML Rx IN- WS, SD, SCK TX/SCL RX/SDA AUDIO FIFO P
PAGE 18
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel RL/2 OUT+ VOD VOS OUT- RL/2 GND ((OUT+) + (OUT-))/2 OUTVOS(+) VOS(-) VOS(-) OUT+ DVOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) VOD(-) DVOD = |VOD(+) - VOD(-)| (OUT+) - (OUT-) Figure 1. MAX9259 Serial Output Parameters OUT+ VOD(P) VOS VOD(D) OUT- SERIAL-BIT TIME Figure 2.
PAGE 19
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel 1.7V TO 1.9V MAX9259 45.3kI* 45.3kI* LMN0 LMN1 OUTPUT LOGIC (OUT+) 4.99kI* OUT+ 4.99kI* TWISTED PAIR OUT49.9kI* LFLT 1.5V 0.5V 49.9kI* CONNECTORS 2.1V REFERENCE VOLTAGE GENERATOR OUTPUT LOGIC (OUT-) *Q1% TOLERANCE Figure 3. Fault-Detector Circuit PCLKIN DIN_ NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE. Figure 4.
PAGE 20
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel tT VIH MIN tHIGH PCLKIN VIL MAX tR tF tLOW Figure 5. MAX9259 Parallel Input Clock Requirements START CONDITION (S) PROTOCOL BIT 7 MSB (A7) tLOW tSU;STA BIT 6 (A6) tHIGH BIT 0 (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1/fSCL VIOVDD x 0.7 SCL VIOVDD x 0.3 tBUF tr tSP tf VIOVDD x 0.7 SDA VIOVDD x 0.3 tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO Figure 6.
PAGE 21
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel VIH MIN PCLKIN VIL MAX tSET tHOLD VIH MIN VIH MIN VIL MAX VIL MAX DIN_ NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE. Figure 8. MAX9259 Input Setup-and-Hold Times EXPANDED TIME SCALE DIN_ N N+1 N+3 N+2 N+4 PCLKIN N-1 N OUT+/tSD FIRST BIT LAST BIT Figure 9.
PAGE 22
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel PCLKIN tLOCK 350Fs SERIAL LINK INACTIVE SERIAL LINK ACTIVE REVERSE CONTROL CHANNEL ENABLED REVERSE CONTROL CHANNEL AVAILABLE CHANNEL DISABLED PWDN MUST BE HIGH Figure 10.
PAGE 23
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel RL/2 IN+ MAX9260 VOD REVERSE CONTROL-CHANNEL TRANSMITTER IN- VCMR RL/2 IN+ IN- IN- IN+ VCMR VROH 0.9 x VROH 0.1 x VROH (IN+) - (IN-) 0.1 x VROL tR 0.9 x VROL VROL tF Figure 13. MAX9260 Reverse Control-Channel Output Parameters RL/2 IN+ VIN+ PCLKOUT VID(P) RL/2 IN- _ + _ VIN- + _ CIN CIN DOUT_ NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
PAGE 24
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel tT VOH MIN tHIGH PCLKOUT VOL MAX tLOW Figure 16. MAX9260 Clock Output High-and-Low Times CL MAX9260 SINGLE-ENDED OUTPUT LOAD 0.8 x VI0VCC 0.2 x VI0VCC tR tF Figure 17.
PAGE 25
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel IN+ - IN- tLOCK LOCK VOH PWDN MUST BE HIGH Figure 19. MAX9260 Lock Time IN+/- VIH1 PWDN tPU LOCK VOH Figure 20. MAX9260 Power-Up Delay WS tDVA tR tDVB SCK tDVB tDVA tF SD Figure 21.
PAGE 26
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Detailed Description The MAX9259/MAX9260 chipset presents Maxim’s GMSL technology. The MAX9259 serializer pairs with the MAX9260 deserializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data for video-display or image-sensing applications. The serial-payload data rate can reach up to 2.5Gbps for a 15m STP cable.
PAGE 27
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Parallel Inputs and Outputs The parallel bus uses two selectable bus widths, 24 bits and 32 bits. BWS selects the bus width according to Table 1. In 24-bit mode, DIN21–DIN28 are not used and are internally pulled down. For both modes, SD, SCK, and WS pins are dedicated for I2S audio data.
PAGE 28
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 2. Maximum Audio Sampling Rates for Various PCLK_ Frequencies PCLK_ FREQUENCY (DRS = LOW) (MHz) WORD LENGTH (Bits) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.
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MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 3. MAX9260 fSRC Settings MCLKSRC SETTING (REGISTER 0x12, D7) DATA-RATE SETTING High speed 0 Low speed 1 — BIT-WIDTH SETTING MCLK SOURCE FREQUENCY (fSRC) 24-bit mode 3 x fPCLKOUT 32-bit mode 4 x fPCLKOUT 24-bit mode 6 x fPCLKOUT 8 x fPCLKOUT 32-bit mode — Internal oscillator (120MHz typ) Choose MCLKDIV values so that fMCLK is not greater than 60MHz.
PAGE 30
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel WRITE DATA FORMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N ACK MASTER WRITES TO SLAVE MASTER READS FROM SLAVE READ DATA FRMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES MASTER WRITES TO SLAVE ACK BYTE 1 BYTE N MASTER READS FROM SLAVE Figure 24.
PAGE 31
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0) MAX9259/MAX9260 FC 11 SYNC FRAME 11 DEVICE ID + WR MAX9259/MAX9260 11 REGISTER ADDRESS 11 NUMBER OF BYTES 11 DATA 0 11 DATA N 11 ACK FRAME PERIPHERAL 1 S 7 DEV ID 1 1 W A 8 REG ADDR 8 DATA 0 1 A 1 A 8 DATA N 1 1 A P UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0) MAX9259/MAX9260 FC 11 SYNC FRAME 11 DEVICE ID + RD MAX9259/MAX92
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MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 4. MAX9259 CML Driver Strength (Default Level, CMLLVL = 11) PREEMPHASIS LEVEL (dB)* PREEMPHASIS SETTING (0x05, D[3:0]) ICML (mA) IPRE (mA) -6.0 0100 12 -4.1 0011 -2.5 0010 -1.2 SINGLE-ENDED VOLTAGE SWING MAX (mV) MIN (mV) 4 400 200 13 3 400 250 14 2 400 300 0001 15 1 400 350 0 0000 16 0 400 400 1.1 1000 16 1 425 375 2.2 1001 16 2 450 350 3.
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MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 5. MAX9260 Cable Equalizer Boost Levels BOOST SETTING (0x05 D[3:0]) TYPICAL BOOST GAIN (dB) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 Power-up default (EQS = high) 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 Power-up default (EQS = low) 1010 11.
PAGE 34
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 8. MAX9260 Parallel Output Spread SS SPREAD (%) 00 No spread spectrum. Power-up default when SSEN = low. 01 Q2% spread spectrum. Power-up default when SSEN = high. 10 No spread spectrum 11 Q4% spread spectrum Table 9.
PAGE 35
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel To program the SDIV setting, first look up the modulation coefficient according to the part number and desired bit-width and spread-spectrum settings. Solve the above equation for SDIV using the desired parallel clock and modulation frequencies. If the calculated SDIV value is larger than the maximum allowed SDIV value in Tables 9 or 10, set SDIV to the maximum value.
PAGE 36
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 11. Startup Selection for Video-Display Applications (CDS = Low) CASE AUTOS (MAX9259) MAX9259 POWER-UP STATE MS (MAX9260) MAX9260 POWER-UP STATE LINK STARTUP MODE 1 Low Serialization enabled Low Normal (SLEEP = 0) Both devices power up with serial link active (autostart) Sleep mode (SLEEP = 1) Serial link is disabled and the MAX9260 powers up in sleep mode.
PAGE 37
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel SLEEP = 1, VIDEO LINK OR CONFIG LINK NOT LOCKED AFTER 8ms MS PIN SETTING SLEEP BIT POWER-UP VALUE LOW HIGH 0 1 SLEEP WAKE-UP SIGNAL POWER-ON IDLE SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER FC SETS SLEEP = 1 SEND INT TO INT CHANGES FROM LOW TO HIGH OR HIGH TO LOW MAX9259 SIGNAL DETECTED PWDN = HIGH, POWER-ON CONFIG LINK UNLOCKED SERIAL PORT LOCKING CONFIG LINK OPERATING PROGRAM REGISTERS
PAGE 38
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel AUTOS PIN SETTING LOW HIGH POWER-UP VALUE SEREN SLEEP 1 0 0 1 SLEEP CLINKEN = 0 OR SEREN = 1 CLINKEN = 0 OR SEREN = 1 SLEEP = 1 FOR > 8ms SLEEP = 0, WAKE-UP REVERSE LINK POWER-ON IDLE SEREN = 0 CONFIG LINK STARTED CLINKEN = 1 WAKE-UP SIGNAL PWDN = HIGH, POWER-ON, AUTOS = HIGH SLEEP = 1 ALL STATES PWDN = LOW OR POWER-OFF POWER-DOWN OR POWER-OFF SLEEP = 0, SLEEP = 1 SEREN = 1, PCLKIN RUNNING
PAGE 39
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Applications Information MAX9260 Error Checking The MAX9260 checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register (DECERR, 0x0D). If a large number of decoding errors are detected within a short duration, the deserializer loses lock and stops the error counter. The deserializer then attempts to relock to the serial data.
PAGE 40
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 13.
PAGE 41
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel are not recognized if the transition time becomes too slow. The MAX9259/MAX9260 support I2C/UART rates up to 1Mbps. AC-Coupling AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor.
PAGE 42
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel 1MI HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 100pF ATE. Keep PCB traces that make up a differential pair equal in length to avoid skew within the differential pair. RD 1.5kI ESD Protection DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 34.
PAGE 43
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16. MAX9259 Register Table REGISTER ADDRESS 0x00 0x01 BITS NAME VALUE D[7:1] SERID XXXXXXX D0 — 0 D[7:1] DESID XXXXXXX D0 — 0 D[7:5] SS 0x02 D4 D[3:2] D[1:0] D[7:6] AUDIOEN PRNG SRNG Maxim Integrated Reserved Deserializer device address Reserved 000 001 Q0.5% spread spectrum. Power-up default when SSEN = high. 010 Q1.
PAGE 44
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16. MAX9259 Register Table (continued) REGISTER ADDRESS BITS D7 NAME CLINKEN D5 PRBSEN 0x04 D[3:2] FUNCTION 0 Disable serial link. Power-up default when AUTOS = high. Reverse-channel communication remains unavailable for 350Fs after the MAX9259 starts/stops the serial link. 1 Enable serial link. Power-up default when AUTOS = low.
PAGE 45
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16.
PAGE 46
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16.
PAGE 47
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 17.
PAGE 48
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 17. MAX9260 Register Table (continued) REGISTER ADDRESS BITS D7 D[6:5] D4 NAME I2CMETHOD HPFTUNE PDHF 0x05 D[3:0] D7 D6 0x06 48 EQTUNE DISSTAG VALUE 0 I2C conversion sends the register address 1 Disable sending of I2C register address (command-byte-only mode) 00 7.5MHz Equalizer highpass cutoff frequency 01 3.75MHz cutoff frequency 10 2.5MHz cutoff frequency 11 1.
PAGE 49
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 17. MAX9260 Register Table (continued) REGISTER ADDRESS BITS NAME VALUE 0x07 D[7:0] — 01010100 Reserved 01010100 0x08 D[7:0] — 00110000 Reserved 00110000 0x09 D[7:0] — 11001000 Reserved 11001000 0x0A D[7:0] — 00010010 Reserved 00010010 0x0B D[7:0] — 00100000 Reserved 00100000 0x0C D[7:0] ERRTHR XXXXXXXX Error threshold for decoding errors.
PAGE 50
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Chip Information PROCESS: CMOS 50 Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO.
PAGE 51
MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Revision History REVISION NUMBER REVISION DATE 0 9/09 Initial release 1 7/10 Added clarification of fault thresholds and updated Pin Description table 2 11/10 Added TQFN package to Ordering Information, Absolute Maximum Ratings, Pin Configurations, Pin Description, and Package Information 3 1/11 Added Patent Pending to Features 4 10/14 Updated General Description and Features sections and Figu