Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX9325EQI+

General Description

The MAX9325 low-skew, 2:8 differential driver features

extremely low output-to-output skew (50ps max) and

part-to-part skew (225ps max). These features make

the device ideal for clock and data distribution across a

backplane or board. The device selects one of the two

differential HSTL or LVECL/LVPECL inputs and repeats

them at eight differential outputs. Outputs are compati-

ble with LVECL and LVPECL, and can directly drive

50Ω terminated transmission lines.

The differential inputs can be configured to accept a

single-ended signal when the unused complementary

input is connected to the on-chip reference output volt-

age V

BB.

All inputs have internal pulldown resistors to

EE.

The internal pulldowns and a fail-safe circuit

ensure differential low default outputs when the inputs

are left open or at V

The MAX9325 operates over a 2.375V to 3.8V supply

range for interfacing to differential HSTL and LVPECL

signals. This allows high-performance clock or data dis-

tribution in systems with a nominal +2.5V or +3.3V sup-

ply. For LVECL operation, the device operates with a

-2.375V to -3.8V supply.

The MAX9325 is offered in 28-lead PLCC and space-

saving 28-lead QFN packages. The MAX9325 is speci-

fied for operation from -40°C to +85°C.

Applications

Precision Clock Distribution

Low-Jitter Data Repeaters

Features

♦ 50ps (max) Output-to-Output Skew

♦ 1.5ps

RMS

(max) Random Jitter

♦ Guaranteed 300mV Differential Output at 700MHz

♦ +2.375V to +3.8V Supplies for Differential

HSTL/LVPECL

♦ -2.375V to -3.8V Supplies for Differential LVECL

♦ Two Selectable Differential Inputs

♦ On-Chip Reference for Single-Ended Inputs

♦ Outputs Low for Inputs Open or at V

♦ Pin Compatible with MC100LVE310

MAX9325

2:8 Differential LVPECL/LVECL/HSTL Clock and

Data Driver

________________________________________________________________ Maxim Integrated Products 1

N.C.

*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V

CLK1

CLKO

CLK_SEL

MAX9325

QFN

N.C.

CLK1

CLKO

CLK_SEL

CLKO

CLK1

PLCC

TOP VIEW

567891011

232425 192021

MAX9325

CLK_SEL INPUT CLOCK

INPUT SELECT TRUTH TABLE

CLK0, CLK0 SELECTED

CLK1, CLK1 SELECTED

Pin Configurations

Ordering Information

19-2511; Rev 3; 11/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Functional Diagram appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX9325EQI -40°C to +85°C 28 PLCC

MAX9325EGI -40°C to +85°C

28 QFN 5mm x 5mm

Summary of content (12 pages)

PAGE 1
9-2511; Rev 3; 11/04 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPECL inputs and repeats them at eight differential outputs.
PAGE 2
MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS VCC - VEE ...............................................................-0.3V to +4.1V Inputs (CLK_, CLK_, CLK_SEL) to VEE ......-0.3V to (VCC + 0.3V) CLK_ to CLK_ .....................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................
PAGE 3
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver ((VCC - VEE) = 2.375V to 3.8V, RL = 50Ω ±1% to VCC - 2V. Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Notes 1–4) PARAMETER SYMBOL Differential Input Low Voltage VILD Differential Input Voltage VIHD VILD Input Current IIN CONDITIONS -40°C TYP +25°C MAX MIN VEE VCC - 0.095 (VCC - VEE) < 3.0V, Figure 1 0.095 (VCC - VEE) ≥ 3.
PAGE 4
MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS—PLCC Package ((VCC - VEE) = 2.375V to 3.8V, RL = 50Ω ±1% to VCC - 2V, fIN ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).
PAGE 5
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver ((VCC - VEE) = 2.375V to 3.8V, RL = 50Ω ±1% to VCC - 2V, fIN ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).
PAGE 6
Typical Operating Characteristics (PLCC package, typical values are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V), RL = 50Ω ±1% to VCC - 2V, fIN = 500MHz, input transition time = 125ps (20% to 80%).) OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY SUPPLY CURRENT (IEE) vs. TEMPERATURE 40 35 30 600 500 400 25 300 20 -40 -15 10 35 60 0 85 500 1000 1500 TEMPERATURE (°C) FREQUENCY (MHz) TRANSITION TIME vs. TEMPERATURE PROPAGATION DELAY vs.
PAGE 7
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver PIN NAME FUNCTION PLCC QFN 1, 8, 15, 22 4, 11, 18, 25 VCC 2 5 CLK0 3 6 VBB 4 7 CLK1 Noninverting Differential Clock Input 1. Internal 105kΩ pulldown to VEE. 5 8 CLK1 Inverting Differential Clock Input 1. Internal 105kΩ pulldown to VEE. 6 9 N.C. Not Connected 7 10 Q7 Inverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V. 9 12 Q7 Noninverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V.
PAGE 8
MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver VCC VIHD (MAX) VCC VIHD - VILD VIH VILD (MAX) VBB VIL VIHD (MIN) VIHD - VILD VILD (MIN) VEE VEE DIFFERENTIAL INPUT VOLTAGE DEFINITION SINGLE-ENDED INPUT VOLTAGE DEFINITION Figure 1. Input Voltage Definitions CLK VIHD VIHD - VILD VILD CLK tPHLD tPLHD Q_ VOH VOH - VOL Q_ VOL 80% 80% VOH - VOL 0V (DIFFERENTIAL) VOH - VOL DIFFERENTIAL OUTPUT WAVEFORM 20% 20% Q_ - Q_ tR tF Figure 2.
PAGE 9
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver MAX9325 CLK_ WHEN CLK_ = VBB VIH VBB VBB VIL OR VIH VBB VBB CLK_ WHEN CLK_ = VBB VIL tPLH tPHL VOH Q_ VOH - VOL VOL Q_ Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram Detailed Description The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max).
PAGE 10
MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver ferential input is configured for single-ended operation by connecting the on-chip reference voltage, VBB, to an unused complementary input as a reference. For example, the differential CLK0, CLK0 input is converted to a noninverting, single-ended input by connecting VBB to CLK0 and connecting the single-ended input to CLK0. Similarly, an inverting input is obtained by connecting VBB to CLK0 and connecting the single-ended input to CLK0.
PAGE 11
2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver PLCC.EPS e A A1 A2 A3 B B1 C e D D1 D3 N INCHES MIN MAX 0.165 0.180 0.090 0.120 0.145 0.156 0.020 --0.013 0.021 0.026 0.032 0.009 0.011 0.050 D3 D1 D A A2 A1 B1 B A3 C D2 MIN MAX 4.20 4.57 2.29 3.04 3.69 3.96 0.51 --0.33 0.53 0.66 0.81 0.23 0.28 1.27 D D1 D2 D3 INCHES MIN MAX 0.385 0.395 0.350 0.356 0.290 0.330 0.200 REF MIN 9.78 8.89 7.37 5.08 MAX N 10.03 20 AA 9.04 8.38 REF D 0.485 D1 0.450 D2 0.390 D3 0.300 0.495 0.456 0.
PAGE 12
Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L QFN.EPS MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.