Datasheet

SHUNT
POSITION
V
SET
FULL-SCALE
CURRENT
LIMIT (A)
CURRENT-
LIMIT STEP
SIZE (mA)
1-2 V
DAC
2.56 10
2-3 V
DAC
/10 0.256 1
_________________________________________________________________ Maxim Integrated Products 4
MAX9611PMB1 Peripheral Module
Current Limit
The point at which current limiting begins is determined
by the voltage at pin 4 on the MAX9611 (V
SET
). This volt-
age is set by the output of the DAC (MAX5380) and the
setting of the shunt on JP1, which selects either V
DAC
or
V
DAC
/10. The nominal 2.00V output of the DAC is divided
to 1.26V full scale by the divider formed by R3 and R8
+ R9. The lower tap of that divider (R3 + R8 and R9)
provides 0.126V full scale. The position of the shunt on
JP1 determines which of the two voltages is connected
to V
SET
on the MAX9611. With the shunt connected
between JP1-1 and JP1-2, the higher voltage (V
DAC
) is
connected to V
SET
. This setting allows full-scale current
limit at 2.56A with 10mA steps (Caution: Although soft-
ware settings do not prohibit it, the circuit should not be
operated above 1A output current as overheating and
unreliable operation could result). When the shunt is con-
nected between JP1-2 and JP1-3, the full-scale current is
256mA with 1mA steps.
Important: The total power dissipation for the pass FET
(Q1) should not exceed 1.5W. This can easily be exceed-
ed with even moderate output current if the load voltage
is high and the load resistance is low.
The JP1 connector determines the current-limit range
and step size. Note: Do not operate the board without a
shunt in place, in one of these two positions. See Table 5.
Software and FPGA Code
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module function-
ality and uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions
within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download at
www.maxim-ic.com. Quick start instructions are also
available as a separate document.
Table 5. Jumper JP1 (Current-Limit Range)