Datasheet

MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
26Maxim Integrated
Standby Mode
If BCLK stops toggling, the ICs automatically enter
standby mode. In standby mode, the Class D speaker
is turned off and the outputs go into a high-impedance
state, ensuring that unwanted current is not transferred to
the load during this condition. Standby mode should not
be used in place of the shutdown mode, as the shutdown
mode provides the lowest power consumption and the
best power-on/off click-and-pop performance.
DAC Digital Filters
The DAC features a digital lowpass filter that is automati-
cally configured for voice playback or music playback
based on the sample rate that is used. This filter elimi-
nates the effect of aliasing and any other high-frequency
noise that might otherwise be present. Table 4 shows the
digital filter settings that are automatically selected.
SD_MODE and Shutdown Operation
The ICs feature a low-power shutdown mode, drawing
less than 0.6FA (typ) of supply current. During shutdown,
all internal blocks are turned off, including setting the
output stage to a high-impedance state. Drive SD_MODE
low to put the ICs into shutdown.
The state of SD_MODE determines the audio channel
that is sent to the amplifier output (Table 5).
Drive SD_MODE high to select the left word of the stereo
input data. Drive SD_MODE high through a sufficiently
small resistor to select the right word of the stereo input
data. Drive SD_MODE high through a sufficiently large
resistor to select both the left and right words of the
stereo input data ((left + right)/2). R
LARGE
and R
SMALL
are determined by the V
DDIO
voltage (logic voltage from
control interface) that is driving SD_MODE according to
the following two equations:
R
SMALL
(kI) = 98.5 x V
DDIO
- 100
R
LARGE
(kI) = 222.2 x V
DDIO
- 100
Table 4. Digital Filter Settings
Table 5. SD_MODE Control
Table 6. Examples of SD_MODE Pullup Resistor Values
LRCLK FREQUENCY
-3dB CUTOFF
FREQUENCY
RIPPLE LIMIT CUTOFF
FREQUENCY
STOPBAND CUTOFF
FREQUENCY
STOPBAND
ATTENUATION (dB)
f
LRCLK
< 30kHz 0.446 x f
LRCLK
0.443 x f
LRCLK
0.464 x f
LRCLK
75
30kHz < f
LRCLK
< 50kHz 0.47 x f
LRCLK
0.43 x f
LRCLK
0.58 x f
LRCLK
60
f
LRCLK
> 50kHz 0.31 x f
LRCLK
0.24 x f
LRCLK
0.477 x f
LRCLK
60
LOGIC VOLTAGE LEVEL (V
DDIO
) (V)
R
SMALL
(kI, 1% TOLERANCE) R
LARGE
(kI, 1% TOLERANCE)
1.8 76.8 300
3.3 226 634
SD_MODE STATUS
SELECTED CHANNEL
High
V
SD_MODE
> B2 trip point (1.4V typ)
Left
Pullup through R
SMALL
B2 trip point (1.4V typ) > V
SD_MODE
>
B1 trip point (0.77V typ)
Right
Pullup through R
LARGE
B1 trip point (0.77 typ) > V
SD_MODE
>
B0 trip point (0.16V typ)
Left/2 + Right/2
Low
B0 trip point (0.16V typ) > V
SD_MODE
Shutdown