Datasheet

MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
27Maxim Integrated
When the devices are configured in left-channel mode
(SD_MODE is directly driven to logic-high by the con-
trol interface), take care to avoid violating the Absolute
Maximum Ratings limits for SD_MODE. Ensuring that
V
DD
is always greater than V
DDIO
is one way to prevent
SD_MODE from violating the Absolute Maximum Ratings
limits. If this is not possible in the application (e.g., if V
DD
< 3.0V and V
DDIO
= 3.3V, then it is necessary to add a
small resistance (~2kI) in series with SD_MODE to limit
the current into the SD_MODE pin. This is not a concern
when using the right channel or (left + right)/2 modes.
Figure 12 and Figure 13 show how to connect an external
resistor to SD_MODE when using an open-drain driver or
a pullup/down driver.
Class D Speaker Amplifier
The filterless Class D amplifier offers much higher efficiency
than Class AB amplifiers. The high efficiency of a Class
D amplifier is due to the switching operation of the output
stage transistors. Any power loss associated with the
Class D output stage is mostly due to the I
2
R loss of the
MOSFET on-resistance and quiescent current overhead.
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet EN55022B electromag-
netic-interference (EMI) regulation standards. Maxim’s
active emissions-limiting edge-rate control circuitry and
spread-spectrum modulation reduces EMI emissions
while maintaining up to 92% efficiency.
Figure 13. SD_MODE Resistor Connection Using Pullup/Down Driver
Figure 12. SD_MODE Resistor Connection Using Open-Drain Driver
GPIO
PROCESSOR
V
DDIO
R
100kI
±8%
LEFT MODE
RIGHT MODE
(LEFT + RIGHT/2
MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
V
SD_MODE
MAX98355A
MAX98355B
GPIO
PROCESSOR
V
DDIO
R
100kI
±8%
LEFT MODE
RIGHT MODE
(LEFT + RIGHT)/2
MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
V
SD_MODE
MAX98355A
MAX98355B