Datasheet

PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
I
2
C TIMING
Serial Clock Frequency f
SCL
0
400
kHz
Bus Free Time Between STOP
and START Conditions
t
BUF
1.3 µs
Hold Time (Repeated) START
Condition
t
HD
,
STA
0.6 µs
SCL Pulse-Width Low t
LOW
1.3 µs
SCL Pulse-Width High t
HIGH
0.6 µs
Repeated START Condition
Setup Time
t
SU
,
STA
0.6 µs
Data Hold Time
t
HD
,
DAT
0
900
ns
Data Setup Time
t
SU
,
DAT
100
ns
Bus Capacitance C
B
400
pF
SDA and SCL Receiving Rise
Time (Note 8)
t
R
20 +
0.1C
B
300
ns
SDA and SCL Receiving Fall
Time (Note 8)
t
F
20 +
0.1C
B
300
ns
DV
DD
= 1.8V, T
A
= +25°C
20 +
0.1C
B
250
SDA Transmitting Fall Time
(Note 8)
t
F
DV
DD
= 3.6V, T
A
= +25°C
20 +
0.05C
B
250
ns
Setup Time for STOP Condition
t
SU
,
STO
0.6 µs
Pulse Width of Suppressed Spike
t
SP
050ns
DIGITAL AUDIO TIMING
BCLK Period (Note 9) t
BCLK
3 x
1 / f
IC LK
ns
Low or High BCLK Pulse Width
t
BCLK_PW
0.35 x
t
BCLK
ns
BCLK and LRCLK Rise Time t
R
Master mode, C
LOAD
= 15pF 1 ns
BCLK and LRCLK Fall Time t
F
Master mode, C
LOAD
= 15pF 1 ns
SDIN or LRCLK to BCLK Rising
Setup Time
t
DBSU,
t
BWSU
30 ns
DV
DD
= 1.8V 0
SDIN or LRCLK to BCLK Rising
Hold Time
t
DBH,
t
BWBH
DV
DD
= 3.6V 5
ns