9-5139; Rev 1; 3/11 KIT ATION EVALU E L B AVAILA Low-Power, High-Performance Dual I2S Stereo Audio Codec Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9880AEWM+ -40°C to +85°C 48 WLP MAX9880AETM+ -40°C to +85°C 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ABSOLUTE MAXIMUM RATINGS (Voltages with respect to AGND.) DVDD, AVDD, PVDD ................................................-0.3V to +2V DVDDS1, JACKSNS, MICVDD ..............................-0.3V to +3.6V DGND, PGND........................................................-0.1V to +0.1V PREG, REF, REG ....................................-0.3V to (VAVDD + 0.3V) MICBIAS .............................................-0.3V to (VMICVDD + 0.
Low-Power, High-Performance Dual I2S Stereo Audio Codec (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Low-Power, High-Performance Dual I2S Stereo Audio Codec (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Low-Power, High-Performance Dual I2S Stereo Audio Codec (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Low-Power, High-Performance Dual I2S Stereo Audio Codec (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Low-Power, High-Performance Dual I2S Stereo Audio Codec (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Low-Power, High-Performance Dual I2S Stereo Audio Codec (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, differential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Low-Power, High-Performance Dual I2S Stereo Audio Codec -20 3kHz 1kHz -60 -80 20Hz -90 -90 -100 -100 20 30 40 -20 -50 1kHz 6kHz -60 -70 20Hz -80 20Hz -90 -100 0 50 -40 10 20 30 40 50 60 10 0 20 30 40 50 POWER OUT (mW) POWER OUT (mW) POWER OUT (mW) TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION + NOISE vs.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.
Low-Power, High-Performance Dual I2S Stereo Audio Codec -60 -65 -70 20Hz 3kHz -75 20Hz 6kHz -40 -60 -80 -80 -85 -90 -90 4 6 8 10 12 6kHz -70 -85 2 1kHz -50 -80 0 20Hz -100 0 2 4 6 8 10 12 3 0 6 9 12 15 POWER OUT (mW) POWER OUT (mW) POWER OUT (mW) TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTON + NOISE vs. FREQUENCY (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION + NOISE vs.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.) THD+N (dB) 0.
Low-Power, High-Performance Dual I2S Stereo Audio Codec VRIPPLE = 100mVP-P -20 20 PSRR (dB) -40 -50 -60 AMPLITUDE (dB) -40 -60 -80 -70 -100 -60 -80 -120 -90 -100 -120 1 10 100 1k 10k 100k -140 1 10 100 1k 10k 100k 0 5k 10k 15k 20k FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 13MHz, fLRCLK = 8kHz FFT, DAC TO HEADPHONE, 0dBFS, fMCLK = 12.288MHz, fLRCLK = 48kHz FFT, DAC TO HEADPHONE, -60dBFS, fMCLK = 12.
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.
Low-Power, High-Performance Dual I2S Stereo Audio Codec 0 FREQ1 = 0xA -20 AMPLITUDE (dB) -40 -60 -80 -60 -80 -140 40k 60k 80k 100k 120k -40 -60 DVFLT = 4 -140 20k 0 -20 -80 -120 -120 fLRCLK = 8kHz DVFLT = 3 -40 -100 -100 DVFLT = 0 0 -100 0 20k 40k 60k 80k 100k 120k 0 100 200 300 400 500 600 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) ADC IIR HIGHPASS FILTER FREQUENCY RESPONSE, MODE = 0 DAC IIR/FIR LOWPASS FILTER FREQUENCY RESPONSE (fLRCLK = 8kHz) DAC FIR LOWPASS
Typical Operating Characteristics (continued) (VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, differential output, unless otherwise noted.
Low-Power, High-Performance Dual I2S Stereo Audio Codec TOP VIEW (BUMP SIDE DOWN) + MAX9880A 1 2 3 4 5 6 7 8 DGND X1 X2 IRQ MODE AVDD PREG AGND DVDD SDA/DIN SCL/SCLK CS DOUT REF MICVDD MICBIAS SDINS2 LRCLKS2 BCLKS2 N.C. N.C. REG MICLN/ DIGMICCLK MICRP/ SPDMDATA MCLK SDOUTS2 SDINS1 N.C. JACKSNS/ AUX N.C.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Pin Description PIN NAME FUNCTION TQFN-EP WLP 1 B2 SDA/DIN 2 B3 SCL/SCLK 3 A2 X1 Crystal Oscillator Input. Connect load capacitor and one terminal of the crystal to this pin. Acceptable input frequency range: 10MHz to 30MHz. 4 A3 X2 Crystal Oscillator Output. Connect load capacitor and second terminal of the crystal to this pin. 24 I2C Serial-Data Input/Output (MODE = 0).
Low-Power, High-Performance Dual I2S Stereo Audio Codec PIN NAME FUNCTION TQFN-EP WLP 23 E8 LINL Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor. 24 F8 LINR Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor. 25 F7 LOUTR 26 E7 LOUTL Left-Line Output 27 E6, F6 PGND Headphone Power Ground 29 E5 ROUTP Positive Right-Channel Headphone Output. Connect directly to the load in differential and capacitorless mode.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Detailed Description The MAX9880A is a low-power stereo audio codec designed for portable applications requiring minimum power consumption. The stereo playback path accepts digital audio through flexible digital audio interfaces compatible with I2S, TDM, and left-justified audio signals. The MAX9880A can process two simultaneous digital input streams that can be mixed digitally.
Low-Power, High-Performance Dual I2S Stereo Audio Codec REGISTER B7 B6 B5 B4 B3 B2 B1 B0 REGISTER POR ADDRESS STATE (SEE NOTE) R/W DAI1 CLOCK CONTROL Stereo Audio Clock Control High PLL1 NI1[14:8] Stereo Audio Clock Control Low NI1[7:1] RLK1/NI1[0] 0x06 0x00 R/W 0x07 0x00 R/W DAI1 CONFIGURATION Interface Mode A MAS1 WCI1 BCI1 Interface Mode B DL1 SEL1 SDOEN1 Time-Division Multiplex SLOTL1 DLY1 HIZOFF1 TDM1 FSW1 SDIEN1 DMONO1 SLOTR1 0 BSEL1 SLOTDLY1[3:0] 0x08 0x00 R
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Table 1. Register Map (continued) REGISTER REGISTER POR ADDRESS STATE (SEE NOTE) B7 B6 B5 B4 B3 B2 B1 B0 R/W Enable LNLEN LNREN LOLEN LOREN DALEN DAREN ADLEN ADREN 0x26 0x00 R/W System Shutdown SHDN 0 0 0 XTEN XTOSC 0 0 0x27 0x00 R/W 0xFF 0x42 R/W POWER MANAGEMENT REVISION ID Revision ID REV *Reserved. Grayed boxes = Not used. Note: Register addresses listed are for I2C.
Low-Power, High-Performance Dual I2S Stereo Audio Codec BITS FUNCTION CLD Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC. To resolve a clip condition in the signal path, the DAC gain settings and analog input gain settings should be lowered. As the CLD bit does not indicate where the overload has occurred, identify the source by lowering gains individually. SLD Slew Level Detect Flag.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Hardware Interrupts If a flag is set, it is reported as a hardware interrupt only if the corresponding interrupt enable is set. Each bit enables interrupts for the status flag in the respective bit location in register 0x00. Hardware interrupts are reported on the open-drain IRQ pin. When an interrupt occurs, IRQ remains low until the interrupt is serviced by reading the status register 0x00. Table 4.
Low-Power, High-Performance Dual I2S Stereo Audio Codec BITS PSCLK MAX9880A Table 5. System and Audio Clock Registers (continued) FUNCTION MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz. 00 = Disable clock for low-power shutdown. 01 = Select if MCLK is between 10MHz and 20MHz. PCLK = MCLK. 10 = Select if MCLK is between 20MHz and 40MHz. PCLK = MCLK/2. 11 = Select if MCLK is greater than 40MHz. PCLK = MCLK/4. Exact Integer Modes.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Table 6. Common NI Values (DAI1, DAI2 for DHF = 0) LRCLK (kHz) PCLK (MHz): (Note: Any PCLK from 10MHz to 20MHz with any LRCLK 7.8kHz to 50kHz can be used.) (DAI2 for DHF = 1) 8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96 10 13A9 1B18 1D7E 2752 3631 3AFB 4EA5 6C61 75F7 4EA5 6C61 75F7 11 11E0 18A2 1ACF 23BF 3144 359F 477E 6287 6B3E 477E 6287 6B3E 11.
Low-Power, High-Performance Dual I2S Stereo Audio Codec B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE) Interface Mode A MAS1 WCI1 BCI1 DLY1 HIZOFF1 TDM1 FSW1 0 0x08 Interface Mode B DL1 SEL1 SDOEN1 SDIEN1 DMONO1 REGISTER DAI1 CONFIGURATION Time-Division Multiplex SLOTL1 SLOTR1 BSEL1 0x09 SLOTDLY1[3:0] 0x0A DAI2 CONFIGURATION Interface Mode A MAS2 WCI2 BCI2 DLY2 HIZOFF2 Interface Mode B DL2 SEL2 SDOEN2 SDIEN2 DHF Time-Division Multiplex SLOTL2 SLOTR2 TDM2
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Table 7. Digital Audio Interface Registers (continued) BITS FUNCTION TDM1/2 TDM Mode Select 1 = Enables time-division multiplex mode and configures the audio interface to accept PCM data. 0 = Disables time-division multiplex mode. LRCLK signal polarity indicates left and right audio.
Low-Power, High-Performance Dual I2S Stereo Audio Codec BITS FUNCTION BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unless sharing the bus with multiple devices. BSEL BSEL1/2 DESCRIPTION 000 Off (BCLK output held low) 001 64x LRCLK (192x internal clock divided by 3) 010 48x LRCLK (192x internal clock divided by 4) 011 128x LRCLK (Note: Not a valid BSEL2 choice when DHF = 1.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec AUDIO MASTER MODES: LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0 7ns (typ) 7ns (typ) LRCLK RIGHT LEFT 1/fS RELATIVE TO PCLK (SEE NOTE) D15 SDOUT D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) 7ns (typ) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 7ns (typ) BCLK 20ns (min) CONFIGURED BY BSEL 5ns (min) SDIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A AUDIO SLAVE MODES: LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0 LEFT LRCLK RIGHT 1/fS 20ns (min) D15 SDOUT 0ns (min) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 30ns (min) BCLK 20ns (min) 75ns (min) 5ns (min) SDIN 30ns (min) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec VOICE (TDM/PCM) MASTER MODES: TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0 7ns (typ) 7ns (typ) LRCLK 1/fS 200ns SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 40ns (max) 0ns (min) 7ns (typ) 7ns (typ) BCLK 20ns (min) SDIN 0ns (min) CONFIGURED BY BSEL L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A VOICE (TDM/PCM) SLAVE MODES: TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0 LRCLK 1/fS 20ns SDOUT 0ns (min) 0ns (min) L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 40ns (max) 0ns (min) 30ns (min) 7ns (typ) BCLK 20ns (min) SDIN 75ns (min) 0ns (min) 30ns (min) L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Digital Filtering The MAX9880A incorporates both IIR (voice) and FIR (audio) digital filters to accomodate a wide range of audio sources. The IIR fiilters provide over 70dB of stopband attenuation as well as selectable highpass filters. The FIR filters provide low power consumption and are linear phase to maintain stereo imaging. Table 9.
Low-Power, High-Performance Dual I2S Stereo Audio Codec REGISTER B7 Configuration SPDMCLK Input B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE) SPDML SPDMR 0 0 0 0 0x12 B6 MIXSPDML MIXSPDMR 0x13 Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI. The MAX9880A supports stereo PDM outputs.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Digital Gain Control The MAX9880A includes gain adjustment for the playback and record paths. Independent gain adjustment is provided for the two record channels. Sidetone gain adjustment is also provided to set the sidetone level relative to the playback level. Table 12.
Low-Power, High-Performance Dual I2S Stereo Audio Codec BITS MAX9880A Table 12. Digital Gain Registers (continued) FUNCTION SDACM/ VDACM DAC Mute Enable 0 = No mute 1 = Mute VDACG DAC Gain 00 = 0dB 01 = +6dB 10 = +12dB 11 = +18dB Note: VDACG is only used when MODE = 0. If MODE = 1, then the DAC gain is always 0dB. DAC Level Control. VDACA/SDACA works in all modes.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Line Inputs Playback Volume The MAX9880A include one pair of single-ended line inputs. When enabled the line inputs connect directly to the headphone amplifier and line outputs and can be optionally connected to the ADC for recording. The MAX9880A incorporates volume and mute control to allow level control for the playback audio path. Program registers 0x1C and 0x1D to set the desired volume.
Low-Power, High-Performance Dual I2S Stereo Audio Codec BITS MAX9880A Table 14. Playback Volume Registers (continued) FUNCTION Left/Right Playback Volume. VOLL and VOLR control the playback volume for both the DAC and line input audio signals. VOLL/VOLR SETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB) 0x00 +9 0x0E -2 0x1C -39 0x01 +8.5 0x0F -3 0x1D -43 0x02 +8 0x10 -5 0x1E -47 0x03 +7.5 0x11 -7 0x1F -51 0x04 +7 0x12 -9 0x20 -55 0x05 +6.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Microphone Inputs microphone signals are amplified by two stages of gain and then routed to the ADCs. The first stage offers selectable 0dB, 20dB, or 30dB settings. The second stage is a programmable gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps. Zero-crossing detection is included on the PGA to minimize zipper noise while making gain changes. See Figure 6 for a detailed diagram of the microphone input structure.
Low-Power, High-Performance Dual I2S Stereo Audio Codec BITS MAX9880A Table 16. Microphone Input Registers (continued) FUNCTION Left/Right Microphone Programmable Gain Amplifier PGAML/ PGAMR SETTING GAIN (dB) SETTING GAIN (dB) 0x00 0x01 +20 0x0B +9 +19 0x0C +8 0x02 +18 0x0D +7 0x03 +17 0x0E +6 0x04 +16 0x0F +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 to 0x1F 0 0x0A +10 ADC The MAX9880A includes two 18-bit ADCs.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Offset Calibration Procedure Perform before the first DC measurement is taken after applying power to the MAX9880A. Complete DC Measurement Example fMCLK = 13MHz, slave mode, BCLK, and LRCLK are not externally supplied. 1) Enable the AUX input (AUXEN = 1). 1) Configure the digital audio interface for fs = 48kHz (PSCLK = 01, FREQ1 = 0x0, PLL = 0, NI = 0x5ABE, MAS = 0). 2) Enable the offset calibration (AUXCAL = 1).
Low-Power, High-Performance Dual I2S Stereo Audio Codec REGISTER Input B7 B6 MXINL B5 B4 MXINR B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE) AUXCAP AUXGAIN AUXCAL AUXEN 0x22 Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Digital Microphone Input microphone input. The right analog microphone input is still available to allow a combination of analog and digital microphones to be used. Figure 7 shows the digital microphone interface timing diagram. The MAX9880A can accept audio from up to two digital microphones.
Low-Power, High-Performance Dual I2S Stereo Audio Codec and providing information to assist the system controller in determining the configuration of an inserted plug. If programmed to do so, upon insertion or removal of a plug, the IRQ output is asserted (pulled low). Table 20 shows the registers associated with the jack detect function in MAX9880A. Table 20.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec LOUTP MIC GND HPR MICBIAS HPL JACKSNS/AUX ROUTP MICLP Figure 8. Typical Configuration for Headset Detection Table 22. Debounce Time JDEB DEBOUNCE (ms) 00 25 01 50 10 100 11 200 Debounce (JDEB) Configures the JDET debounce time for changes to JKSNS[1:0] according to Table 22. For jack plug insertion/removal, the sequence of events is as follows: Jack insertion: No jack is present.
Low-Power, High-Performance Dual I2S Stereo Audio Codec JACK ACTION IRQ TOGGLES? JKSNS SHDN MICBIAS JDWK FROM TO FROM TO IJDET = 1 0 — 0 None Headset 11 01 Yes No 0 — 0 None Headphone 11 00 Yes No IJDET = 0 0 — 0 Headset None 01 11 Yes No 0 — 0 Headphone None 00 11 Yes No 0 — 1 None Headset 11 00 Yes No 0 — 1 None Headphone 11 00 Yes No 0 — 1 Headset None 00 11 Yes No 0 — 1 Headphone None 00 11 Yes No 1 0 0 None Headset
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Headphone Modes The MAX9880A’s headphone amplifier supports differential, single-ended, and capacitorless output modes, as shown in Figure 9. In each mode, the amplifier can be configured for stereo or mono operation. The single- DIFFERENTIAL ended mode optionally includes click-and-pop reduction to eliminate the click-and-pop that would normally be caused by the output coupling capacitor.
Low-Power, High-Performance Dual I2S Stereo Audio Codec BITS MAX9880A Table 24.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Table 25. Power Management Register B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS (SEE NOTE) Enable LNLEN LNREN LOLEN LOREN DALEN DAREN ADLEN ADREN 0x26 System Shutdown SHDN 0 0 0 XTEN XTOSC 0 0 0x27 REGISTER Grayed boxes = Not used. Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not accessible through SPI.
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A tCSS tCSH tCP CS tCSW tCL SCLK tCH DIN tDH tDS tDZ tDO tDEN DOUT Figure 10. SPI Interface Timing Diagram CS SCLK DIN DOUT R/W ADDR9 ADDR0 UNUSED4 HIGH-Z UNUSED0 D7 D0 1 DATA BYTE Figure 11. Writing 1 Byte of Data to the MAX9880A Serial Peripheral Interface (SPI) Chip Select (CS) The MAX9880A SPI interface is active only when CS is low.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec CS SCLK DIN R/W ADDR9 ADDR0 UNUSED4 UNUSED0 HIGH-Z DOUT D7 D0 1 DATA BYTE Figure 12. Reading 1 Byte of Data from the MAX9880A CS SCLK DIN DOUT R/W ADDR9 ADDR0 UNUSED4 HIGH-Z UNUSED0 D7 D0 D7 1 DATA BYTE D0 1 DATA BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 13. Reading n Bytes of Data from the MAX9880A do not change until the transfer is complete.
Low-Power, High-Performance Dual I2S Stereo Audio Codec MAX9880A SDA tLOW tBUF tSU,STA tSU,DAT tHD,STA tSP tHD,DAT tSU,STO tHIGH SCL tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 14. 2-Wire Interface Timing Diagram S Sr P SCL SDA Figure 15. START, STOP, and Repeated START Conditions sequence is framed by a START or repeated START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 1 2 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 16. Acknowledge ACKNOWLEDGE FROM MAX9880A B7 ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS 0 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9880A A REGISTER ADDRESS R/W A A DATA BYTE P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 17.
Low-Power, High-Performance Dual I2S Stereo Audio Codec Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9880A acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX9880A is the contents of register 0x00.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec ACKNOWLEDGE FROM MAX9880A ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS 0 A REGISTER ADDRESS ACKNOWLEDGE FROM MAX9880A A Sr SLAVE ADDRESS REPEATED START R/W NOT ACKNOWLEDGE FROM MASTER 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 20. Reading n Bytes of Data Applications Information Proper layout and grounding are essential for optimum performance.
Low-Power, High-Performance Dual I2S Stereo Audio Codec SEQUENCE DESCRIPTION MAX9880A Table 29. Line Input Playback REGISTERS 1 Set line input gain 0x1A, 0x1B 2 Set volume 0x1C, 0x1D 3 Set line output volume (if using) 0x1E, 0x1F 4 Select headphone mode 0x24 5 Enable line outputs and line inputs as required 0x26 6 Enable MAX9880A 0x27 7 Enable external amplifier (if using) N/A Table 30.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Table 32. Voice Microphone Record SEQUENCE DESCRIPTION REGISTERS 1 Select voice filters 2 Set ADC level to 0dB 0x18, 0x19 0x11 3 Configure microphone gain 0x20, 0x21 4 Set line output volume (if using) 0x1E, 0x1F 5 Configure ADC input mixer 0x22 6 Configure MICBIAS voltage 0x23 7 Enable ADC 0x26 8 Enable LRCLK and BCLK (if operating in slave mode) N/A 9 Enable MAX9880A 0x27 Table 33.
Low-Power, High-Performance Dual I2S Stereo Audio Codec Music Playback fMCLK = 12.288MHz (master clock supplied to codec), fLRCLK = 48kHz, standard I2S format, codec in slave mode, music source connected through S2 pins to DAI2 audio path, and output on headphone amplifiers (output capacitorless mode). Table 34.
1µF FM RECEIVER 20 (C8) 21 (D8) 23 (E8) MICLN/ DIGMICCLK MICRP/ SPDMDATA MICRN/ SPDMCLK LINL LINR 18 (C7) MICLP/ DIGMICDATA 24 (F8) 19 (D7) MICBIAS 1µF 17 (B8) 10 (B6) 13 (C6) REF REG 2.2µF REF 16 (B7) DVDDS1 36 (F2) PGAMR: +20dB TO 0dB LNREN LIGR: +30dB TO 0dB LNLEN LIGL: +30dB TO 0dB SPDMCLK PAREN: 0/20/30dB SPDMDATA IRQ PREG 8 (A4) 1µF PGAML: +20dB TO 0dB VCM MICVDD PALEN: 0/20/30dB MICBIAS 1µF 1.
Low-Power, High-Performance Dual I2S Stereo Audio Codec For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Package Information (continued) For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Low-Power, High-Performance Dual I2S Stereo Audio Codec For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
MAX9880A Low-Power, High-Performance Dual I2S Stereo Audio Codec Revision History REVISION NUMBER REVISION DATE 0 7/10 1 3/11 DESCRIPTION Initial release Various data sheet errors PAGES CHANGED — 15–22, 24, 29, 31, 47, 49, 51, 52, 55–58, 60, 61, 62, 66 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.