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MAXQ FAMILY USER’S GUIDE

Rev: 6; 9/08

Data

Memory

I/O

Source

1:16 16:1

Instruction

Decoder

ALU

I/O

Program

Memory

Destination

Note: The MAXQ Family User's Guide should be used in conjunction with the data sheet(s) for MAXQ microcontrollers.

Summary of content (216 pages)

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MAXQ FAMILY USER’S GUIDE Program Memory Data Memory IR Instruction Decoder Source Destination IP DP SP 1:16 16:1 ALU I/O I/O Functional Diagrams I/O Note: The MAXQ Family User's Guide should be used in conjunction with the data sheet(s) for MAXQ microcontrollers. Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc.
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MAXQ Family User’s Guide TABLE OF CONTENTS SECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 SECTION 2: Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 SECTION 3: Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 SECTION 4: System Register Descriptions .
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MAXQ Family User’s Guide SECTION 1: OVERVIEW This section contains the following information: 1.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2 1.2 Harvard Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2 1.3 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 1: OVERVIEW The MAXQ® family of 16-bit reduced instruction set computing (RISC) microcontrollers is targeted toward low-cost, low-power, embedded-application designs. The flexible, modular architecture design used in these microcontrollers allows development of targeted designs for specific applications with minimal effort.
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MAXQ Family User’s Guide • Real-Time Clock • 1-Wire® Bus Master • General-Purpose Digital I/O Ports 1.4 MAXQ10 and MAXQ20 Microcontrollers This user’s guide covers both the 8-bit MAXQ10 and 16-bit MAXQ20 microcontrollers. The primary difference between the MAXQ10 and MAXQ20 implementations is the width of the internal data bus and ALU. The MAXQ10 design implements an 8-bit internal data bus and ALU, while the MAXQ20 design implements a 16-bit internal data bus and ALU.
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MAXQ Family User’s Guide SECTION 2: ARCHITECTURE This section contains the following information: 2.1 Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 2.2 Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide 2.9.2 Power Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19 2.9.2.1 Switchback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20 2.9.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20 LIST OF FIGURES Figure 2-1. MAXQ Transport-Triggered Architecture . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 2: ARCHITECTURE The MAXQ architecture is designed to be modular and expandable. Top-level instruction decoding is extremely simple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the System Register and Peripheral Register groups. Figure 2-1 illustrates the modular architecture and the basic transport possibilities.
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MAXQ Family User’s Guide Memory access from the MAXQ is based on a Harvard architecture with separate address spaces for program and data memory. The simple instruction set and transport-triggered architecture allow the MAXQ to run in a nonpipelined execution mode where each instruction can be fetched from memory, decoded, and executed in a single clock cycle. Data memory is accessed through one of three data pointer registers. Two of these data pointers, DP[0] and DP[1], are stand-alone 16-bit pointers.
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MAXQ Family User’s Guide 2.2 Register Space The MAXQ architecture provides a total of 16 register modules. Each of these modules contains 32 registers. The first eight registers in each module may be read from or written to in a single cycle; the second eight registers may be read from in a single cycle and written to in two cycles (by using the prefix register PFX); the last sixteen registers may be read or written in two cycles (always requiring use of the prefix register PFX).
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MAXQ Family User’s Guide 2.3 Memory Organization Beyond the internal register space, memory on the MAXQ microcontroller is organized according to a Harvard architecture, with a separate address space and bus for program memory and data memory. Stack memory is also separate and is accessed through a dedicated register set.
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MAXQ Family User’s Guide post increment/decrement source pointers by a MOVE instruction or pre increment/decrement destination pointers by a MOVE instruction. Using Data Pointer indirectly with "++" will automatically increase the content of the active Data Pointer by 1 immediately following the execution of read data transfer (@DP[n]++) or immediately preceding the execution of a write operation (@++DP[n]).
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MAXQ Family User’s Guide page (16kWords) may be logically mapped, as just defined, to either the upper or lower half of data memory. If word access mode is selected, two pages (32kWords total) may be logically mapped to data memory. To avoid memory overlapping in the byte access mode, the physical data memory should be confined to the address range x0000h to x3FFFh in word mode.
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MAXQ Family User’s Guide MAXQ20 MEMORY MAP (DEFAULT CONDITION, UPA = 0) PROGRAM MEMORY 15 MAXQ20 MEMORY MAP (UPA = 1, CDA IS DON’T CARE) PROGRAM MEMORY DATA MEMORY 0 15 0 LOGICAL SPACE 0 15 xFFFF xFFFF DATA MEMORY 0 15 xFFFF xFFFF LOGICAL SPACE P3 PHYSICAL PROGRAM (P3) Physical Program (P0) P2 xA000 PHYSICAL PROGRAM (P2) UTILITY ROM x8000 x8000 PHYSICAL PROGRAM (P1) LOGICAL UTILITY ROM x8000 x8000 PHYSICAL PROGRAM (P1) LOGICAL SPACE LOGICAL SPACE x4000 PHYSICAL PROGRAM (P0) x400
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MAXQ Family User’s Guide When executing from the data memory (only allowable when UPA = 0): • Program flows freely between the lower 32k user code (P0 and P1) and the utility ROM segment. • The upper half of the code segment (P2 and P3) is not accessible as program (since UPA = 0). • The utility ROM can be accessed as data with offset at x8000h. • One page (byte access mode) or two pages (word access mode) can be accessed as data with offset at x0000h as determined by the CDA1:0 bits. 2.
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MAXQ Family User’s Guide MAXQ20 MEMORY MAP (UPA = 0, EXECUTING FROM UTILITY ROM) PROGRAM MEMORY 15 DATA MEMORY 0 15 0 xFFFF LOGICAL SPACE P3 LOGICAL DATA P2 xA000 UTILITY ROM CDA1 = 1 x8000 x8000 PHYSICAL PROGRAM (P1) x4000 A1 PHYSICAL PROGRAM (P0) =0 CD PHYSICAL DATA x0000 x0000 MAXQ20 MEMORY MAP (UPA = 0, EXECUTING FROM LOGICAL DATA MEMORY) PROGRAM MEMORY 15 DATA MEMORY 0 0 15 xFFFF xFFFF LOGICAL SPACE P3 LOGICAL SPACE LOGICAL DATA MEMORY P2 xA000 LOGICAL UTILITY ROM UTILITY ROM
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MAXQ Family User’s Guide EXECUTING FROM UTILITY ROM (UPA = 0, ONLY P1, P2 PRESENT) PROGRAM MEMORY 15 DATA MEMORY 0 7 0 xFFFF xFFFF LOGICAL SPACE LOGICAL DATA MEMORY xA000 UTILITY ROM x8000 x8000 0=1 CDA PHYSICAL PROGRAM (P1) PHYSICAL DATA A0 =0 CD PHYSICAL PROGRAM (P0) x0000 x0000 EXECUTING FROM LOGICAL DATA MEMORY (UPA = 0, ONLY P1, P2 PRESENT) PROGRAM MEMORY 15 DATA MEMORY 7 0 0 xFFFF xFFFF LOGICAL SPACE LOGICAL SPACE LOGICAL DATA MEMORY xA000 UTILITY ROM x8000 x8000 PHYSICAL PROGR
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MAXQ Family User’s Guide - Physical program memory pages (P0, P1, P2, P3) are logically mapped into data space based upon the memory segment currently being used for execution, selection of byte/word access mode, and CDA1:0 bit settings (described under Pseudo Von Neumann Memory Map and Pseudo Von Neumann Memory Access.) • Data memory - Access can be either word or byte. - All 16 data pointer address bits are significant in either access mode (word or byte.) 2.
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MAXQ Family User’s Guide The external clock and crystal are mutually exclusive since they are input via the same clock pin. The basic clock source selection is made through two bits: RGSL and XT/RC. The RGSL bit controls selection of the internal ring oscillator for system clock generation. When RGSL = 1, the internal ring oscillator is used for system clock generation.
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MAXQ Family User’s Guide resistor to ensure a satisfactory logic level for active clock pulses. To minimize system noise on the clock circuitry, the external clock source must meet the maximum rise and fall times and the minimum high and low times specified for the clock source. The external noise can affect clock generation circuit if these parameters do not meet the specification. 2.7.4 External RC For timing-insensitive applications, the external RC option offers additional cost savings.
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MAXQ Family User’s Guide 2.8 Interrupts The MAXQ provides a single, programmable interrupt vector (IV) that can be used to handle internal and external interrupts. Interrupts can be generated from system level sources (e.g., watchdog timer) or by sources associated with the peripheral modules included in the specific MAXQ microcontroller. Only one interrupt can be handled at a time, and all interrupts naturally have the same priority.
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MAXQ Family User’s Guide SYSTEM MODULES WATCHDOG EWDI (LOCAL ENABLE) IMS (SYSTEM ENABLE) GPI/O MODULE INT0 ƒ INT1 ƒ IT0 IMx (MODULE ENABLE) INT2 INT3 INT4 ƒ INS (INTERRUPT IN SERVICE) ƒ INTERRUPT VECTOR INT5 IT1 IGE (GLOBAL ENABLE) EX0-EX5 (LOCAL ENABLES) TIMER/COUNTER MODULE TF0 TF1 EXF1 ET0, ET1 (LOCAL ENABLES) IMx (MODULE ENABLE) SERIAL I/O MODULE RI TI SPIC ROVR WCOL MODF ESI, ESPII (LOCAL ENABLES) IMx (MODULE ENABLE) NOTE: ONLY A FEW OF THE MANY POSSIBLE MAXQ PERIPHERAL MODULES A
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MAXQ Family User’s Guide • if the system clock divide ratio is 2, the interrupt request is recognized after 2 system clock; • if the system clock divide ratio is 4 or greater, the interrupt request is recognized after 1 system clock; An interrupt request with a pulse width less than three undivided clock cycles is not recognized. Note that the granularity of interrupt source is at module level.
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MAXQ Family User’s Guide Certain MAXQ devices may also incorporate brownout detection capability. For these devices, an on-chip precision reference and comparator monitor the supply voltage VDD to ensure that it is within acceptable limits. If VDD is below the power-fail level, the power monitor initiates a reset condition. This can occur either when the MAXQ is first powered up when the VDD supply is above the POR voltage threshold, or when VDD drops out of tolerance from an acceptable level.
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MAXQ Family User’s Guide The PMME bit may not be set to 1 if any potential switchback source is active. Attempts to set the PMME bit under these conditions result in a no-op. 2.9.2.1 Switchback When Power Management Mode is active, the MAXQ operates at a reduced clock rate. Although execution continues as normal, peripherals that base their timing on the system clock such as the UART module and the SPI module may be unable to operate normally or at a high enough speed for proper application response.
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MAXQ Family User’s Guide SECTION 3: PROGRAMMING This section contains the following information: 3.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.2 Prefixing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.3 Reading and Writing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide 3.8 Handling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13 3.8.1 Conditional Return from Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14 3.9 Accessing the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 3.10 Accessing Data Memory . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 3: PROGRAMMING The following section provides a programming overview of the MAXQ. For full details on the instruction set, as well as System Register and Peripheral Register detailed bit descriptions, see the appropriate sections in this user’s guide. 3.1 Addressing Modes The instruction set for the MAXQ provides three different addressing modes: direct, indirect, and immediate.
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MAXQ Family User’s Guide 3.3 Reading and Writing Registers All functions in the MAXQ are accessed through registers, either directly or indirectly. This section discusses loading registers with immediate values and transferring values between registers of the same size and different sizes. 3.3.1 Loading an 8-Bit Register With an Immediate Value Any writeable 8-bit register with a sub-index from 0h to 7h within its module can be loaded with an immediate value in a single cycle using the MOVE instruction.
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MAXQ Family User’s Guide 8-bit destination ← high byte (16-bit source) If, however, we needed to load an 8-bit register with the high byte of a 16-bit source, it would be best to use the GR register. Transferring the 16-bit source to the GR register adds a single cycle.
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MAXQ Family User’s Guide 3.4 Reading and Writing Register Bits The MOVE instruction can also be used to directly set or clear any one of the lowest 8 bits of a peripheral register in module 0h-5h or a system register in module 8h. The set or clear operation will not affect the upper byte of a 16-bit register that is the target of the set or clear operation.
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MAXQ Family User’s Guide • SLA (Arithmetic shift left on active accumulator) • SLA2 (Arithmetic shift left active accumulator two bit positions) • SLA4 (Arithmetic shift left active accumulator four bit positions) • SRA (Arithmetic shift right on active accumulator) • SRA2 (Arithmetic shift right active accumulator two bit positions) • SRA4 (Arithmetic shift right active accumulator four bit positions) • RL (Rotate active accumulator left) • RLC (Rotate active accumulator left through Carry flag) • RR (Rot
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MAXQ Family User’s Guide For the modulo increment or decrement operation, the selected range of bits in AP are incremented or decremented. However, if these bits roll over or under, they simply wrap around without affecting the remaining bits in the accumulator pointer.
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MAXQ Family User’s Guide 3.5.4 ALU Operations Using Only the Active Accumulator The following arithmetic and logical operations operate only on the active accumulator.
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MAXQ Family User’s Guide 3.5.7 MAXQ20 Example: Adding Two 4-Byte Numbers Using Auto-Increment move A[0], #5678h ; First number – 12345678h move A[1], #1234h move A[2], #0AAAAh ; Second number – 0AAAAAAAh move A[3], #0AAAh move APC, #81h ; Active Acc = A[0], increment low bit = mod 2 add A[2] ; A[0] = 5678h + AAAAh = 0122h + Carry addc A[3] ; A[1] = 1234h + AAAh + 1 = 1CDFh ; 12345678h + 0AAAAAAAh = 1CDF0122h 3.
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MAXQ Family User’s Guide • SLA, SLA2, SLA4 (Arithmetic shift left active accumulator) • SRA, SRA2, SRA4 (Arithmetic shift right active accumulator) • SR (Shift active accumulator right) • RLC/RRC (Rotate active accumulator left / right through Carry) • MOVE C, Acc. (Set Carry to selected active accumulator bit) • MOVE C, #i (Explicitly set, i = 1, or clear, i = 0, the Carry flag) • CPL C (Complement Carry) • AND Acc. • OR Acc. • XOR Acc. • MOVE C, src.
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MAXQ Family User’s Guide 3.7.2 Unconditional Jumps An unconditional jump can be relative (IP +127/-128 words) or absolute (to anywhere in program space). Relative jumps must use an 8-bit immediate operand, such as Label1: ... jump Label1 ; must be within +127/-128 words of the JUMP Absolute jumps can use a 16-bit immediate operand, a 16-bit register, or an 8-bit register.
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MAXQ Family User’s Guide When the supplied loop address is outside the relative jump range, the prefix register (PFX[0]) is used to supply the high byte of the loop address as required. move LoopTop: call ...
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MAXQ Family User’s Guide Once the interrupt handler receives the interrupt, the Interrupt in Service (INS) bit will be set by hardware to block further interrupts, and execution control is transferred to the interrupt service routine. Within the interrupt service routine, the source of the interrupt must be determined. Since all interrupts go to the same interrupt service routine, the Interrupt Identification Register (IIR) must be examined to determine which module initiated the interrupt.
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MAXQ Family User’s Guide 3.9 Accessing the Stack The hardware stack is used automatically by the CALL, RET and RETI instructions, but it can also be used explicitly to store and retrieve data. All values stored on the stack are 16 bits wide. The PUSH instruction increments the stack pointer SP and then stores a value on the stack. When pushing a 16-bit value onto the stack, the entire value is stored.
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MAXQ Family User’s Guide The Frame Pointer (BP[OFFS]) is actually composed of a base pointer (BP) and an offset from the base pointer (OFFS). For the frame pointer, the offset register (OFFS) is the target of any increment or decrement operation. The base pointer (BP) is unaffected by increment and decrement operations on the Frame Pointer.
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MAXQ Family User’s Guide The following data pointer related instructions are invalid: move move move move move move move move move move move move move move move move move move move move move move move move @++DP[0], @DP[0]++ @++DP[1], @DP[1]++ @BP[++Offs], @BP[Offs++] @--DP[0], @DP[0]-@--DP[1], @DP[1]-@BP[--Offs], @BP[Offs--] @++DP[0], @DP[0]-@++DP[1], @DP[1]-@BP[++Offs], @BP[Offs--] @--DP[0], @DP[0]++ @--DP[1], @DP[1]++ @BP[--Offs], @BP[Offs++] @DP[0], @DP[0]++ @DP[1], @DP[1]++ @BP[Offs], @BP[Offs++] @DP
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MAXQ Family User’s Guide RWT (WDCN.0) (RESET WATCHDOG) XTAL1 XTAL2 SYSTEM CLOCK MODE DIVIDE BY 212 DIVIDE BY 23 212 WD1 WD0 DIVIDE BY 23 215 218 TIME-OUT SELECTOR WDIF (WDCN.3) DIVIDE BY 23 221 TIME-OUT WATCHDOG INTERRUPT EWDI (WDCN.6) (ENABLE WATCHDOG INTERRUPT) MAXQ 512 SYSCLK DELAY EWT (WDCN.1) (ENABLE WATCHDOG TIMER RESET) RESET WTRF (WDCN.2) Figure 3-1.
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MAXQ Family User’s Guide Table 3-3. Watchdog Timeout Period Selection WATCHDOG TIMEOUT (IN NUMBER OF OSCILLATOR CLOCKS) SYSTEM CLOCK MODE SYSTEM CLOCK SELECT BITS PMME, CD1, CD0 WD1:0 = 00b WD1:0 = 01b WD1:0 = 10b WD1:0 = 11b Divide by 1 (default) 000 212 215 218 221 Divide by 2 001 213 216 219 222 Divide by 4 010 214 217 220 223 Divide by 8 011 15 2 18 2 21 2 224 Power Management Mode (Divide by 256) 1xx 220 223 226 229 Table 3-4.
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MAXQ Family User’s Guide Table 3-5.
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MAXQ Family User’s Guide Table 3-6.
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MAXQ Family User’s Guide SECTION 4: SYSTEM REGISTER DESCRIPTIONS This section contains the following information: 4.1 Accumulator Pointer Register (AP, 8h[0h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2 4.2 Accumulator Pointer Control Register (APC, 8h[1h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2 4.3 Processor Status Flags Register (PSF, 8h[4h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 4.
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MAXQ Family User’s Guide SECTION 4: SYSTEM REGISTER DESCRIPTIONS Those registers currently defined in the MAXQ System Register map are described in the following pages. The addresses for each register are given in the format module[index], where module is the module specifier from 8h to Fh and index is the register sub-index from 0h to Fh. 4.1 Accumulator Pointer Register (AP, 8h[0h]) The bit definitions are for 16 accumulators. Initialization: This register is cleared to 00h on all forms of reset.
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MAXQ Family User’s Guide 4.3 Processor Status Flags Register (PSF, 8h[4h]) The OV and S bit definitions are given for the MAXQ20 (16-bit accumulators and ALU). Initialization: This register is cleared to 80h on all forms of reset. Access: Bit 7 (Z), bit 6 (S), and bit 2 (OV) are read only. Bits 4 and 3 (GPF1,GPF0), bit 1 (C), and bit 0 (E) are unrestricted read/write. BIT FUNCTION PSF.0 (E) Equals Flag. This bit flag is set to 1 whenever a compare operation (CMP) returns an equal result.
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MAXQ Family User’s Guide 4.6 System Control Register (SC, 8h[8h]) Initialization: This register is reset to 100000s0b on all reset. Bit 1 (PWL) is set to 1 on a power-on reset only. Access: Unrestricted read/write access. BIT SC.0 FUNCTION Reserved. All reads return 0. SC.1 (PWL) Password Lock. This bit defaults to 1 on a power-on reset.
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MAXQ Family User’s Guide 4.8 System Clock Control Register (CKCN, 8h[Eh]) Initialization: Bits 4:0 are cleared to zero on all forms of reset. See bit description for bits 7:5. Access: Bit 5 (RGMD) is read-only. All other bits are unrestricted read/write, except for the locking mechanism on CD0 and CD1 as described below. BIT FUNCTION Clock Divide Bit 0. Clock Divide Bit 1.
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MAXQ Family User’s Guide 4.9 Watchdog Control Register (WDCN, 8h[Fh]) Initialization: Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions. Access: Unrestricted direct read/write access. BIT FUNCTION WDCN.0 (RWT) Reset Watchdog Timer. Setting this bit to 1 resets the watchdog timer count.
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MAXQ Family User’s Guide 4.10 (MAXQ10) Accumulator n Register (A[n], 9h[nh]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION This register acts as the accumulator for all ALU arithmetic and logical operations when selected by the accumulator pointer (AP). It can also be used as a general-purpose working register. A[n].7 to A[n].0 4.
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MAXQ Family User’s Guide 4.14 Stack Pointer Register (SP, Dh[1h]) Bits defined below for 16-word stack depth. Initialization: This register is cleared to 000Fh on all forms of reset. Access: Unrestricted direct read/write access. BIT SP.3 to SP.0 SP.15 to SP.4 FUNCTION These four bits indicate the current top of the hardware stack, from 0h to Fh. This pointer is incremented after a value is pushed on the stack and decremented before a value is popped from the stack. Reserved; all reads return 0. 4.
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MAXQ Family User’s Guide 4.19 Data Pointer Control Register (DPC, Eh[4h]) Initialization: (MAXQ10) This register is cleared to 0000h on all forms of reset. (MAXQ20) This register is cleared to 001Ch on all forms of reset. Access: Unrestricted direct read/write access. BIT FUNCTION Source Data Pointer Select Bits 1:0. These bits select one of the three data pointers as the active source pointer for the load operation. A new data pointer must be selected before being used to read data memory: DPC.1 to DPC.
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MAXQ Family User’s Guide 4.23 General Register Byte-Swapped (GRS, Eh[8h]) Initialization: This register is cleared to 0000h on all forms of reset Access: Unrestricted read-only access. BIT GRS.15 to GRS.0 FUNCTION This register is intended primarily for supporting byte operations on 16-bit data. This 16-bit read only register returns the byteswapped value for the data contained in the GR register. 4.
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MAXQ Family User’s Guide SECTION 5: PERIPHERAL REGISTER MODULES The MAXQ microcontroller uses Peripheral Registers to control and monitor peripheral modules. These registers reside in Modules 0h through 5h, with sub-index values 0h to 1Fh. While the peripherals must reside in modules 0h through 5h, they are not necessarily tied to specific index numbers inside this range and can be moved, removed, and/or duplicated for certain MAXQ-based products as space permits.
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MAXQ Family User’s Guide SECTION 6: GENERAL-PURPOSE I/O MODULE This section contains the following information: 6.1 I/O Port: Type A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2 6.2 I/O Port: Type B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2 6.3 I/O Port: Type C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 6: GENERAL-PURPOSE I/O MODULE The General-Purpose I/O Module (GPIO) for the MAXQ supports multiple 8-bit port types, each having different I/O characteristics. From a software perspective, each port appears as a group of Peripheral Registers with unique addresses. The exact quantity and type of ports provided by the GPIO Module is product-dependent. Each of the four different types of I/O ports are described. 6.
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MAXQ Family User’s Guide 6.3 I/O Port: Type C The Type C I/O port is nearly identical to the Type B I/O port, but with the addition of a selectable internal, weak, P-channel, pullup device. The weak pullup device can be enabled by configuring the port pin as an input and setting the associated port output bit to logic 1 (default reset state). Vdd I/O PAD WEAK Vdd MUX PD.x SF DIRECTION SF ENABLE MUX PO.x PIN.x SF OUTPUT PI.x OR SF INPUT MAXQ Figure 6-3. Type C Port Pin Schematic Table 6-1.
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MAXQ Family User’s Guide 6.5 I/O Port Peripheral Registers 6.5.1 Port Output x Register (POx) Bit # 7 6 5 4 3 2 1 0 POx.7 POx.6 POx.5 POx.4 POx.3 POx.2 POx.1 POx.0 Reset (Type A or Type B) 0 0 0 0 0 0 0 0 Reset (Type C or Type D) 1 1 1 1 1 1 1 1 Access rw rw rw rw rw rw rw rw Name r = read, w = write Bits 7 to 0: Port Output x (POx) (POx.[7:0]). This register stores the data that is output on any of the pins of Port x that have been defined as output pins.
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MAXQ Family User’s Guide 6.5.4 (Type A) External Interrupt Enable Register (EIEx) Bit # Name 7 6 5 4 3 2 1 0 IT1 IT0 EX5 EX4 EX3 EX2 EX1 EX0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bit 7: Interrupt 2-5 Edge Select (IT1). This bit selects the edge detection mode for external interrupts 2-5.
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MAXQ Family User’s Guide 6.5.5 (Type A) External Interrupt Flag Register (EIFx) Bit # 7 6 5 4 3 2 1 0 Name — — IE5 IE4 IE3 IE2 IE1 IE0 Reset 0 0 0 0 0 0 0 0 Access r r rw rw rw rw rw rw r = read, w = write Bits 7 and 6: Reserved Bit 5: External Interrupt 5 Flag (IE5). This flag is set when a negative edge (IT1 = 1) or a positive edge (IT1 = 0) is detected on the INT5 pin. This bit remains set until cleared in software.
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MAXQ Family User’s Guide Bit 3: Enable External Interrupt 3 (EX3) 0 = external interrupt 3 function disabled 1 = external interrupt 3 function enabled Bit 2: Enable External Interrupt 2 (EX2) 0 = external interrupt 2 function disabled 1 = external interrupt 2 function enabled Bit 1: Enable External Interrupt 1 (EX1) 0 = external interrupt 1 function disabled 1 = external interrupt 1 function enabled Bit 0: Enable External Interrupt 0 (EX0) 0 = external interrupt 0 function disabled 1 = external interrupt 0
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MAXQ Family User’s Guide 6.5.8 (Type D) External Interrupt Edge Select Register (EIESx) Bit # 7 6 5 4 3 2 1 0 Name IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bit 7: Interrupt 7 Edge Select (IT7). This bit selects the edge detection mode for external interrupt 7. 0 = INT7 is positive-edge triggered 1 = INT7 is negative-edge triggered Bit 6: Interrupt 6 Edge Select (IT6).
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MAXQ Family User’s Guide SECTION 7: TIMER/COUNTER 0 MODULE This section contains the following information: 7.1 Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2 7.1.1 Timer 0 Mode: 13-Bit Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2 7.1.2 Timer 0 Mode: 16-Bit Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.1.
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MAXQ Family User’s Guide SECTION 7: TIMER/COUNTER 0 MODULE The Timer/Counter 0 Module allows the MAXQ to control a 16-bit programmable timer/counter. Whether and how many Timer/Counter 0 Modules are implemented in a given MAXQ-based microcontroller is product dependent. 7.1 Timer 0 Timer 0 is the first type of 16-bit timer/counter. Timer 0 consists of a 16-bit register in two bytes, T0H and T0L. Timer 0 is enabled by the Timer 0 Run Control (TR0) bit in the T0CN register.
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MAXQ Family User’s Guide 7.1.2 Timer 0 Mode: 16-Bit Timer/Counter Setting the T0CN register bits M1:M0 = 01b invokes the 16-bit Timer/Counter operating mode. This mode is identical to the 13-bit Timer/Counter mode, except that the T0H:T0L register pair hold a 16-bit value. T0H holds the MSB and T0L holds the LSB. Rollover occurs when the timer reaches FFFFh. An interrupt occurs if enabled and the TF0 (T0CN.5) flag is set.
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MAXQ Family User’s Guide 7.1.4 Timer 0 Mode: Two 8-Bit Timer/Counters When T0CN register bits M1:M0 = 11b, Timer 0 provides two 8-bit timer/counters as shown in Figure 7-3. In this mode, T0L is an 8-bit timer/counter that can be used to count clock cycles or 1-to-0 transitions on pin T0 as determined by C/T. (T0CN.2). As in the other modes, the GATE function can use T0G to give external run control of the timer to an outside signal.
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MAXQ Family User’s Guide 7.2 Timer/Counter 0 Peripheral Registers 7.2.1 Timer/Counter 0 Control Register (T0CN) Bit # Name 7 6 5 4 3 2 1 0 ET0 T0M TF0 TR0 GATE C/T M1 M0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bit 7: Enable Timer 0 Interrupt (ET0). Setting this bit to 1 enables interrupts from the Timer 0 TF0 flag. Clearing this bit to 0 disables the Timer 0 interrupt. Bit 6: Timer 0 Clock Select (T0M).
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MAXQ Family User’s Guide 7.2.2 Timer/Counter 0 High Register (T0H) Bit # 7 6 5 4 3 2 1 0 Name T0H.7 T0H.6 T0H.5 T0H.4 T0H.3 T0H.2 T0H.1 T0H.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bits 7 to 0: Timer/Counter 0 High (T0H.[7:0]). The T0H register is used to load the most significant 8-bit value and least significant 8-bit value of Timer 0. 7.2.3 Timer/Counter 0 Low Register (T0L) Bit # 7 6 5 4 3 2 1 0 Name T0L.7 T0L.6 T0L.
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MAXQ Family User’s Guide SECTION 8: TIMER/COUNTER 1 MODULE This section contains the following information: 8.1 Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 8.1.1 Timer 1 Mode: 16-Bit Timer/Counter with Auto-Reload . . . . . . . . . . . . . . . . . . . . . . . . .8-2 8.1.2 Timer 1 Mode: 16-Bit Event Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 8.1.
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MAXQ Family User’s Guide SECTION 8: TIMER/COUNTER 1 MODULE The Timer/Counter 1 Module allows the MAXQ to control a 16-bit programmable timer/counter. Whether and how many Timer/Counter 1 Modules are implemented in a given MAXQ-based microcontroller is product dependent. 8.1 Timer 1 Timer 1 is the second type of 16-bit timer/counter. Timer 1 consists of a 16-bit register in two bytes, T1H and T1L. Timer 1 is enabled by the Timer 1 Run Control (TR1) bit in the T1CN register.
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MAXQ Family User’s Guide If the C/T1 bit (T1CN.1) is logic 0, the timer’s input clock is a function of the system clock. When C/T1 = 1, pulses on the T1 pin are counted. Counting or timing is enabled or disabled using the with the Timer 1 Run Control bit = TR1 (T1CN.2). This mode, including the optional reload control, is illustrated in Figure 8-1. DIVIDE BY 12 0 T1M = T1MD.0 SYSTEM CLOCK 0 1 C/T1 = T1CN.1 CLK 0 7 8 T1L 15 TF1 = T1CN.7 T1H 1 T1 PIN TR1 = T1CN.
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MAXQ Family User’s Guide 8.1.3 Timer 1 Mode: Up/Down Count with Auto-Reload The up/down count auto-reload option is enabled by the DCEN (T1CN.4) bit. When DCEN is set to logic 1, Timer 1 counts up or down as controlled by the state of T1EX pin. T1EX causes upward counting when a logic 1 is applied and down counting when a logic 0 is applied. When DCEN = 0, Timer 1 only counts up. When an upward counting overflow occurs, the value in T1CH and T1CL loads into T1H and T1L.
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MAXQ Family User’s Guide (T1CN.2) must also be set to logic 1 to enable the timer. The DCEN bit has no effect in this mode. This mode produces a 50% duty cycle square-wave output. The frequency of the square wave is given by the formula in Figure 8-4. Each timer overflow causes an edge transition on the pin, i.e., the state of the pin toggles. Note that the timer itself does not generate an interrupt, but if needed, the Timer 1 external interrupt is still available for use when enabled (EXEN1 = 1). 8.
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MAXQ Family User’s Guide 8.2.2 Timer/Counter 1 High Register (T1H) Bit # 7 6 5 4 3 2 1 0 Name T1H.7 T1H.6 T1H.5 T1H.4 T1H.3 T1H.2 T1H.1 T1H.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bits 7 to 0: Timer/Counter 1 High (T1H.[7:0]). The T1H register is used to load the most significant 8-bit value and least significant 8-bit value of Timer 1. 8.2.3 Timer/Counter 1 Low Register (T1L) Bit # 7 6 5 4 3 2 1 0 Name T1L.7 T1L.6 T1L.
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MAXQ Family User’s Guide 8.2.6 Timer/Counter 1 Mode Register (T1MD) Bit # 7 6 5 4 3 2 1 0 Name — — — — — — ET1 T1M Reset 0 0 0 0 0 0 0 0 Access r r r r r r rw rw r = read, w = write Bits 7 to 2: Reserved Bit 1: Enable Timer 1 Interrupt (ET1). Setting this bit to 1 enables interrupts from the Timer 1 TF1 and EXF1 flags in T1CN. The EXF1 flag does not cause interrupts in the up/down count mode. Bit 0: Timer 1 Clock Select (T1M).
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MAXQ Family User’s Guide SECTION 9: TIMER/COUNTER 2 MODULE This section contains the following information: 9.1 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 9.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 9.2.1 16-Bit Timer: Auto-Reload/Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide 9.3.2 Measure High-Pulse Duration Repeatedly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11 9.3.3 Measure Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12 9.3.4 Measure Duty Cycle Repeatedly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13 9.3.5 Overflow/Interrupt on Cumulative Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide LIST OF FIGURES Figure 9-1. Timer 2 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 Figure 9-2. Output Enable and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 Figure 9-3. Timer 2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9 Figure 9-4. Timer 2 Application Example—Measure Low Pulse Width . .
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MAXQ Family User’s Guide SECTION 9: TIMER/COUNTER 2 MODULE The Timer/Counter 2 Module provides a 16-bit programmable timer/counter with pulse-width modulation capability. Whether and how many Timer 2 Modules are implemented in a given MAXQ-based microcontroller is product dependent.
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MAXQ Family User’s Guide 9.2 Modes of Operation As summarized in Table 9-1, Timer 2 can provide six timer functions. The Timer 2 operating mode selection is illustrated in Figure 9-1 and Figure 9-2 shows the PWM timer output possibilities. T2L COMPARE MATCH T2CL T2CH TR2L T2H:T2L COMPARE MATCH OR T2H COMPARE MATCH T2MD T2L OVERFLOW T2L T2H T2RL T2RH T2CLK T2H:T2L OVERFLOW OR T2H OVERFLOW C/T2 EDGE DETECTION AND GATING T2P PIN INPUT CCF [1:0] G2EN TR2 SS2 T2POL [0] Figure 9-1.
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MAXQ Family User’s Guide 9.2.1 16-Bit Timer: Auto-Reload/Compare The 16-bit auto-reload/compare mode for Timer 2 is in effect when the Timer 2 mode select bit (T2MD) is cleared and the capture/compare function definition bits are both cleared (CCF[1:0] = 00b). The Timer 2 value is contained in the T2V register. The Timer 2 run control bit (TR2) starts and stops the 16-bit Timer. The input clock for 16-bit Timer 2 is defined as the system clock divided by the ratio specified by the T2DIV[2:0] prescale bits.
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MAXQ Family User’s Guide 9.2.1.5 Capture/Reload Control For the 16-bit compare operating mode, the CPRL2 bit is not used. 9.2.2 16-Bit Timer: Capture Mode The 16-bit capture mode requires that some event trigger the capture. Normally this event is an external edge. The CCF[1:0] bits define which edge(s) cause a capture to occur. If CCF[1:0] = 01b, a rising edge causes a capture. If CCF[1:0] = 10b, a falling edge causes a capture. If CCF[1:0] = 11b, rising and falling edges both cause a capture to occur.
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MAXQ Family User’s Guide 9.2.3.1 Output Enable For Timer 2 to serve as a counter, the T2P pin must be used as an input. Thus, when C/T2 = 1, the T2OE[0] bit is ignored. The T2OE[1] bit can be used to output the generated waveform on T2PB resulting from compare match and overflow conditions for the counter.
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MAXQ Family User’s Guide 9.2.5 8-Bit Timer/8-Bit Capture Mode When the CCF[1:0] bits are configured to a state other than 00b, the edge-capture mode is enabled for the primary timer (T2H). The secondary timer (T2L) always remains in the timer/compare mode and does not support any capture functionality. The capture controls for the 8-bit mode are identical to those specified for the 16-bit mode, however they apply only to the upper timer, T2H.
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MAXQ Family User’s Guide 9.3 Timer 2 Capture Application Examples The following examples and accompanying figures (Figures 9-4 through 9-8) are used to demonstrate some of the Timer 2 functions. All examples assume that pulse and/or period measurements do not exceed 216 input clocks and that capture register holds the desired result. 9.3.
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MAXQ Family User’s Guide 9.3.2 Measure High-Pulse Duration Repeatedly To measure the duration of high pulses seen on the T2P input pin repeatedly, Timer 2 could be configured for a single-shot delayed run, gating enabled for logic low, capture on the falling edge. The CPRL2 bit could be set to generate a reload on each falling edge.
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MAXQ Family User’s Guide 9.3.3 Measure Period To measure the period of the signal seen on the T2P input pin, Timer 2 could be configured for a single-shot capture, no gating, either edge (selected by the CCF[1:0] bits). The CPRL2 bit could be set to generate a reload on each capture edge.
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MAXQ Family User’s Guide 9.3.4 Measure Duty Cycle Repeatedly To measure the duty cycle of the signal seen on the T2P input pin, Timer 2 could be configured for a single-shot delayed run with both edges defined for capture. The CPRL2 bits should be configured to 1 to request reloads on each edge. To prevent reloads on one of the edges, gating should be enabled. The T2POL[0] bit specifies which edge starts/ends the capture cycle and which edge does not have a reload associated with it.
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MAXQ Family User’s Guide 9.3.5 Overflow/Interrupt on Cumulative Time To cause an overflow only when the T2P pin has been low for some cumulative duration, Timer 2 could be configured to the gated compare mode of operation with an initial starting value appropriate for the cumulative duration to be detected.
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MAXQ Family User’s Guide 9.4 Timer/Counter 2 Peripheral Registers 9.4.1 Timer/Counter 2 Configuration Register (T2CFG) Bit # Name 7 6 5 4 3 2 1 0 T2CI T2DIV2 T2DIV1 T2DIV0 T2MD CCF1 CCF0 C/T2 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bit 7: Timer 2 Clock Input Select Bit (T2CI). Setting this bit enables an alternate input clock source to the Timer 2 block. The alternate input clock selection is the 32kHz clock.
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MAXQ Family User’s Guide 9.4.2 Timer/Counter 2 Control Register A (T2CNA) Bit # 7 6 5 4 3 2 1 0 Name ET2 T2OE0 T2POL0 TR2L TR2 CPRL2 SS2 G2EN Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bit 7: Enable Timer 2 Interrupts (ET2). This bit serves as the local enable for Timer 2 interrupt sources that fall under the TF2 and TCC2 interrupt flags. Bit 6: Timer 2 Output Enable 0 (T2OE0).
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MAXQ Family User’s Guide Compare Mode: If SS2 is written to 1 while in compare mode, one cycle of the defined waveform (reload to overflow) is output to the T2P, T2PB pins as prescribed by T2POL[1:0] and T2OE[1:0] controls. The only time that this does not immediately occur is when a gating condition is also defined. If a gating condition is defined, the single-shot cycle cannot occur until the gating condition is removed.
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MAXQ Family User’s Guide 9.4.4 Timer 2 Value Register (T2V) Bit # Name 15 14 13 12 11 10 9 8 T2V.15 T2V.14 T2V.13 T2V.12 T2V.11 T2V.10 T2V.9 T2V.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name T2V.7 T2V.6 T2V.5 T2V.4 T2V.3 T2V.2 T2V.1 T2V.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bits 15 to 0: Timer 2 Value (T2V.[15:0]).
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MAXQ Family User’s Guide 9.4.7 Timer 2 Reload High Register (T2RH) Bit # 7 6 5 4 3 2 1 0 Name T2RH.7 T2RH.6 T2RH.5 T2RH.4 T2RH.3 T2RH.2 T2RH.1 T2RH.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bits 7 to 0: Timer 2 Reload High (T2RH.[7:0]). This register is used to load and read the most significant 8-bit reload value in Timer 2. 9.4.8 Timer 2 Capture/Compare Register (T2C) Bit # 15 14 13 12 11 10 9 8 Name T2C.15 T2C.14 T2C.
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MAXQ Family User’s Guide 9.5 Low-Speed Infrared Transmit/Receive Support Using Timer 2 The MAXQ microcontroller can provide hardware to simplify support for low-speed infrared (IR) communication. To take advantage of the embedded hardware, the microcontroller device must be equipped with at least one Timer 2 module; that Timer must have at least two pins implemented and that Timer must be configured to a specific mode of operation.
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MAXQ Family User’s Guide 1 1 0 0 1 DESIRED OUTPUT IRBB BIT (SOFTWARE CONTROLLED) Figure 9-10. Biphase Encoding Example (T2RH Remains Fixed) 9.5.2.1 IR Encoding (Transmit) Example For any encoding scheme, the proper T2L subcarrier generation settings should be established along with the desired T2POL[1] bit state. The T2POL[1] state takes effect once IREN = 1 and IRTX = 1. For biphase encoding, the T2H reload value (T2RH) would be configured to count X subcarrier pulses in one half a bit time.
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MAXQ Family User’s Guide 9.5.2.2 Receive Pin Sampling When IREN = 1 and IRTX = 0, the IR hardware supports the T2H register counting of internal T2L edges just as described for the IR Transmit mode, but the function of the IRBB bit changes. The IRBB bit is used to store the state of the T2P input pin when a compare match occurs between the T2H and T2CH registers.
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MAXQ Family User’s Guide 0 1 0 1 T2P INPUT RELOAD (FALLING) CCF[1:0] = 10b IRBB BIT (T2CH MATCH) Figure 9-14. Bit Length Decoding Example 9.6 IR Peripheral Register 9.6.1 Infrared Control Register (IRCN) Bit # 7 6 5 4 3 2 1 0 Name — — — — — IREN IRTX IRBB Reset 0 0 0 0 0 0 0 0 Access r r r r r rw rw rw r = read, w = write Bits 7 to 3: Reserved Bit 2: Infrared Subcarrier Enable (IREN). This register bit enables a special mode of operation for Timer 2.
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MAXQ Family User’s Guide SECTION 10: SERIAL I/O MODULE This section contains the following information: 10.1 UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 10.1.1 UART Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 10.1.2 UART Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 10: SERIAL I/O MODULE The Serial I/O Module provides the MAXQ access to a universal asynchronous receiver/transmitter (UART) for serial communication with framing error detection. 10.1 UART Modes The UART supports four basic modes of operation, and is capable of both synchronous and asynchronous modes, with different protocols and baud rates.
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MAXQ Family User’s Guide SBUF SYSTEM CLOCK DIVIDE BY 12 0 RXD PIN LATCH S0 D7 D6 D5 D4 D3 D2 D1 D0 LOAD CLOCK OUTPUT SHIFT REGISTER DIVIDE BY 4 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL LOAD SERIAL BUFFER T1 FLAG = SCON.1 RECEIVE DATA BUFFER WR RECEIVE BUFFER DATA CLOCK D7 D6 D5 D4 D3 D2 D1 D0 INTS BAUD CLOCK RD SERIAL I/O CONTROL CLOCK R1 FLAG = SCON.
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MAXQ Family User’s Guide 10.1.2 UART Mode 1 This mode provides asynchronous, full-duplex communication. A total of 10 bits is transmitted, consisting of a start bit (logic 0), 8 data bits, and 1 stop bit (logic 1), as illustrated in Figure 10-2. The data is transferred LSb first. The baud rate is programmable through the baud clock generator. Following a write to SBUF, the UART begins transmission five cycles after the first baud clock from the baud clock generator. Transmission takes place on the TXD pin.
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MAXQ Family User’s Guide SBUF 1 START D7 D6 D5 D4 D3 D2 D1 D0 SYSTEM CLOCK STOP LOAD CLOCK TRANSMIT SHIFT REGISTER TXD PIN LATCH S0 0 DIVIDE BY 4 0 1 DATA BUS SMOD LDSBUF RDSBUF BAUD CLOCK GENERATOR SHIFT LOAD SERIAL BUFFER BAUD CLOCK DIVIDE BY 16 SBUF READ SERIAL BUFFER SERIAL I/O CONTROL RD RECEIVE DATA BUFFER WR LOAD RESET START SI D7 D6 D5 D4 D3 D2 D1 D0 R1 FLAG = SCON.0 START T1 FLAG = SCON.1 CLOCK INTS RB8 = SCON.
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MAXQ Family User’s Guide SBUF START D7 D6 D5 D4 D3 D2 D1 D0 1 DIVIDE BY 2 0 D8 SYSTEM CLOCK/2 STOP LOAD CLOCK TRANSMIT SHIFT REGISTER LATCH S0 TXD PIN 0 TB8 = SCON.3 1 DATA BUS SMOD LDSBUF RDSBUF SHIFT LOAD SERIAL BUFFER SHIFT CLOCK DIVIDE BY 16 SERIAL I/O CONTROL SBUF READ SERIAL BUFFER RD RECEIVE DATA BUFFER WR LOAD RESET D7 D6 D5 D4 D3 D2 D1 D0 START SI D8 R1 FLAG = SCON.0 STOP T1 FLAG = SCON.1 CLOCK INTS RB8 = SCON.
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MAXQ Family User’s Guide 10.1.4 UART Mode 3 This mode has the same operation as Mode 2, except for the baud-rate source. As shown in Figure 10-4, Mode 3 generates baud rates through the baud clock generator. The bit shifting and protocol are the same. SBUF 1 DIVIDE BY 4 0 START D8 D7 D6 D5 D4 D3 D2 D1 D0 SYSTEM CLOCK STOP LOAD CLOCK TRANSMIT SHIFT REGISTER LATCH S0 TXD PIN 0 TB8 = SCON.
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MAXQ Family User’s Guide 10.2 Baud-Rate Generation Each mode of operation has a baud-rate generator associated with it. The baud-rate generation techniques are affected by certain user options such as the Power Management Mode Enable (PMME), Serial Mode 2 (SM2) select bit, and Baud-Rate Doubler (SMOD) bit. Table 10-2 summarizes the effects of the various user options on the UART baud clock. Table 10-2.
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MAXQ Family User’s Guide 15 0 0 PR ADDITION BAUD CLOCK OUTPUT = CARRY OUT FROM PHASE ACCUMULATOR [16] 16 0 PHASE ACCUMULATOR Figure 10-5. Baud-Clock Generator Table 10-3. Example Baud-Clock Generator Settings (SMOD = 1) SYSTEM CLOCK FREQUENCY (MHz) BAUD RATE (PR SETTING) SYSTEM CLOCK FREQUENCY (MHZ) BAUD RATE (PR SETTING) 10 115,200 (5E5F); 57,600 (2F30); 19,200 (0FBB); 9600 (07DD); 2400 (01FF) 3.
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MAXQ Family User’s Guide 10.4 UART Peripheral Registers 10.4.1 Serial Control Register (SCON) Bit # 7 6 5 4 3 2 1 0 Name FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bit 7: Framing Error Flag (FE). (FEDE = 1) This bit is set upon detection of an invalid stop bit. It must be cleared by software. Modification of this bit when FEDE is set has no effect on the serial mode setting.
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MAXQ Family User’s Guide 10.4.2 Serial Port Mode Register (SMD) Bit # 7 6 5 4 3 2 1 0 Name — — — — — ESI SMOD FEDE Reset 0 0 0 0 0 0 0 0 Access r r r r r rw rw rw r = read, w = write Bits 7 to 3: Reserved Bit 2: Framing Error Detection Enable (FEDE). This bit selects the function of SM0 (SCON.7): 0 = SCON.7 functions as SM0 for serial port mode selection 1 = SCON.7 is converted to the Framing Error (FE) flag Bit 1: Serial Port Baud Rate Select (SMOD).
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MAXQ Family User’s Guide SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE This section contains the following information: 11.1 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 11.2 SPI Character Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 11.3 SPI Transfer Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE The serial peripheral interface (SPI) module of the MAXQ microcontroller provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a four-wire full-duplex serial bus that can be operated in either master mode or slave mode.
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MAXQ Family User’s Guide 11.1 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received over two serial data lines with respect to a single serial shift clock. The polarity and phase of the serial shift clock are the primary components in defining the SPI data transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and therefore also defines which clock edge is the active edge.
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MAXQ Family User’s Guide 11.3 SPI Transfer Baud Rates When operating as a slave device, an external master drives the SPI serial clock. For proper slave operation, the serial clock provided by the external master should not exceed the system clock frequency divided by 8. When operating in the master mode, the SPI serial clock is sourced to the external slave device(s). The serial clock baud rate is determined by the clock-divide ratio specified in the SPI Clock Divider Ratio (SPICK) register.
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MAXQ Family User’s Guide 11.4.3 Write Collision While Busy A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY = 1). Since the shift register is single buffered in the transmit direction, writes to SPIB are made directly into the shift register. Allowing the write to SPIB while another transfer is in progress could easily corrupt the transmit/receive data.
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MAXQ Family User’s Guide 11.7 SPI Peripheral Registers 11.7.1 SPI Control Register (SPICN) Bit # 7 6 5 4 3 2 1 0 Name STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN Reset 0 0 0 0 0 0 0 0 Access r rw rw rw rw rw rw rw r = read, w = write Bit 7: SPI Transfer Busy Flag (STBY). This bit is used to indicate the current transmit/receive activity of the SPI module. STBY is set to 1 when an SPI transfer cycle starts and is cleared to 0 when the transfer cycle is completed.
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MAXQ Family User’s Guide Bit 0: SPI Enable (SPIEN) 0 = SPI module and its baud-rate generator are disabled 1 = SPI module and its baud-rate generator are enabled 11.7.2 SPI Configuration Register (SPICF) Bit # 7 6 5 4 3 2 1 0 Name ESPII — — — — CHR CKPHA CKPOL Reset 0 0 0 0 0 0 0 0 Access rw r r r r rw rw rw r = read, w = write Bit 7: SPI Interrupt Enable (ESPII).
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MAXQ Family User’s Guide 11.7.4 SPI Data Buffer Register (SPIB) Bit # Name 15 14 13 12 11 10 9 8 SPIB.15 SPIB.14 SPIB.13 SPIB.12 SPIB.11 SPIB.10 SPIB.9 SPIB.8 Reset 0 0 0 0 0 0 0 0 Access rs rs rs rs rs rs rs rs Bit # Name 7 6 5 4 3 2 1 0 SPIB.7 SPIB.6 SPIB.5 SPIB.4 SPIB.3 SPIB.2 SPIB.1 SPIB.0 Reset 0 0 0 0 0 0 0 0 Access rs rs rs rs rs rs rs rs r = read, s = special Bits 15 to 0: SPI Data Buffer (SPIB.[15:0]).
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MAXQ Family User’s Guide SECTION 12: HARDWARE MULTIPLIER MODULE This section contains the following information: 12.1 Hardware Multiplier Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2 12.2 Hardware Multiplier Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3 12.3 Register Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 12: HARDWARE MULTIPLIER MODULE The hardware multiplier module can be used by the MAXQ microcontroller to support high-speed multiplications. The hardware multiplier module is equipped with two 16-bit operand registers, a 32-bit read-only result register, and an accumulator of width between 32 bits and 48 bits, depending on the specific MAXQ device. The multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle.
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MAXQ Family User’s Guide 12.2 Hardware Multiplier Controls The selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register: SUS, MSUB, MMAC, and SQU. The number of operands that must be loaded to trigger the specified operation is dictated by the OPCS bit setting, except when the square function is enabled (SQU = 1).
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MAXQ Family User’s Guide 12.4.1 Accessing the Multiplier There are no restrictions on how quickly data is entered into the operand registers or the order of data entry. The only requirement to do a calculation is to perform the loading of MA and/or MB registers having specified data type and operation in the MCNT register. The multiplier keeps track of the writes to the MA and MB registers, and starts calculation immediately after the prescribed number of operands is loaded.
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MAXQ Family User’s Guide Bit 4: Square Function Enable (SQU). This bit supports the hardware square function. When this bit is set to logic 1, a square operation is initiated after an operand is written to either the MA or the MB register. Writing data to either of the operand registers writes to both registers and triggers the specified square or square-accumulate/subtract operation. Setting this bit to 1 also overrides the OPCS bit setting.
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MAXQ Family User’s Guide 12.5.3 Multiplier Operand B Register (MB) Bit # 15 14 13 12 11 10 9 8 Name MB.15 MB.14 MB.13 MB.12 MB.11 MB.10 MB.9 MB.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name MB.7 MB.6 MB.5 MB.4 MB.3 MB.2 MB.1 MB.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bits 15 to 0: Multiplier Operand B Register (MB.[15:0]).
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MAXQ Family User’s Guide 12.5.5 Multiplier Accumulator 1 Register (MC1) Bit # 15 14 13 12 11 10 9 8 Name MC1.15 MC1.14 MC1.13 MC1.12 MC1.11 MC1.10 MC1.9 MC1.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # Name 7 6 5 4 3 2 1 0 MC1.7 MC1.6 MC1.5 MC1.4 MC1.3 MC1.2 MC1.1 MC1.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bits 15 to 0: Multiplier Accumulator 1 Register (MC1.[15:0]).
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MAXQ Family User’s Guide 12.5.7 Multiplier Read Register 1 (MC1R) Bit # 15 14 13 12 11 10 9 8 Name MC1R.15 MC1R.14 MC1R.13 MC1R.12 MC1R.11 MC1R.10 MC1R.9 MC1R.8 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name MC1R.7 MC1R.6 MC1R.5 MC1R.4 MC1R.3 MC1R.2 MC1R.1 MC1R.0 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r r = read Bits 15 to 0: Multiplier Read Register 1 (MC1R.[15:0]).
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MAXQ Family User’s Guide 12.6 Hardware Multiplier Examples The following are code examples of multiplier operations.
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MAXQ Family User’s Guide SECTION 13: 1-Wire BUS MASTER This section contains the following information: 13.1 1-Wire Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.1.1 1-Wire Address Register (OWA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.1.2 1-Wire Data Register (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.
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MAXQ Family User’s Guide SECTION 13: 1-Wire BUS MASTER The 1-Wire Bus Master can be used by the MAXQ microcontroller to support 1-Wire communication to external 1-Wire devices without tying up valuable CPU resources. The Bus Master provides complete control of the 1-Wire bus, and transmit and receive activities. All timing and control sequences of the 1-Wire bus are generated within the Bus Master.
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MAXQ Family User’s Guide 13.1 1-Wire Peripheral Registers The MAXQ microcontroller interfaces to the 1-Wire Bus Master through two peripheral registers: 1-Wire Master Address (OWA) and 1-Wire Master Data (OWD). These two registers allow read/write access of the six internal registers of the 1-Wire Bus Master. The internal registers provide a means for the CPU to configure and control transmit/receive activity through the Bus Master.
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MAXQ Family User’s Guide 13.2 1-Wire Clock Control All 1-Wire timing patterns are generated using a base clock of 1.0MHz. To create this base clock frequency, the 1-Wire Bus Master must internally divide down the microcontroller system clock. The Clock Divisor internal register implements bits to control this clock division. The prescaler bits (PRE[1:0]) divide the microcontroller system clock by 1, 3, 5, or 7 for settings of 00b, 01b, 10b, and 11b, respectively.
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MAXQ Family User’s Guide 13.3 1-Wire Bus Master Control The 1-Wire Bus Master can perform certain special functions to support OW line operation. These special functions can be set up through the Control register that is documented below. The Control Register defaults to 00h on a reset, which disables all special functions. 13.3.
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MAXQ Family User’s Guide 13.4 1-Wire Bus Master Commands The 1-Wire Bus Master can generate special commands on the 1-Wire bus in addition to transmitting and receiving data. The commands are generated via the setting of a corresponding bit in the Command Register (A[2:0] = 000b), which is documented below. These operational modes are defined in the Book of iButton Standards. 13.4.
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MAXQ Family User’s Guide Table 13-2. ROM ID Read Time Slot Possibilities READ TIME SLOT 1 (SLAVE) READ TIME SLOT 2 (SLAVE) WRITE TIME SLOT (MASTER) 0 1 1 0 0 1 0 0 0 or 1 1 1 1 DESCRIPTION All slave devices remaining in the selection process have a 0 in this ROM ID bit position. All slave devices remaining in the selection process have a 1 in this ROM ID bit position. ID Discrepancy—Slave devices remaining in the selection process have both 0 and 1 in this ROM ID bit position.
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MAXQ Family User’s Guide 13.5.1 Accelerated ROM Search Example The following example should provide a better understanding of how the Search ROM Accelerator functionality allows the 1-Wire Master to identify four different devices on the 1-Wire bus with ROM IDs as shown (least significant bit first): ROM1 = 00110101.... ROM2 = 10101010.... ROM3 = 11110101.... ROM4 = 00010001.... 1) The host issues a reset pulse by writing 01h to the Command Register.
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MAXQ Family User’s Guide 13.6 1-Wire Transmit and Receive Operations All data transmitted and received by the 1-Wire Bus Master passes through the transmit/receive data buffer (internal register address A[2:0] = 001b). The data buffer combination for the transmit interface is composed of the Transmit Buffer and Transmit Shift Register. Each of these registers has a flag that can be used as an interrupt source.
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MAXQ Family User’s Guide 13.7 1-Wire Bus Master Interrupts The 1-Wire Bus Master can be configured to generate an interrupt request to the CPU on the occurrence of a number of 1-Wire related events or conditions. These include the following: Presence Detect, Transmit Buffer Empty, Transmit Shift Register Empty, Receive Buffer Full, Receive Shift Register Full, 1-Wire Short, and 1-Wire Low. Each of these potential 1-Wire interrupt sources has a corresponding enable bit and flag bit.
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MAXQ Family User’s Guide 13.7.2 1-Wire Interrupt Enable Register (OWA = 011b) Bit # 7 6 5 4 3 2 1 0 Name EOWL EOWSH ERSF ERBF ETMT ETBE — EPD Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw r rw r = read, w = write Bit 7: Enable 1-Wire Low Interrupt (EOWL). Setting this bit to logic 1 enables the 1-Wire low interrupt. If both EOWMI and EOWL are set, OWMI is asserted when OW_LOW flag is set. Clearing this bit disables OW_LOW as an active interrupt source.
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MAXQ Family User’s Guide INITIALIZATION SEQUENCE tRSTH tRSTL tPDH tPDL VDD OWOUT GND tPDS WRITE TIME SLOT tWRITE 1 SLOT tWRITE 0 SLOT tLOW0 tLOW1 >1µs VDD OWOUT GND 15µs 15µs 30µs 15µs 15µs SLAVE SAMPLING 30µs SLAVE SAMPLING READ TIME SLOT tREAD 0 SLOT tREAD 1 SLOT VDD OWIN GND 1µs 1µs tRDV BUS MASTER SAMPLING tRDV MASTER ACTIVE LOW MASTER AND SLAVE ACTIVE LOW SLAVE ACTIVE LOW RESISTOR PULLUP BUS MASTER SAMPLING Figure 13-2.
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MAXQ Family User’s Guide SECTION 14: REAL-TIME CLOCK MODULE This section contains the following information: 14.1 RTC Alarm Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3 14.1.1 Time-of-Day Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3 14.1.2 Sub-Second Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 14: REAL-TIME CLOCK MODULE The real-time clock (RTC) is a binary timer that keeps the time of day and provides time-of-day and sub-second alarm functionality in the form of system interrupts. The RTC consists of cascaded 32-bit and 8-bit ripple counters that respectively represent absolute seconds (~136 years) and sub-seconds (in 1/256 second resolution). The 8-bit sub-second counter increments with each 256Hz clock tick derived from the 32.768kHz oscillator.
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MAXQ Family User’s Guide 14.1 RTC Alarm Functions The RTC provides time-of-day and sub-second interval alarm functions. The time-of-day alarm, when enabled, occurs based upon matching of the least significant 20 bits of the RTC seconds counter information (RTSH:RTSL) with the least significant 20 bits of the alarm register values (RASH:RASL) defined by the user. The sub-second interval alarm provides an auto-reload timer that is driven by the untrimmed 256Hz clock source. 14.1.
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MAXQ Family User’s Guide 256Hz MUX 256Hz 512Hz TSGN VALID FOR ONE 256Hz CYCLE EVERY 16SEC. THEN CLEARED TO 0. CARRY-OUT 5-BIT PHASE ACCUMULATOR 16-SECOND CLOCK TRM4:0 Figure 14-2. RTC Digital-Trim Facility Block Diagram 16SEC CLOCK 256Hz CLOCK 512Hz CLOCK ACCUMULATOR CARRY-OUT (CO) 256Hz MUX SELECT 1 1 POSITIVE CAL (S = 0) 256Hz OUTPUT POSITIVE CAL (S = 0) 128Hz OUTPUT NEGATIVE CAL (S = 1) 256Hz OUTPUT NEGATIVE CAL (S = 1) 128Hz OUTPUT Figure 14-3.
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MAXQ Family User’s Guide 14.3 RTC Register Access Since RTC registers and register bits must be used in the 32kHz clock domain and also be accessible in the system clock domain, a handshaking or signaling protocol is implemented to simplify user access. 14.3.1 Busy Bit Write Signaling The BUSY bit of the RTC Control (RCNT) register is a read-only status bit.
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MAXQ Family User’s Guide 14.4 RTC Peripheral Registers 14.4.
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MAXQ Family User’s Guide Bit 3: RTC Busy (BUSY). This bit is set to 1 by hardware when any of the following conditions occur: 1) system reset, 2) software writes to RTC count registers, or 3) software changes RTCE, ASE, or ADE. For conditions 2 and 3, the write or change should not be considered complete until hardware clears the BUSY bit. This is an indication that 32kHz synchronized version of the register bit(s) is in place. Bit 2: Alarm Sub-Second Enable (ASE).
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MAXQ Family User’s Guide 14.4.3 RTC Seconds Low Register (RTSL) Bit # Name 15 14 13 12 11 10 9 8 RTSL.15 RTSL.14 RTSL.13 RTSL.12 RTSL.11 RTSL.10 RTSL.9 RTSL.8 Power-On Reset 0 0 0 0 0 0 0 0 Reset u u u u u u u u Access s s s s s s s s Bit # 7 6 5 4 3 2 1 0 RTSL.7 RTSL.6 RTSL.5 RTSL.4 RTSL.3 RTSL.2 RTSL.1 RTSL.
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MAXQ Family User’s Guide 14.4.5 RTC Alarm Seconds High Register (RASH) Bit # 7 6 5 4 3 2 1 0 Name — — — — RASH.3 RASH.2 RASH.1 RASH.0 Reset 0 0 0 0 0 0 0 0 Access r r r r rs rs rs rs r = read, s = special Bits 7 to 4: Reserved Bits 3 to 0: RTC Alarm Seconds High (RASH.[3:0]). This register contains the most significant bits for the 20-bit time-of-day alarm. The time-of-day alarm is formed by the RASH and the RASL registers.
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MAXQ Family User’s Guide 14.4.7 RTC Sub-Second Alarm Register (RSSA) Bit # 15 14 13 12 11 10 9 8 Name RSSA.15 RSSA.14 RSSA.13 RSSA.12 RSSA.11 RSSA.10 RSSA.9 RSSA.8 Reset 0 0 0 0 0 0 0 0 Access rs rs rs rs rs rs rs rs Bit # 7 6 5 4 3 2 1 0 Name RSSA.7 RSSA.6 RSSA.5 RSSA.4 RSSA.3 RSSA.2 RSSA.1 RSSA.0 Reset 0 0 0 0 0 0 0 0 Access rs rs rs rs rs rs rs rs r = read, s = special Bits 15 to 0: RTC Sub-Second Alarm (RSSA.[15:0]).
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MAXQ Family User’s Guide SECTION 15: TEST ACCESS PORT (TAP) This section contains the following information: 15.1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-2 15.2 TAP State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-2 15.2.1 Test-Logic-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 15: TEST ACCESS PORT (TAP) The MAXQ microcontroller incorporates a Test Access Port (TAP) and TAP controller for communication with a host device across a 4-wire synchronous serial interface. The TAP can be used by MAXQ microcontrollers to support in-system programming and/or in-circuit debug. The TAP is compatible with the JTAG IEEE standard 1149, and is formed by four interface signals, as described in the following table.
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MAXQ Family User’s Guide TEST-LOGIC-RESET 1 0 RUN-TEST-IDLE 1 1 1 SELECT-DR-SCAN 0 SELECT-IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 0 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 UPDATE-IR 0 1 0 Figure 15-1. TAP Controller State Diagram 15.2.3 IR-Scan Sequence The controller state sequence allows instructions (e.g.
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MAXQ Family User’s Guide When the parallel instruction register (IR2:0) is updated, the TAP controller decodes the instruction and performs any necessary operations, including activation of the data shift register to be used for the particular instruction during data register shift sequences (DRScan). The length of the activated shift register depends upon the value loaded to the instruction register (IR2:0).
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MAXQ Family User’s Guide READ WRITE 7 6 5 4 3 2 1 0 s1 s0 DEBUG VDD 2 SYSTEM PROGRAM 1 0 BY-PASS TDO TDI VDD INSTRUCTION REGISTER 2 1 0 TMS TAP CONTROLLER TCK POWER-ON RESET UPDATE-DR UPDATE-DR Figure 15-2. TAP and TAP Controller 15.3 Communication via TAP The TAP controller is in Test-Logic-Reset state after a power-on-reset.
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MAXQ Family User’s Guide TCK TMS RUN-TEST/IDLE UPDATE-IR EXIT1-IR SHIFT-IR EXIT2-IR PAUSE-IR EXIT1-IR SHIFT-IR CAPTURE-IR SELECT-IR-SCAN SELECT-DR-SCAN RUN-TEST/IDLE TEST-LOGIC-RESET CONTROL STATE TDI IR SHIFT REGISTER DON'T CARE OR UNDEFINED IR PARALLEL OUTPUT REGISTER SELECTED DON'T CARE OR UNDEFINED NEW INSTRUCTION BY-PASS DON'T CARE OR UNDEFINED INSTRUCTION REGISTER DON'T CARE OR UNDEFINED TDO ENABLE TDO Figure 15-3.
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MAXQ Family User’s Guide TCK TMS TEST-LOGIC-RESET SELECT-IR-SCAN SELECT-DR-SCAN RUN-TEST/IDLE UPDATE-DR EXIT1-DR SHIFT-DR EXIT2-DR PAUSE-DR EXIT1-DR SHIFT-DR CAPTURE-DR SELECT-DR-SCAN RUN-TEST/IDLE CONTROL STATE TDI SHIFT REGISTER PARALLEL OUTPUT DON'T CARE OR UNDEFINED DON'T CARE OR UNDEFINED NEW DATA OLD DATA INSTRUCTION REGISTER DATA REGISTER DON'T CARE OR UNDEFINED TDO ENABLE TDO Figure 15-4.
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MAXQ Family User’s Guide SECTION 16: IN-CIRCUIT DEBUG MODE This section contains the following information: 16.1 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3 16.1.1 Breakpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-5 16.1.1.1 Breakpoint 0 Register (BP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-5 16.1.1.
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MAXQ Family User’s Guide SECTION 16: IN-CIRCUIT DEBUG MODE Most MAXQ microcontroller devices are equipped with embedded debug hardware and embedded ROM firmware developed for the purpose of providing in-circuit debugging capability to the user application. The in-circuit debug mode uses the JTAG-compatible TAP as its means of communication between the host and MAXQ microcontroller. Figure 16-1 shows a block diagram of the in-circuit debugger.
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MAXQ Family User’s Guide The host now can transmit and receive serial data through the 10-bit data shift register that exists between the TDI input and TDO output during DR-Scan sequences. All background and debug mode communication (commands, data input/output, and status) occurs via this serial channel. Each 10-bit exchange of data between the host and the MAXQ internal hardware is composed of two status bits and a single byte of command or data.
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MAXQ Family User’s Guide Table 16-1 shows the background mode commands supported by the MAXQ microcontroller. Encodings not listed in this table are not supported in background mode and are treated as no operations. Table 16-1. Background Mode Commands OP CODE 0000-0000 COMMAND No Operation 0000-0001 Read ICDC Read Control Data from the ICDC. The contents of the ICDC register are loaded into the Debug Shift Register via the ICDB register for host read.
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MAXQ Family User’s Guide 16.1.1 Breakpoint Registers The MAXQ microcontroller incorporates six breakpoint registers (BP0-BP5) that are configurable by the host for establishing different types of breakpoint mechanisms. The first four breakpoint registers (BP0-BP3) are 16-bit registers that are configurable as program memory address breakpoints. When enabled, the debug engine will force a break when a match between the breakpoint register and the program memory execution address occurs.
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MAXQ Family User’s Guide 16.1.1.3 Breakpoint 2 Register (BP2) Bit # 15 14 13 12 11 10 9 8 Name BP2.15 BP2.14 BP2.13 BP2.12 BP2.11 BP2.10 BP2.9 BP2.8 Reset 1 1 1 1 1 1 1 1 Access s s s s s s s s Bit # 7 6 5 4 3 2 1 0 Name BP2.7 BP2.6 BP2.5 BP2.4 BP2.3 BP2.2 BP2.1 BP2.0 Reset 1 1 1 1 1 1 1 1 Access s s s s s s s S s = special Bits 15 to 0: Breakpoint 2 (BP2.[15:0]).
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MAXQ Family User’s Guide 16.1.1.5 Breakpoint 4 Register (BP4) (REGE = 0) Bit # 15 14 13 12 11 10 9 8 BP4.15 BP4.14 BP4.13 BP4.12 BP4.11 BP4.10 BP4.9 BP4.8 Reset 1 1 1 1 1 1 1 1 Access s s s s s s s s* Bit # 7 6 5 4 3 2 1 0 BP4.7 BP4.6 BP4.5 BP4.4 BP4.3 BP4.2 BP4.1 BP4.
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MAXQ Family User’s Guide 16.1.1.7 Breakpoint 5 Register (BP5) (REGE = 0) Bit # 15 14 13 12 11 10 9 8 BP5.15 BP5.14 BP5.13 BP5.12 BP5.11 BP5.10 BP5.9 BP5.8 Reset 1 1 1 1 1 1 1 1 Access s s s s s s s s* Bit # 7 6 5 4 3 2 1 0 BP5.7 BP5.6 BP5.5 BP5.4 BP5.3 BP5.2 BP5.1 BP5.
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MAXQ Family User’s Guide 16.1.2 Using Breakpoints All breakpoint registers (BP0-BP5) default to the FFFFh state on power-on reset or when the Test-Logic-Reset TAP state is entered. The breakpoint registers are accessible only with Background mode read/write commands issued over the TAP communication link. The breakpoint registers are not read/write accessible to the CPU.
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MAXQ Family User’s Guide 16.2.1 Debug Mode Commands The debug engine sets the data shift register status bits to 01b (debug-idle) to indicate that it is ready to accept debug commands from the host.
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MAXQ Family User’s Guide Table 16-2. Debug Mode Commands OP CODE COMMAND 0010-0000 No Operation OPERATION No Operation Read Register Map Read Data from Internal Registers. This command forces the debug engine to update the CMD3:0 bits in the ICDC to 0001b and perform a jump to ROM code at x8010h.
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MAXQ Family User’s Guide 16.2.2 Read Register Map Command Host-ROM Interaction A read register map command reads out data contents for all implemented system and peripheral registers. The host does not specify a target register but instead should expect register data output in successive order, starting with the lowest order register in register module 0. Data is loaded by the ROM to the 8-bit ICDB register and is output one byte per transfer cycle.
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MAXQ Family User’s Guide allows user code to configure breakpoints that occur inside PMM, thus providing reliable use of debug commands. However, it does not allow a good means for re-entering PMM. • Special caution should be exercised when using the Write Register command on register bits that globally affect system operation (e.g., IGE, STOP).
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MAXQ Family User’s Guide 16.3.2 In-Circuit Debug Temp 1 Register (ICDT1) Bit # 15 14 13 12 11 10 9 8 Name ICDT1.15 ICDT1.14 ICDT1.13 ICDT1.12 ICDT1.11 ICDT1.10 ICDT1.9 ICDT1.8 Reset 0 0 0 0 0 0 0 0 Access s s s s s s s s Bit # 7 6 5 4 3 2 1 0 Name ICDT1.7 ICDT1.6 ICDT1.5 ICDT1.4 ICDT1.3 ICDT1.2 ICDT1.1 ICDT1.0 Reset 0 0 0 0 0 0 0 0 Access s s s s s s s s s = special Bits 15 to 0: In-Circuit Debug Temp 1 (ICDT1.[15:0]).
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MAXQ Family User’s Guide 16.3.4 In-Circuit Debug Flag Register (ICDF) Bit # 7 6 5 4 3 2 1 0 Name — — — — PSS1 PSS0 SPE TXC Reset 0 0 0 0 0 0 0 0 Access r r r r rw rw rw rw r = read, w = write Bits 7 to 4: Reserved Bits 3 to 2: Programming Source Select Bits 1:0 (PSS[1:0]). These bits are used to select a programming interface during In-System programming when SPE is set to logic 1. Otherwise, the logic values of these bits have no meaning.
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MAXQ Family User’s Guide 16.3.6 In-Circuit Debug Data Register (ICDD) Bit # 15 14 13 12 11 10 9 8 Name ICDD.15 ICDD.14 ICDD.13 ICDD.12 ICDD.11 ICDD.10 ICDD.9 ICDD.8 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name ICDD.7 ICDD.6 ICDD.5 ICDD.4 ICDD.3 ICDD.2 ICDD.1 ICDD.0 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r r = read Bits 15 to 0: In-Circuit Debug Data (ICDD.[15:0]).
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MAXQ Family User’s Guide SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) This section contains the following information: 17.1 JTAG Bootloader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2 17.2 Password-Protected Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3 17.2.1 Entering Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) Internal nonvolatile memory of MAXQ microcontrollers can be initialized via Bootstrap Loader mode. To enable the Bootstrap loader and establish a desired communication channel, the System Programming instruction (100b) must be loaded into the TAP instruction register using the IR-Scan sequence.
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MAXQ Family User’s Guide 17.2 Password-Protected Access Some applications require preventative measures to protect against simple access and viewing of program code memory. To address this need for code protection, any MAXQ microcontroller equipped with a Utility ROM that permits in-system programming, in-application programming, or in-circuit debugging grants full access to those utilities only after a password has been supplied.
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MAXQ Family User’s Guide SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY This section contains the following information: ADD/ADDC src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-5 AND src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-6 AND Acc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide RL/RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-26 RR/RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-28 SLA/SLA2/SLA4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-30 SR/SRA/SRA2/SRA4 . . . . . . . . . .
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MAXQ Family User’s Guide SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY Table 18-1. Instruction Set Summary MATH BIT OPERATIONS LOGICAL OPERATIONS MNEMONIC 18-3 AND src OR src XOR src CPL NEG SLA SLA2 SLA4 RL RLC SRA SRA2 SRA4 SR RR RRC MOVE C, Acc. MOVE C, #0 MOVE C, #1 CPL C MOVE Acc., C AND Acc. OR Acc. XOR Acc. MOVE dst., #1 MOVE dst., #0 MOVE C, src.
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MAXQ Family User’s Guide Table 18-1.
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MAXQ Family User’s Guide ADD/ADDC src Add/Add with Carry Description: The ADD instruction sums the active accumulator (Acc or A[AP]) and the specified src data and stores the result back to the active accumulator. The ADDC instruction additionally includes the Carry (C) Status Flag in the summation. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ20 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ Family User’s Guide MAXQ20 Example(s): ; Acc = 2345h for each example ADDC A[3] ; A[3] = DCBAh, C=1 ; → Acc = 0000h, C=1, Z=1, S=0, OV=0 ADDC @DP[0]-- ; @DP[0] = 00EEh, C=1 ; → Acc = 2434h, C=0, Z=0, S=0, OV=0 Special Notes: The active accumulator (Acc) is not allowed as the src for these operations. AND src Logical AND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction.
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MAXQ Family User’s Guide AND Acc. Logical AND Carry Flag with Accumulator Bit Description: Performs a logical-AND between the Carry (C) status flag and a specified bit of the active accumulator (Acc.) and returns the result to the Carry. Status Flags: C Operation: C ← C AND Acc. Encoding: 15 1001 0 1010 MAXQ10 Example(s): 18-7 1010 ; Acc = 45h, C=1 at start AND Acc.0 ; Acc.0=1 → C=1 AND Acc.1 ; Acc.1=0 → C=0 AND Acc.2 ; Acc.
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MAXQ Family User’s Guide {L/S}CALL src {Long/Short} Call to Subroutine Description: Performs a call to the subroutine destination specified by src. The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words). The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute long CALL.
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MAXQ Family User’s Guide CMP src Compare Accumulator Description: Compare for equality between the active accumulator and the least significant byte of the specified src. The MAXQ20 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ Family User’s Guide CPL C Complement Carry Flag Description: Logically complements the Carry (C) Flag. Status Flags: C Operation: C ← ~C Encoding: 15 1101 0 1010 Example(s): 0010 1010 ;C=0 ;C←1 CPL C {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Description: The DJNZ LC[n], src instruction performs a conditional branch based upon the associated Loop Counter (LC[n]) register.
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MAXQ Family User’s Guide {L/S} JUMP src Unconditional {Long/Short} Jump Description: Performs an unconditional jump as determined by the src specifier. The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words). The JUMP instruction uses a 16-bit immediate src to perform an absolute JUMP to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute JUMP. Using the optional 'L' prefix (i.e.
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MAXQ Family User’s Guide Conditional {Long/Short} Jump on Status Flag {L/S}JUMP C/{L/S}JUMP NC, src, L/S}JUMP Z/{L/S}JUMP NZ, src, {{L/S}JUMP E/{L/S}JUMP NE, src, {L/S}JUMP S, src Description: Performs conditional branching based upon the state of a specific processor status flag. JUMP C results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear. JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear.
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MAXQ Family User’s Guide JUMP NZ Z=0: IP ← IP + src (relative) -or- src (absolute) Operation: Z=1: IP ← IP + 1 Encoding: 15 f101 0 1100 ssss ssss Example(s): JUMP NZ, label1 JUMP E E=1: IP ← IP + src (relative) -or- src (absolute) Operation: E=0: IP ← IP + 1 Encoding: 15 0011 ; Z=1, branch taken 0 1100 ssss ssss Example(s): JUMP E, label1 Special Notes: The src specifier must be immediate data.
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MAXQ Family User’s Guide MOVE dst, src Move Data Description: Moves data from a specified source (src) to a specified destination (dst). A list of defined source, destination specifiers is given in the table below. Also, since src can be either 8-bit (byte) or 16-bit (word) data, the rules governing data transfer are also explained below in the encoding section.
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MAXQ Family User’s Guide MOVE dst, src (continued) Move Data Table 18-3. Destination Specifier Codes dst dst Bit Encoding (ddd dddd) WIDTH (16 OR 8) NUL 111 0110 8/16 Null (Virtual) Destination. Intended as a bit bucket to assist software with pointer increments/decrements. MN[n] nnn 0NNN 8/16 nnnn Selects One of First 8 Registers in Module NNN; where NNN= 0 to 5. Access to Next 24 Using PFX[n].
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MAXQ Family User’s Guide Example(s): MOVE A[0], A[3] MOVE DP[0], #110h ; A[0] ← A[3] ; DP[0] ← #0110h (PFX[0] register used) ; MOVE PFX[0], #01h (smart-prefixing) ; MOVE DP[0], #10h MOVE DP[0], #80h Special Notes: ; DP[0] ← #0080h (PFX[0] register not needed) Proper loading of the PFX[n] registers, when for the purpose of supplying 16-bit immediate data or accessing 2-cycle destinations, is handled automatically by the assembler and is therefore an optional step for the user when writing assembly sour
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MAXQ Family User’s Guide MOVE C, Acc. Move Accumulator Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified active accumulator bit. Status Flags: C Operation: C ← Acc. Encoding: 15 1110 0 1010 bbbb MAXQ010 Example(s): ; Acc = 01h, C=0 MOVE C, Acc.0 ; C =1 MAXQ020 Example(s): ; Acc = 01C0h, C=0 MOVE C, Acc.8 Special Notes: 1010 ; C =1 For the MAXQ10, the accumulator width is only 8 bits.
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MAXQ Family User’s Guide MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag. Status Flag: C←1 Operation: C←1 Encoding: 15 1101 0 1010 0001 Example(s): 1010 ;C=0 ;C←1 MOVE C, #1 MOVE dst., #0 Clear Bit Description: Clears the bit specified by dst.. Status Flags: C, E (if dst is PSF), S, Z Operation: dst. ← 0 Encoding: 15 1ddd 0 dddd 0bbb Example(s): Special Notes: 0111 ; M0[0] = FEh MOVE M0[0].1, #0 ; M0[0] = FCh MOVE M0[0].
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MAXQ Family User’s Guide NEG Negate Accumulator Description: Performs a negation (two's complement) of the active accumulator and returns the result back to the active accumulator.
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MAXQ Family User’s Guide OR Acc. Logical OR Carry Flag with Accumulator Bit Description: Performs a logical-OR between the Carry (C) status flag and a specified bit of the active accumulator (Acc.) and returns the result to the Carry. Status Flags: C Operation: C ← C OR Acc. Encoding: 15 1010 0 1010 bbbb MAXQ10 Example(s): ; Acc = 45h, C=0 at start OR Acc.1 ; Acc.1=0 → C=0 OR Acc.2 ; Acc.2=1 → C=1 MAXQ20 Example(s): Special Notes: 1010 ; Acc = 2345h, C=0 at start OR Acc.
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MAXQ Family User’s Guide POPI dst Pop Word from the Stack Enable Interrupts Description: Pops a single word from the stack (@SP) to the specified dst and decrements the stack pointer (SP). Additionally, POPI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
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MAXQ Family User’s Guide RET Return from Subroutine Description: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). The decremented SP is saved as the new stack pointer (SP).
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MAXQ Family User’s Guide RET NC Operation: C=0: IP ← @SP-C=1: IP ← IP +1 Encoding: 15 1110 Example(s): 0 1100 0000 RET NC 1101 ; C=1, return (RET) does not occur RET Z Operation: Z=1: IP ← @SP-Z=0: IP ← IP + 1 Encoding: 15 1001 Example(s): 0 1100 0000 RET Z 1101 ; Z=0, return (RET) does not occur RET NZ Operation: Z=0: IP ← @SP-Z=1: IP ← IP +1 Encoding: 15 1101 Example(s): 0 1100 0000 RET NZ 1101 ; Z=0, return (RET) is performed RET S Operation: S=1: IP ← @SP-- Encoding: 15
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MAXQ Family User’s Guide RETI Return from Interrupt Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). Additionally, RETI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
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MAXQ Family User’s Guide RETI Z Operation: Z=1: IP ← @SP-INS ← 0 Z=0: IP ← IP + 1 Encoding: 15 1001 Example(s): 0 1100 1000 RETI Z 1101 ; Z=0, return from interrupt (RETI) does not occur RETI NZ Operation: Z=0: IP ← @SP-INS ← 0 Z=1: IP ← IP +1 Encoding: 15 1101 Example(s): 0 1100 1000 RETI NZ 1101 ; Z=0, return from interrupt (RETI) is performed RETI S Operation: S=1: IP ← @SP-INS ← 0 S=0: IP ← IP + 1 Encoding: 15 1100 Example(s): 18-25 RETI S 0 1100 1000 1101 ; S=0, return fr
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MAXQ Family User’s Guide (MAXQ10 Version) RL/RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msb of the accumulator (bit 7) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 7 Active Acc 0 Acc.[7:1]← Acc.[6:0]; Acc.0 ← Acc.
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MAXQ Family User’s Guide (MAXQ20 Version) RL/RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msb of the accumulator (bit 15) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 15 Active Accumulator (Acc) 0 Acc.[15:1]← Acc.[14:0]; Acc.0 ← Acc.
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MAXQ Family User’s Guide (MAXQ10 Version) RR/RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsb of the accumulator (bit 0) back to the msb (bit 7) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: 7 Active Acc (Acc) 0 Acc.[6:0] ← Acc.[7:1]; Acc.7 ← Acc.
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MAXQ Family User’s Guide (MAXQ20 Version) RR/RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsb of the accumulator (bit 0) back to the msb (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: 15 Active Accumulator (Acc) 0 Acc.[14:0]← Acc.[15:1]; Acc.15 ← Acc.
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MAXQ Family User’s Guide (MAXQ10 Version) SLA/SLA2/SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iteration, a 0 is shifted into the lsb, and the msb is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
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MAXQ Family User’s Guide (MAXQ20 Version) SLA/SLA2/SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iteration, a 0 is shifted into the lsb, and the msb is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
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MAXQ Family User’s Guide (MAXQ10 Version) SR/SRA/SRA2/SRA4 Shift Accumulator Right/ Shift Accumulator Right Arithmetically One, Two, or Four Times Description: Shifts the active accumulator right once for the SR, SRA instructions and two or four times, respectively, for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msb, while the SRA, SRA2, and SRA4 instructions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation.
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MAXQ Family User’s Guide SRA2 Operation: 7 Active Acc (Acc) 0 Carry Flag Acc.[5:0] ← Acc.[7:2] Acc.[7:6] ← Acc.7 C ← Acc.1 Encoding: 15 1000 0 1010 1110 Example(s): 1010 ; Acc = 03h, C=0, Z=0 SRA2 SRA4 Operation: ; Acc = 00h, C=1, Z=1 7 Active Acc (Acc) 0 Carry Flag Acc.[3:0] ← Acc.[7:4] Acc.[7:4] ← Acc.7 C ← Acc.
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MAXQ Family User’s Guide (MAXQ20 Version) SR/SRA/SRA2/SRA4 Shift Accumulator Right/ Shift Accumulator Right Arithmetically One, Two, or Four Times Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times, respectively, for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msb while the SRA, SRA2, and SRA4 instructions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation.
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MAXQ Family User’s Guide SRA2 Operation: 15 Active Accumulator (Acc) 0 Carry Flag 0 Carry Flag Acc.[13:0] ← Acc.[15:2] Acc.[15:14] ← Acc.15 C ← Acc.1 Encoding: 15 1000 0 1010 1110 1010 Example(s): ; Acc = 0003h, C=0, Z=0 SRA2 SRA4 Operation: ; Acc = 0000h, C=1, Z=1 15 Active Accumulator (Acc) Acc.[11:0] ← Acc.[15:4] Acc.[15:12] ← Acc.15 C ← Acc.
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MAXQ Family User’s Guide SUB/SUBB src Subtract /Subtract with Borrow Description: Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumulator. The SUBB additionally subtracts the borrow (Carry Flag), which may have resulted from previous subtraction. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ20 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ Family User’s Guide (MAXQ20 Only) XCH Exchange Accumulator Bytes Description: Exchanges the upper and lower bytes of the active accumulator. Status Flags: S Operation: Acc.[15:8] ← Acc.[7:0] Acc.[7:0] ← Acc.[15:8] Encoding: 15 1000 0 1010 1000 1010 Example(s): ; Acc = 2345h XCHN ; Acc = 4523h XCHN Exchange Accumulator Nibbles Description: Exchanges the upper and lower nibbles in the active accumulator byte(s). Status Flags: S Operation: Acc.[7:4] ← Acc.[3:0] Acc.[3:0] ← Acc.
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MAXQ Family User’s Guide XOR src Logical XOR Description: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ20 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ Family User’s Guide REVISION HISTORY REVISION REVISION NUMBER DATE 0 1 2 3 9/04 DESCRIPTION PAGES CHANGED Original release. — Updated Loading a 16-bit register with a 16-bit immediate value: Changed …PFX[2]…to…PFX[0]. 28 Updated I/O Port: Type B: Changed alternate function to special function. 54 Replaced Table 10.