Users Guide: MAXQ2000 Supplement Manual

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MAXQ Family User’s Guide:

MAXQ2000 Supplement

TABLE OF CONTENTS

Rev 3; 6/07

ADDENDUM TO SECTION 1: OVERVIEW 7

References 7

ADDENDUM TO SECTION 2: ARCHITECTURE 7

Instruction Set 7

Harvard Memory Architecture 7

Memory Organization 9

Program Stack 9

Data SRAM 9

Program Flash 9

Program and Data Memory Mapping 9

Clock Generation 11

External High-Frequency Oscillator Circuit or Clock 12

Internal Ring Oscillator 12

External 32kHz Crystal Oscillator Circuit or Clock 13

Interrupts 13

Reset Conditions 16

Power-On Reset 16

Watchdog Timer Reset 16

External Reset 16

MAXQ2000

132-SEGMENT

LCD CONTROLLER/

DRIVER

RTC

1-WIRE MASTER

TIMER/PWM

16-BIT MAXQ™

RISC CPU

32k x 16 FLASH ROM

(64kBytes)

1k x 16 DATA RAM

(2kBytes)

16 x 16 HARDWARE

MULTIPLY

JTAG DEBUG

SERIAL UART

SPI INTERFACE

17 x 8 DISPLAY

RAM

This document is provided as a supplement to the MAXQ Family User’s Guide, covering new or modified features specific to the MAXQ2000. This document

must be used in conjunction with the MAXQ Family User’s Guide, available from Dallas Semiconductor. Addenda are arranged by section number, which

correspond to sections in the MAXQ Family User’s Guide. Additions and changes, with respect to the MAXQ Family User’s Guide, are contained in this docu-

ment. This document is a work in progress, and updates/additions are added when available.

Summary of content (93 pages)

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MAXQ Family User’s Guide: MAXQ2000 Supplement 17 x 8 DISPLAY RAM 132-SEGMENT LCD CONTROLLER/ DRIVER 32k x 16 FLASH ROM (64kBytes) 16-BIT MAXQ™ RISC CPU 1k x 16 DATA RAM (2kBytes) RTC 16 x 16 HARDWARE MULTIPLY 1-WIRE MASTER SERIAL UART TIMER/PWM SPI INTERFACE JTAG DEBUG MAXQ2000 This document is provided as a supplement to the MAXQ Family User’s Guide, covering new or modified features specific to the MAXQ2000.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Power Management Features Divide-by-256 Mode (PMM1) 32kHz Mode (PMM2) Switchback Mode Stop Mode ADDENDUM TO SECTION 3: PROGRAMMING ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE (GPIO AND EXTERNAL INTERRUPTS) ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULE ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULE ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULE Using the 32
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) 57 Bootloader Protocol Family 0 Commands (Not Password Protected) Family 1 Commands: Load Variable Length (Password Protected) Family 2 Commands: Dump Variable Length (Password Protected) Family 3 Commands: CRC Variable Length (Password Protected) Family 4 Commands: Verify Variable Length (Password Protected) Family 5 Commands: Load and Verify Variable Length (Password Protected) Family 6 Commands: Erase Var
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MAXQ Family User’s Guide: MAXQ2000 Supplement LIST OF FIGURES Figure 1. MAXQ2000 System and Peripheral Register Map 8 Figure 2. Memory Map When Executing from Application Flash/ROM 10 Figure 3. Memory Map When Executing from Utility ROM 10 Figure 4. Memory Map When Executing from Data SRAM 11 Figure 5. MAXQ2000 Clock Sources 12 Figure 6. MAXQ2000 Power-On Reset 16 Figure 7. MAXQ2000 External Reset 17 Figure 8. LCD Controller Block Diagram 66 Figure 9.
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MAXQ Family User’s Guide: MAXQ2000 Supplement LIST OF TABLES Table 1. System Clock Generation and Control Registers 12 Table 2. MAXQ2000 Interrupt Sources and Control Bits 14 Table 3. System Power Management Registers 17 Table 4. System Register Map 19 Table 5. System Register Bit Functions 20 Table 6. System Register Reset Values 21 Table 7. Peripheral Register Map 26 Table 8. Peripheral Register Bit Functions 27 Table 9. Peripheral Register Bit Reset Values 30 Table 10.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 32. LCD Display Memory Map (Static, 56-Pin Package) 76 Table 33. LCD Display Memory Map (1/2 Duty, 56-Pin Package) 76 Table 34. LCD Display Memory Map (1/3 Duty, 56-Pin Package) 77 Table 35. LCD Display Memory Map (1/4 Duty, 56-Pin Package) 77 Table 36. LCD Display Memory Map (Static, 68-Pin Package) 78 Table 37. LCD Display Memory Map (1/2 Duty, 68-Pin Package) 78 Table 38. LCD Display Memory Map (1/3 Duty, 68-Pin Package) 79 Table 39.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 1: OVERVIEW The MAXQ2000 is a low-power, high-performance 16-bit RISC microcontroller based on the MAXQ™ architecture. It includes support for integrated, in-system-programmable flash memory and a wide range of peripherals including an LCD driver supporting up to x4 multiplexed displays.
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MAXQ Family User’s Guide: MAXQ2000 Supplement • 1-Wire Interface Master • LCD Controller (up to 132 segments) The lower 8 bits of all registers in modules 0 through 4 (as well as the AP module M8) are bit addressable.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Memory Organization As with all MAXQ microcontrollers, the MAXQ2000 contains logically separate program and data memory spaces. All memory is internal, and physical memory segments (other than the stack and register memories) can be accessed as either program memory or as data memory, but not both at once. The MAXQ2000 contains the following physical memory segments.
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MAXQ Family User’s Guide: MAXQ2000 Supplement DATA SPACE (BYTE MODE) PROGRAM SPACE 1k x 16 DATA SRAM DATA SPACE (WORD MODE) A3FFh A000h 8FFFh 87FFh 4k x 8 UTILITY ROM 2k x 16 UTILITY ROM 87FFh 2k x 16 UTILITY ROM 8000h 8000h 8000h EXECUTING FROM 7FFFh 32k x 16 PROGRAM FLASH OR MASKED ROM 0000h 2k x 8 DATA SRAM 07FFh 0000h 1k x 16 DATA SRAM 003FFh 0000h Figure 2.
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MAXQ Family User’s Guide: MAXQ2000 Supplement DATA SPACE (BYTE MODE) EXECUTING FROM PROGRAM SPACE 1k x 16 DATA SRAM DATA SPACE (WORD MODE) A3FFh A000h 8FFFh 87FFh 4k x 8 UTILITY ROM 2k x 16 UTILITY ROM 8000h 7FFFh 32k x 16 PROGRAM FLASH OR MASKED ROM 64k x 8 PROGRAM FLASH OR MASKED ROM 2k x 16 UTILITY ROM 8000h 8000h 7FFFh 7FFFh 32k x 16 PROGRAM FLASH OR MASKED ROM PAGE 0 (IF CDA0 = 0) 0000h PAGE 1 (IF CDA0 = 1) 87FFh PAGES 0 AND 1 0000h 0000h Figure 4.
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MAXQ Family User’s Guide: MAXQ2000 Supplement POWER-ON RESET RWT RESET STOP RESET DOG XDOG COUNT RESET WATCHDOG TIMER XDOG STARTUP TIMER WATCHDOG RESET WATCHDOG INTERRUPT XDOG DONE CLK INPUT CRYSTAL KLL HF CRYSTAL MAXQ2000 STOP CLOCK DIVIDER RING GLITCH-FREE MUX GLITCH-FREE MUX POWER-ON RESET ENABLE CLOCK GENERATION SYSTEM CLOCK WAKE-UP ALARM TIMERS 32kHz CRYSTAL DIV 1 DIV 2 DIV 4 DIV 8 32kHz PMM ENABLE SWB INTERRUPT/SERIAL PORT RESET SELECTOR DEFAULT RING SELECT STOP INPUT CRYSTAL
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MAXQ Family User’s Guide: MAXQ2000 Supplement To select the ring oscillator as the system clock source, the RGSL bit (CKCN.6) must be set to 1. Setting this bit immediately switches over the system clock source to the ring oscillator. The RGMD (CKCN.5) bit indicates the current system clock source. If the ring oscillator is currently providing the system clock, RGMD equals 1; otherwise, RGMD equals 0.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 2. MAXQ2000 Interrupt Sources and Control Bits MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG Watchdog Interrupt INTERRUPT IMS (IMR.7) EWDI (WDCN.6) WDIF (WDCN.3) External Interrupt 0 IM0 (IMR.0) EX0 (EIE0.0) IE0 (EIF0.0) External Interrupt 1 IM0 (IMR.0) EX1 (EIE0.1) IE1 (EIF0.1) External Interrupt 2 IM0 (IMR.0) EX2 (EIE0.2) IE2 (EIF0.2) External Interrupt 3 IM0 (IMR.0) EX3 (EIE0.3) IE3 (EIF0.3) External Interrupt 4 IM0 (IMR.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 2. MAXQ2000 Interrupt Sources and Control Bits (continued) INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG Timer 1–Capture/Compare IM4 (IMR.4) ET2 (T2CNA1.7) TCC2 (T2CNB1.1) Timer 1–Overflow IM4 (IMR.4) ET2 (T2CNA1.7) TF2 (T2CNB1.3) Timer 2–Low Compare IM4 (IMR.4) ET2L (T2CNB2.7) T2CL (T2CNB2.0) Timer 2–Low Overflow IM4 (IMR.4) ET2L (T2CNB2.7) TF2L (T2CNB2.2) Timer 2–Capture/Compare IM4 (IMR.4) ET2 (T2CNA2.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Reset Conditions There are three possible reset sources for the MAXQ2000. While in the reset state, the enabled system clock oscillator continues running, but no code execution occurs. Once the reset condition has been removed or has completed, code execution resumes at address 8000h for all reset types.
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MAXQ Family User’s Guide: MAXQ2000 Supplement CLOCK RESET RESET SAMPLING INTERNAL RESET FIRST INSTRUCTION FETCH Figure 7. MAXQ2000 External Reset Power Management Features The MAXQ2000 provides the following features to assist in power management. • Divide-by-256 (PMM1) and 32kHz (PMM2) modes to reduce current consumption. • Switchback mode to exit PMM modes automatically when rapid processing is required. • Ultra-low-power Stop mode.
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MAXQ Family User’s Guide: MAXQ2000 Supplement This power management mode is entered by setting the PMME bit (CKCN.2) to 1 while the CD1 and CD0 (CKCN[1:0]) bits are both cleared to 0. When PMM1 mode is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation will revert to the mode indicated by the values of the CD1 and CD0 bits, which in this case will be the standard divide-by-1 clock mode.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Note that exiting Stop mode through external reset or power-on reset causes the processor to undergo a normal reset cycle, as opposed to resuming execution at the point at which it entered Stop mode. Exiting Stop mode by means of an external interrupt or time-of-day alarm causes the processor to resume execution at the instruction following the one that set the STOP bit. When Stop mode is exited, processor execution resumes as follows.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 5.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 6. System Register Reset Values REG BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 AP 0 0 0 0 0 0 0 0 APC 0 0 0 0 0 0 0 0 PSF 1 0 0 0 0 0 0 0 IC 0 0 0 0 0 0 0 0 IMR 0 0 0 0 0 0 0 0 SC 0 0 0 0 0 0 s 0 IIR 0 0 0 0 0 0 0 0 CKCN 0 s s 0 0 0 0 0 s s 0 0 0 s s 0 A[0..
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MAXQ Family User’s Guide: MAXQ2000 Supplement The following section details the functionality of any System Registers contained in the MAXQ2000 that operate differently from their descriptions in the MAXQ Family User’s Guide.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Bits 5 and 6: (SC.5 and SC.6) Reserved Bit 7: (SC.7) Test Access (JTAG) Port Enable 0 = JTAG TAP functions are disabled and P4.0 through P4.3 can be used as general-purpose I/O pins. 1 = TAP special function pins P4.0 through P4.3 are enabled to act as JTAG inputs and outputs.
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MAXQ Family User’s Guide: MAXQ2000 Supplement MAXQ2000 System Clock Modes RGMD SWB PMME CD1 CD0 SYSTEM CLOCK HIGH-FREQUENCY OSCILLATOR SWITCHBACK 0 0 0 0 0 HFOsc / 1 Running N/A 0 0 0 0 1 HFOsc / 2 Running N/A 0 0 0 1 0 HFOsc / 4 Running N/A 0 0 0 1 1 HFOsc / 8 Running N/A 0 0 1 0 0 HFOsc / 256 Running Not Active 0 1 1 0 0 HFOsc / 256 Running Active 1 0 0 0 0 Ring / 1 Off or Warming Up N/A 1 0 0 0 1 Ring / 2 Off or Warming Up N/A 1 0
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MAXQ Family User’s Guide: MAXQ2000 Supplement Bit 3: (CKCN.3) Switchback Enable (SWB). Setting this bit to 1 enables Switchback mode. If power management mode (either divide by 256 or 32kHz) is active and Switchback is enabled, the PMME bit will be cleared to 0 when any of the following conditions occur. • An external interrupt is generated based on an edge detect. • Either serial port 0 or serial port 1 is enabled to receive data and detects a low condition on its data receive pin.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES Refer to the MAXQ Family User’s Guide. Table 7.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 8.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 8.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 8. Peripheral Register Bit Functions (continued) REG BIT15 BIT14 BIT13 BIT12 BIT11 BIT 10 BIT 9 BIT 8 T2CH0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T2C0.9 T2C0.8 RB8 TI RI T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 SPIB SPIB (16 bits) SCON1 SM0/FE SM1 SM2 — — — — — ESI1 SMOD1 FEDE1 ET2L T2OE1 T2POL1 TR2L TF2 TF2L TCC2 TC2L T2V0.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 9.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 9.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 9.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE (GPIO AND EXTERNAL INTERRUPTS) The MAXQ2000 provides 50 port pins (in the 68-pin package) or 38 port pins (in the 56-pin package) for general-purpose I/O, which are grouped into logical ports P0 through P7. Each of these port pins has the following features. • CMOS output drivers • Schmitt trigger inputs • Optional weak pullup to VDDIO when operating in input mode Port pins P6.4, P6.5, P7.0, and P7.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 10. Port Pin Special Functions (continued) PORT PIN TYPE SPECIAL FUNCTION ENABLED WHEN P3.1 Analog LCD Segment SEG25 PCF3=1 and OPM=1 P3.2 Analog LCD Segment SEG26 PCF3=1 and OPM=1 P3.3 Analog LCD Segment SEG27 PCF3=1 and OPM=1 P3.4 Analog LCD Segment SEG28 PCF3=1 and OPM=1 P3.4 Input External Interrupt 4 EX4=1 P3.5 Analog LCD Segment SEG29 PCF3=1 and OPM=1 P3.5 Input External Interrupt 5 EX5=1 P3.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 11. Port Pin Special Functions (56-Pin Package) PORT PIN TYPE P0.0 Analog LCD Segment SEG0 PCF0=1 and OPM=1 P0.1 Analog LCD Segment SEG1 PCF0=1 and OPM=1 P0.2 Analog LCD Segment SEG2 PCF0=1 and OPM=1 P0.3 Analog LCD Segment SEG3 PCF0=1 and OPM=1 P0.4 Analog LCD Segment SEG4 PCF0=1 and OPM=1 P0.4 Input External Interrupt 0 EX0=1 P0.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 11. Port Pin Special Functions (56-Pin Package) (continued) PORT PIN TYPE P4.0 Input JTAG Interface—TAP Clock (TCK) SPECIAL FUNCTION (SC.7) TAP=1 ENABLED WHEN P4.0 Input External Interrupt 8 EX8=1 P4.1 Input JTAG Interface—TAP Data Input (TDI) (SC.7) TAP=1 P4.1 Input External Interrupt 9 EX9=1 P4.2 Input JTAG Interface—TAP Mode Select (TMS) (SC.7) TAP=1 P4.3 Input JTAG Interface—TAP Data Output (TDO) (SC.7) TAP=1 P5.
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MAXQ Family User’s Guide: MAXQ2000 Supplement The following peripheral registers control the general-purpose I/O and external interrupt features specific to the MAXQ2000. Register Name: Register Description: Register Address: Bit # PO0 Port 0 Output Register M0[00h] 7 6 5 4 3 2 1 0 Name PO0.7 PO0.6 PO0.5 PO0.4 PO0.3 PO0.2 PO0.1 PO0.0 Reset 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w Access Bits 0 to 7: (PO0.0 to PO0.7) Port 0 Output.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: Bit # Name PO3 Port 3 Output Register M0[03h] 7 6 5 4 3 2 1 0 PO3.7 PO3.6 PO3.5 PO3.4 PO3.3 PO3.2 PO3.1 PO3.0 Reset Access 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w Bits 0 to 7: (PO3.0 to PO3.7) Port 3 Output. This register stores the data that will be output on any of the pins of Port 3 that have been defined as output pins.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Bit 0: (EIE0.0) External Interrupt 0 Enable (EX0) Bit 1: (EIE0.1) External Interrupt 1 Enable (EX1) Bit 2: (EIE0.2) External Interrupt 2 Enable (EX2) Bit 3: (EIE0.3) External Interrupt 3 Enable (EX3) Bit 4: (EIE0.4) External Interrupt 4 Enable (EX4) Bit 5: (EIE0.5) External Interrupt 5 Enable (EX5) Bit 6: (EIE0.6) External Interrupt 6 Enable (EX6) Bit 7: (EIE0.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: Bit # PI3 Port 3 Input Register M0[0Bh] 7 6 5 4 3 2 1 0 Name PI3.7 PI3.6 PI3.5 PI3.4 PI3.3 PI3.2 PI3.1 PI3.0 Reset s s s s s s s s Access r r r r r r r r Each of the read-only bits in this register reflects the logic state present at the corresponding port pin.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: Bit # PD1 Port 1 Direction Register M0[11h] 7 6 5 4 3 2 1 0 Name PD1.7 PD1.6 PD1.5 PD1.4 PD1.3 PD1.2 PD1.1 PD1.0 Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access Each of the bits in this register controls the input/output direction of a port pin (P1.0 to P1.7), as follows.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: PO4 Port 4 Output Register M1[00h] Bit # 7 6 5 4 3 2 1 0 Name — — — PO2.4 PO2.3 PO2.2 PO2.1 PO2.0 Reset 0 0 0 1 1 1 1 1 Access r r r r/w r/w r/w r/w r/w Bits 0 to 4: (PO4.0 to PO4.4) Port 4 Output. This register stores the data that will be output on any of the pins of Port 4 that have been defined as output pins.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: PO7 Port 7 Output Register M1[03h] Bit # 7 6 5 4 3 2 1 0 Name — — — — — — PO2.1 PO2.0 Reset 0 0 0 0 0 0 1 1 Access r r r r r r r/w r/w Bits 0 and 1: (PO7.0 and PO7.1) Port Output for P7.0 and P7.1. This register stores the data that will be output on any of the pins of Port 7 that have been defined as output pins.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: Bit # EIE1 External Interrupt Enable 1 Register M1[07h] 7 6 5 4 3 2 1 0 Name EX15 EX14 EX13 EX12 EX11 EX10 EX9 EX8 Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access Each bit in this register controls the enable for one external interrupt. If the bit is set to 1, the interrupt is enabled (if it is not otherwise masked).
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: Bit # PI6 Port 6 Input Register M1[0Ah] 7 6 5 4 3 2 1 0 Name PI6.7 PI6.6 PI6.5 PI6.4 PI6.3 PI6.2 PI6.1 PI6.0 Reset s s s s s s s s Access r r r r r r r r Bits 0 to 7: (PI6.0 to PI6.7) Port Pin Input Bits for P6.0 to P6.7. Each of these read-only bits reflects the logic state present at the corresponding port pin.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: PD4 Port 4 Direction Register M1[10h] Bit # 7 6 5 4 3 2 1 0 Name — — — PD4.4 PD4.3 PD4.2 PD4.1 PD4.0 Reset 0 0 0 0 0 0 0 0 Access r r r r/w r/w r/w r/w r/w Bits 0 to 4: (PD4.0 to PD4.4) Port Direction Bits for P4.0 to P4.4. Each these bits controls the input/output direction of its corresponding port pin as follows.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: PD7 Port 7 Direction Register M1[13h] Bit # 7 6 5 4 3 2 1 0 Name — — — — — — PD7.1 PD7.0 Reset 0 0 0 0 0 0 0 0 Access r r r r/w r/w r/w r/w r/w Bits 0 and 1: (PD7.0 and PD7.1) Port Direction Bits for P7.0 and P7.1. Each these bits controls the input/output direction of its corresponding port pin as follows.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: WKO Wakeup Output Register M1[1Fh] Bit # 7 6 5 4 3 2 1 0 Name — — — — — WKL WKE1 WKE0 Reset 0 0 0 0 0 0 0 0 Access r r r r r r/w r/w r/w Bit 0: (WKO.0) Wakeup Output 0 Enable (WKE0). When set to 1, this bit enables the output of a wakeup signal on port pin P6.4.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULE The MAXQ2000 does not provide these peripherals. Refer to the MAXQ Family User’s Guide. ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULE The MAXQ2000 does not provide these peripherals. Refer to the MAXQ Family User’s Guide. ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULE The MAXQ2000 provides three Type 2 timer/counters (Timer 0, Timer 1, Timer 2), which operate as described in the MAXQ Family User’s Guide.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 14. Type 2 Timer/Counter Control Registers (continued) REGISTER ADDRESS FUNCTION T2V1 M4[09h] Timer/Counter 1 (Type 2) Value Register T2H1 M4[01h] Timer/Counter 1 (Type 2) Value MSB Register. Provides access to high byte of T2V. T2R1 M4[0Ah] Timer/Counter 1 (Type 2) Reload Register T2RH1 M4[02h] Timer/Counter 1 (Type 2) Reload MSB Register. Provides access to high byte of T2R.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 10: SERIAL I/O (UART) MODULE The MAXQ2000 provides up to two serial UART modules (Serial 0 and 1 in the 68-pin package, Serial 0 in the 56-pin package), which operate as described in the MAXQ Family User’s Guide. Table 15 shows the associated pins and Table 16 shows the associated registers for these UARTs. Table 15.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) The MAXQ2000 provides a Serial Peripheral Interface (SPI) module, which operates as described in the MAXQ Family User’s Guide. Table 17 shows the associated pins and Table 18 shows the associated registers for this interface. Table 17. SPI Input and Output Pins PIN NUMBER SPI INTERFACE FUNCTION MULTIPLEXED WITH PORT PIN 68-PIN 56-PIN Slave Select—SSEL 38 — P5.4 Slave Clock—SCLK 40 — P5.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 12: HARDWARE MULTIPLIER The MAXQ2000 provides a hardware multiplier module that provides the following features (detailed in the MAXQ Family User’s Guide).
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 13: 1-Wire BUS MASTER The MAXQ2000 provides a 1-Wire Bus Master (68-pin package only) that operates as described in the MAXQ Family User’s Guide. Tables 20 to 23 show the associated pins and registers for this interface. Table 20. 1-Wire Master Input and Output Pins PIN NUMBER 1-WIRE MASTER FUNCTION MULTIPLEXED WITH PORT PIN 68-PIN 56-PIN 1-Wire Master Input—OW_IN 46 — P6.3 1-Wire Master Output—OW_OUT 47 — P6.4 Table 21.
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MAXQ Family User’s Guide: MAXQ2000 Supplement 1-Wire Example: Reset and Presence Detect OW_COMMAND OW_BUFFER OW_INTERRUPT OW_INT_ENABLE OW_CLOCK OW_CONTROL equ equ equ equ equ equ 00h 01h 02h 03h 04h 05h move move OWA, #OW_CLOCK OWD, #10001001b ; Access 1-Wire Clock Control Register ; Divide ratio = 12, enable clock move move OWA, #OW_CONTROL OWD, #00h ; Access 1-Wire Control Register ; Clear register Reset: move move OWA, #OW_COMMAND OWD, #01h ; Access 1-Wire Command Register ; Initiate 1-Wire r
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MAXQ Family User’s Guide: MAXQ2000 Supplement ADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP) The JTAG TAP port on the MAXQ2000 is multiplexed with port pins P4.0, P4.1, P4.2, and P4.3. These pins default to their JTAG TAP function on reset, which means that the part will always be ready for in-circuit debugging or in-circuit programming operations following any reset. Once an application has been loaded and starts running, the JTAG TAP port can still be used for in-circuit debugging operations.
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MAXQ Family User’s Guide: MAXQ2000 Supplement The first byte output by this command is the value 146 (092h), which represents the number of peripheral registers output. Table 25 lists the remaining 356 bytes output by this command. Table 25.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Bit 1: (ICDF.1) System Program Enable (SPE). This bit controls the behavior of the MAXQ2000 following reset. 0 = The MAXQ2000 jumps to application code (in flash/ROM) at 0000h following a reset. 1 = The MAXQ2000 executes the in-system programming bootloader following a reset. Bits 2 and 3: (ICDF.2 and ICDF.3) Programming Source Select (PSS0 and PSS1). When SPE = 1, these bits determine which interface is used for in-system programming operations.
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MAXQ Family User’s Guide: MAXQ2000 Supplement All commands in Family 0 can be executed without first matching the password. All other commands (in Families 1x through Fx) are password protected; the password must first be matched before these commands can be executed. A special case exists when the program memory has not been initialized (following master erase).
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 27. Bootloader Status Flags FLAG BIT FUNCTION 0 Password Lock 0 = The password is unlocked or had a default value; password-protected commands can be used. 1 = The password is locked. Password-protected commands cannot be used. 1 Word/Byte Mode 0 = The bootloader is currently in byte mode for memory reads/writes. 1 = The bootloader is currently in word mode for memory reads/writes.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Command 09h—Get Utility ROM Version I/O Byte 1 Input 09h Output VersionL Byte 2 VersionH Command 0Ah—Set Word/Byte Mode Access The Mode byte should be 0 to set byte access mode or 1 to set word access mode. The current access mode is returned in the status flag byte by command 04h, as well as a flag to indicate whether word access mode is supported by this particular bootloader.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Family 2 Commands: Dump Variable Length (Password Protected) Command 20h—Dump Code Variable Length This command has a slightly different format depending on the length of the dump requested. It returns the contents of the application flash/ROM—(LengthL) or (LengthH:LengthL) bytes/words starting at (AddressH:AddressL).
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MAXQ Family User’s Guide: MAXQ2000 Supplement Family 4 Commands: Verify Variable Length (Password Protected) Command 40h—Verify Code Variable Length This command operates in the same manner as the “Load Code Variable Length” command, except that instead of programming the input data into code flash, it verifies that the input data matches the data already in code space. If the data does not match, the status code is set to reflect this failure.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Family E Commands: Erase Fixed Length (Password Protected) Command E0h—Erase Code Fixed Length This command erases (programs to FFFFh) all words in a 256-word block of the program flash memory. The address given should be located in the 256-word block to be erased. For example, providing address 0000h (in byte mode) to this command will erase the first 256-word block, address 0200h will erase the second block, and so on.
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MAXQ Family User’s Guide: MAXQ2000 Supplement DATA TRANSFER BRANCHING MATH MNEMONIC ADD src ADDC src SUB src SUBB src {L/S}JUMP src {L/S}JUMP C, src {L/S}JUMP NC, src {L/S}JUMP Z, src {L/S}JUMP NZ, src {L/S}JUMP E, src {L/S}JUMP NE, src {L/S}JUMP S, src {L/S}DJNZ LC[n], src {L/S}CALL src RET RET C RET NC RET Z RET NZ RET S RETI RETI C RETI NC RETI Z RETI NZ RETI S XCH (MAXQ20 only) XCHN MOVE dst, src PUSH src POP dst POPI dst CMP src NOP DESCRIPTION Acc ← Acc + src Acc ← Acc + (src + C) Acc ← Acc – src
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MAXQ Family User’s Guide: MAXQ2000 Supplement LCD CONTROLLER (SPECIFIC TO MAXQ2000) The MAXQ2000 provides an on-board LCD controller module that can generate segment and common signals for an LCD based on display memory content. Once the LCD controller settings and display memory have been initialized, the LCD segment and common signals are generated automatically at the selected display frequency. No additional processor overhead is required while the LCD controller is running.
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MAXQ Family User’s Guide: MAXQ2000 Supplement The following peripheral registers are used to control the LCD controller. Register Name: Register Description: Register Address: Bit # LCFG LCD Configuration Register M2[0Eh] 7 6 5 4 3 2 1 0 Name PCF3 PCF2 PCF1 PCF0 — — OPM DPE Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access Bit 0: (LCFG.0) Display Enable (DPE).
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: LCRA LCD Adjust Register M2[0Dh] Bit # 15 14 13 12 11 10 9 8 Name — — — DUTY1 DUTY0 FRM3 FRM2 FRM1 Reset 0 0 0 0 0 0 0 0 Access r r r r/w r/w r/w r/w r/w Bit # 7 6 5 4 3 2 1 0 Name FRM0 LCCS LRIG LRA4 LRA3 LRA2 LRA1 LRA0 Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access This register can only be written to when the LCD contr
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MAXQ Family User’s Guide: MAXQ2000 Supplement The following registers (LCD0 to LCD15) contain display memory for the LCD controller.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: LCD4 LCD Display Register 4 M2[14h] Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access Register Name: Register Description: Register Address: LCD5 LCD Display Register 5 M2[15h] Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access Register Name: Register Description: Register Address: LCD6
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: Bit # Reset Access 7 Reset Access Reset Access 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w 4 3 2 1 0 7 LCD9 LCD Display Register 9 M2[19h] 6 5 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 4 3 2 1 0 Register Name: Register Description: Register Address: Bit # 6 r/w Register Name: Register Description: Register Address: Bit # LCD8 LCD Dis
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MAXQ Family User’s Guide: MAXQ2000 Supplement Register Name: Register Description: Register Address: LCD12 LCD Display Register 12 M2[1Ch] Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access Register Name: Register Description: Register Address: LCD13 LCD Display Register 13 M2[1Dh] Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w Access Register Name: Register Description: Register Address:
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MAXQ Family User’s Guide: MAXQ2000 Supplement LCD Controller Operation Modes The LCD controller defaults to suspended mode (OPM = 0, DPE = x) on power-up. In this mode, the LCD controller is completely shut down to conserve power. Any pins that are configured for LCD operation (as well as any dedicated LCD segment/common pins) are driven by a weak pullup to VDDIO. Setting the OPM bit to 1 places the LCD controller in normal operating mode.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Segment Pin Configuration The PCF[3:0] bits in the LCFG register switch four banks of pins between LCD segment-display mode and general-purpose port-pin mode. These pins are grouped in banks of four or eight, depending on the package type. Since all of the PCF bits default to 0 on reset, all pins that share LCD segment and port pin capability act as port pins by default.
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MAXQ Family User’s Guide: MAXQ2000 Supplement LCD Frame Frequency The LCD controller clock frequency (fLCD) can be sourced from either the 32kHz clock or the high-frequency clock divided by 128 as specified by the LCCS bit. If Stop mode is entered and the 32kHz clock is being used, LCD display operation continues (if OPM = 1).
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 32. LCD Display Memory Map (Static, 56-Pin Package) REGISTER BIT 7 COM0 BIT 6 COM0 BIT 5 COM0 BIT 4 COM0 BIT 3 COM0 BIT 2 COM0 BIT 1 COM0 BIT 0 COM0 LCD0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 LCD1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 LCD2 SEG19 SEG18 SEG17 SEG16 LCD3 SEG23 SEG22 SEG21 SEG20 LCD4 SEG27 SEG26 SEG25 SEG24 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 LCD16 Table 33.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 34.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 36.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 38.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Display Waveform Generation Once the operational modes and display memory registers on the LCD controller have been properly initialized, the controller generates the segment and common drive waveforms needed to display the enabled segments on the attached LCD display. In static mode, each segment pin is connected to a single LCD segment. There is only one common, or backplane, signal, which is driven by COM0.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 40. Static Drive Example Common Signal Selection COM0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 ON ON ON ON off ON ON off COM1 COM2 COM3 According to the static memory map table, a value of 0F6h should be written to the LCD0 register as shown in Table 41. Table 41.
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MAXQ Family User’s Guide: MAXQ2000 Supplement LCD Controller 1/2 Duty Cycle Drive Example In this example, SEG0 through SEG3 are used to drive the LCD segments. The segments and common signals are connected as shown in Figure 14. SEG0 SEG1 SEG2 SEG3 COM0 COM1 Figure 14. 1/2 Duty Drive Example Display Connection Table 42.
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MAXQ Family User’s Guide: MAXQ2000 Supplement 1 FRAME (fFRAME) COM0 VLCD VLCD1 GND COM1 VLCD VLCD1 GND SEG0 VLCD VLCD1 GND SEG1 VLCD VLCD1 GND SEG2 VLCD VLCD1 GND SEG3 VLCD VLCD1 GND COM0–SEG0 (OFF) VLCD 1/2 VLCD GND -1/2 VLCD -VLCD COM0–SEG1 (ON) VLCD 1/2 VLCD GND -1/2 VLCD -VLCD Figure 15. 1/2 Duty Drive Example Waveform Timing LCD Controller 1/3 Duty Cycle Drive Example In this example, SEG0 through SEG2 are used to drive the LCD segments.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Table 44. 1/3 Duty Drive Example Common Signal Selection SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 ON ON ON COM1 off ON off COM2 ON ON (don’t care) COM0 COM3 According to the 1/3 duty drive memory map table, LCD0 should be set to 071h and LCD1 should be set to 05h as shown in Table 45. Table 45.
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MAXQ Family User’s Guide: MAXQ2000 Supplement LCD Controller 1/4 Duty Cycle Drive Example In this example, SEG0 and SEG1 are used to drive the LCD segments. The segments and common signals are connected as shown in Figure 18. COM3 COM2 COM1 SEG0 COM0 SEG1 Figure 18. 1/4 Duty Drive Example Display Connection Table 46.
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MAXQ Family User’s Guide: MAXQ2000 Supplement 1 FRAME (fFRAME) COM0 VLCD VLCD1 VLCD2 GND COM1 VLCD VLCD1 VLCD2 GND COM2 VLCD VLCD1 VLCD2 GND COM3 VLCD VLCD1 VLCD2 GND SEG0 VLCD VLCD1 VLCD2 GND SEG1 VLCD VLCD1 VLCD2 GND COM3–SEG0 (OFF) VLCD 2/3 VLCD 1/3 VLCD GND -1/3 VLCD -2/3 VLCD -VLCD COM3–SEG1 (ON) VLCD 2/3 VLCD 1/3 VLCD GND -1/3 VLCD -2/3 VLCD -VLCD Figure 19. 1/4 Duty Drive Example Waveform Timing LCD Controller Example: Initializing the LCD Controller move LCRA, #03E0h ; LCRA.
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MAXQ Family User’s Guide: MAXQ2000 Supplement UTILITY ROM (SPECIFIC TO MAXQ2000) The MAXQ2000 utility ROM includes routines that provide the following functions to application software.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Function: Summary: Inputs: Outputs: Destroys: flashErasePage Erases (programs to 0FFFFh) a 256-word page of flash memory. A[0]: Word address located in the page to be erased. (The page number is the high byte of A[0].) Carry: Set on error and cleared on success. PSF, LC[1], GR, AP, APC, A[0] Notes: 1) If the watchdog reset function is active, it should be disabled before calling this function.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Function: Summary: Inputs: Outputs: Destroys: moveDP0dec Reads the byte/word value pointed to by DP[0], then decrements DP[0]. DP[0]: Address to read from GR: Data byte/word read DP[0] is decremented None Notes: 1) Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 3.
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MAXQ Family User’s Guide: MAXQ2000 Supplement Function: Summary: Inputs: Outputs: Destroys: moveFP Reads the byte/word value pointed to by BP[Offs]. BP[Offs]: Address to read from GR: Data byte/word read None Notes: 1) Before calling this function, DPC should be set appropriately to configure BP[Offs] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 3.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ROM Example 1: Calling A Utility ROM Function Directly This example shows the direct addressing method for calling utility functions, using the function moveDP1inc to read a static string from code space. Note the equate UROM_MOVEDP1INC. UROM_MOVEDP1INC EQU 08493h Text: DB “Hello World!”,0 ; Define a string in code space.
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MAXQ Family User’s Guide: MAXQ2000 Supplement ROM Example 2: Calling A Utility ROM Function Indirectly The second example shows the indirect addressing method (lookup table) for calling utility functions. We use the same function (UROM_MoveDP1Inc) to read our static string, but this time we must figure out the address we want dynamically. Note the inserted code where we before had a direct call to the function. Also note that the function index of moveDP1inc is 7.
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MAXQ Family User’s Guide: MAXQ2000 Supplement REVISION HISTORY Rev 0; 10/04: Original release. Rev 1; 10/05: Family Commands section updated. Commands 11h, 20h, 21h, 30h, 31h, and 60h, input to dump, > 256, byte 3 changed from AddressH to AddressL. Rev 2; 11/05: Added note on using the alternate 32kHz clock with Timer 2. Updates and clarifications to POR, LCD, interrupt, utility ROM, and JTAG sections. Added instruction set summary table from MAXQ Family User’s Guide to Section 18.