Users Guide: MAXQ2010 Supplement User Manual

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MAXQ FAMILY USER’S GUIDE:

MAXQ2010 SUPPLEMENT

Rev 0; 6/09

HFX

FLL

32kHz

INSTRUCTION

DECODER

PROGRAM

MEMORY

DATA

MEMORY

CONTROL

STACK

ADD REG

ADDRESS

GENERATOR

DEMUX

MUX

SYSTEM

REGISTERS

IN-CIRCUIT

DEBUGGER

PERIPHERAL

REGISTERS

Acc

STATUS

JTAG

INTERRUPT

SUPPLY

VOLTAGE

MONITOR

MACWATCHDOG

POWER

OSC UP

BROWNOUT

RESET

LCD

DVDD

DGND

AVDD

AGND

12-BIT

8-CHANNEL

ADC

CRTCSPI

RESET

PMM

STOP

SYSTEM

CLOCK

TIMERUSART

MAXQ2010

Summary of content (147 pages)

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Rev 0; 6/09 MAXQ FAMILY USER’S GUIDE: MAXQ2010 SUPPLEMENT IN-CIRCUIT DEBUGGER ADD REG JTAG ADDRESS GENERATOR MAXQ2010 STACK IP DP SYSTEM REGISTERS STATUS Acc 16 MUX DEMUX CONTROL 16 PERIPHERAL REGISTERS INSTRUCTION DECODER PROGRAM MEMORY DATA MEMORY SPI USART HFX PMM FLL STOP 32kHz TIMER AVDD AGND SYSTEM CLOCK WATCHDOG POWER LCD DVDD DGND OSC UP BROWNOUT RESET RTC I2C MAC 12-BIT 8-CHANNEL ADC INTERRUPT SUPPLY VOLTAGE MONITOR RESET ____________________________________________
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MAXQ Family User’s Guide: MAXQ2010 Supplement TABLE OF CONTENTS ADDENDUM TO SECTION 1: OVERVIEW 1-1 1.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ADDENDUM TO SECTION 2: ARCHITECTURE 2-1 2.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement TABLE OF CONTENTS (continued) 6.1.2 Port 1 Direction Register (PD1, M0[11h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.3 Port 2 Direction Register (PD2, M0[12h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.1.4 Port 3 Direction Register (PD3, M0[13h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ2010 Supplement TABLE OF CONTENTS (continued) ADDENDUM TO SECTION 10: SERIAL I/O MODULE 10-1 10.1 Serial USART I/O Pins and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 Serial USART Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement TABLE OF CONTENTS (continued) ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) 17-1 17.1 JTAG Bootloader Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 Family 0 Commands (Not Password Protected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.
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MAXQ Family User’s Guide: MAXQ2010 Supplement TABLE OF CONTENTS (continued) 20.2.13 LCD Display Register 10 (LCD10, M2[15h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.2.14 LCD Display Register 11 (LCD11, M2[16h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.2.15 LCD Display Register 12 (LCD12, M2[17h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.
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MAXQ Family User’s Guide: MAXQ2010 Supplement TABLE OF CONTENTS (continued) 21.2.7 16-Bit Up/Down Count PWM/Output Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10 21.2.8 EXENB Control During PWM/Output Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 21.3 Timer B Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ2010 Supplement TABLE OF CONTENTS (continued) 24.3.6 UROM_moveDP1dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.3.7 UROM_moveBP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.3.8 UROM_moveBPinc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ2010 Supplement LIST OF FIGURES Figure 2-1. MAXQ2010 System and Peripheral Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2-2. Memory Map When Executing from Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-3. Memory Map When Executing from Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement LIST OF TABLES Table 2-1. System Clock Generation and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Table 2-2. Interrupt Sources and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Table 2-3. System Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ2010 Supplement LIST OF TABLES (continued) Table 20-13. 1/4 Duty Drive Example Common Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 Table 20-14. 1/4 Duty Drive Example Register Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 Table 21-1. Type B Timer/Counter Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 1: OVERVIEW This document is provided as a supplement to the MAXQ Family User’s Guide, covering new or modified features specific to the MAXQ2010. This document must be used in conjunction with the MAXQ Family User’s Guide, available on our website at www.maxim-ic.com/MAXQUG. Addenda are arranged by section number, which correspond to sections in the MAXQ Family User’s Guide.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 2: ARCHITECTURE The MAXQ2010 shares the common architecture features with other members of the MAXQ microcontroller family. Details are discussed in the following sections. 2.1 Instruction Set This device uses the standard 16-bit MAXQ20 core instruction set as described in the MAXQ Family User’s Guide. 2.2 Harvard Memory Architecture Program memory, data memory, and register space follow the Harvard architecture model.
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MAXQ Family User’s Guide: MAXQ2010 Supplement REGISTER MODULE M1 M2 M3 M4 M8 M9 PO0 PO4 MCNT I2CBUF TBOR AP A[O] O1h PO1 PO5 MA I2CST TBOC APC A[1] SP O2h PO2 PO6 MB I2CIE TB1R A[2] IV O3h PO3 SPIB MC2 TB1C A[3] REGISTER INDEX M12 M13 M14 M15 OFFS DP[O] IP PFX DPC O4h EIFO EIF1 MC1 SCON0 TB2R PSF A[4] O5h EIEO EIE1 MC0 SBUFO TB2C IC A[5] O6h EIF2 LCFG SCON1 ADST IMR A[6] LC[0] GRL O7h EIE2 SBUF1 ADADDR A[7] LC[1] BP GRS TBOV A[9
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MAXQ Family User’s Guide: MAXQ2010 Supplement 2.4 Memory Organization As with all MAXQ microcontrollers, the MAXQ2010 contains logically separate program and data memory spaces. All memory is internal, and physical memory segments (other than the stack and register memories) can be accessed as either program memory or as data memory, but not both at once. The MAXQ2010 contains the following physical memory segments. 2.4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement DATA SPACE (BYTE MODE) PROGRAM SPACE FFFFh 1K x 16 DATA SRAM DATA SPACE (WORD MODE) FFFFh FFFFh 8FFFh 87FFh A3FFh A000h 87FFh 4K x 8 UTILITY ROM 2K x 16 UTILITY ROM 2K x 16 UTILITY ROM 8000h 8000h 8000h EXECUTING FROM 7FFFh 32K x 16 PROGRAM FLASH 0000h 2K x 8 DATA SRAM 07FFh 1K x 16 DATA SRAM 0000h 03FFh 0000h Figure 2-2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement PROGRAM SPACE DATA SPACE (BYTE MODE, CDA0 = 0) EXECUTING FROM FFFFh DATA SPACE (BYTE MODE, CDA0 = 1) DATA SPACE (WORD MODE) FFFFh FFFFh FFFFh 8FFFh 8FFFh 87FFh A3FFh 1K x 16 DATA SRAM A000h 87FFh 2K x 16 UTILITY ROM 2K x 8 UTILITY ROM 4K x 8 UTILITY ROM 4K x 8 UTILITY ROM 8000h 8000h 8000h 8000h 7FFFh 7FFFh 7FFFh 7FFFh 16K x 16 PROGRAM FLASH (PAGE 1) 4000h 3FFFh 16K x 16 PROGRAM FLASH (PAGE 0) 32K x 8 LOWER HALF (PAGE 0) OF PROGRAM FLAS
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MAXQ Family User’s Guide: MAXQ2010 Supplement POWER-ON RESET RESET STOP XDOG STARTUP TIMER RWT RESET DOG XDOG COUNT RESET WATCHDOG TIMER WATCHDOG RESET WATCHDOG INTERRUPT XDOG DONE CLK INPUT CRYSTAL KLL HF CRYSTAL MAXQ2010 POWER-ON RESET WAKE-UP TIMER, LCD CONTROLLER 32kHz CRYSTAL ENABLE GLITCH-FREE MUX CLOCK DIVIDER CLOCK GENERATION SYSTEM CLOCK DIV 1 DIV 2 DIV 4 DIV 8 32kHz PMM1 FLL ENABLE GLITCH-FREE MUX STOP SWB INTERRUPT/SERIAL PORT RESET SELECTOR DEFAULT FLL SELECT STOP I
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 2-1. System Clock Generation and Control Registers REGISTER ADDRESS BIT(S) FUNCTION CKCN M8[0Eh] [2:0]—PMME, CD[1:0] 000: System clock = high-frequency clock divided by 1. 001: System clock = high-frequency clock divided by 2. 010: System clock = high-frequency clock divided by 4. 011: System clock = high-frequency clock divided by 8. 1xx: System clock = high-frequency clock/256.
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MAXQ Family User’s Guide: MAXQ2010 Supplement When the system clock source is switched back from the FLL to the high-frequency oscillator by clearing FLLSL to zero, the FLL is still used as the system clock source until the warmup period has completed for the high-frequency oscillator. This is reflected by the value of the FLLMD bit, which remains at 1 until the warmup for the high-frequency oscillator has completed and the clock switches over, at which point FLLMD switches to 0. 2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 2-2. Interrupt Sources and Control Bits (continued) INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG External Interrupt 13 (P5.5) IM1 (IMR.1) EX13 (EIE1.5) IE13 (EIF1.5) External Interrupt 14 (P5.6) IM1 (IMR.1) EX14 (EIE1.6) IE14 (EIF1.6) External Interrupt 15 (P6.0) IM1 (IMR.1) EX15 (EIE2.0) IE15 (EIF2.0) External Interrupt 16 (P6.1) IM1 (IMR.1) EX16 (EIE2.1) IE16 (EIF2.1) External Interrupt 17 (P6.2) IM1 (IMR.
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MAXQ Family User’s Guide: MAXQ2010 Supplement SUPPLY AT VDD VRST T1 (T1 = STARTUP TIME FOR FLL) FREQUENCY-LOCKED LOOP T2 INTERNAL RESET (T2 = 65,536 FLL CYCLES, OR 7.84ms AT 8.4MHz) Figure 2-6. Power-On Reset Timing 2.8.1 Power-On Reset When power is first applied to the MAXQ2010, or when the supply voltage at VDD drops below the VRST level, the processor is held in a power-on reset state. See Figure 2-6.
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MAXQ Family User’s Guide: MAXQ2010 Supplement CLOCK RST RESET SAMPLING INTERNAL RESET FIRST INSTRUCTION FETCH Figure 2-7. External Reset Timing Table 2-3. System Power-Management Registers REGISTER ADDRESS BIT FUNCTION 00: System clock = high-frequency clock divided by 1. 01: System clock = high-frequency clock divided by 2. 10: System clock = high-frequency clock divided by 4. 11: System clock = high-frequency clock divided by 8.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 2-3. System Power-Management Registers (continued) REGISTER PWCN PWCN ADDRESS M0[0Fh] M0[0Fh] BIT FUNCTION [9:8]—X32KMD[1:0] Selects operating mode of the 32kHz oscillator as follows. 00: Always operate in noise immune mode. 01: Always operate in quiet mode. 10: Operate in noise immune mode normally and in quiet mode during stop. Wait for 32kHz oscillator warmup upon stop mode exit.
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MAXQ Family User’s Guide: MAXQ2010 Supplement • An ADC conversion is initiated by setting ADCONV to 1. • A ctive debug mode is entered either by a breakpoint match or direct issuance of the debug command from background mode. As described in the MAXQ Family User’s Guide, if any of these conditions is true (a switchback source is active) and the SWB bit has been set, the PMME bit cannot be set to enter power-management mode. 2.9.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 3: PROGRAMMING Refer to Section 3: Programming of the MAXQ Family User’s Guide for examples of general program operations involving the MAXQ core. The MAXQ2010 contains the MAXQ20 (16-bit accumulator version) of the MAXQ core.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS Refer to Section 4: System Register Descriptions of the MAXQ Family User’s Guide for functional descriptions of the registers and bits in Table 4-1. Table 4-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 4-2. System Register Bit Functions (continued) REG BIT 15 14 13 12 11 10 9 8 7 6 5 4 OFFS DPC — — — — — — — GR — — GR.7 BP 1 0 — — GR.6 GR.5 WBS2 WBS1 WBS0 SDPS1 SDPS0 GR.4 GR.3 GR.2 GR.1 GR.0 GR.0 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 GR.7 GR.0 BP (16 bits) GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GRH GRXL 2 GR (16 bits) GRL GRS 3 OFFS (8 bits) GR.7 GR.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 4.1 System Register Descriptions This section details the functionality of any system register contained in the MAXQ2010 that operates differently from its description in the MAXQ Family User’s Guide. Addresses for all system and peripheral registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal).
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MAXQ Family User’s Guide: MAXQ2010 Supplement 4.1.3 System Control Register (SC, M8[08h]) Bit # Name 7 6 5 4 3 2 1 0 TAP — — CDA0 — — PWL — Reset 1 0 0 0 0 0 Unchanged 0 POR 1 0 0 0 0 0 1 0 Access rw r r r r r rw r Bit 7: Test Access (Debug) Port Enable (TAP) 0 = Debug port functions are disabled, and P6.0 to P6.3 can be used as general-purpose I/O pins. 1 = Port pins P6.0 to P6.3 are enabled to act as debug port inputs and outputs.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 4.1.5 System Clock Control Register (CKCN, M8[0Eh]) Bit # 7 6 5 4 3 2 1 0 Name — FLLSL FLLMD STOP SWB PMME CD1 CD0 0 Reset 1 Unchanged 0 0 0 0 0 POR 1 0 0 0 0 0 0 0 Access r rw s rw rw rw rw* rw* *Unrestricted read access. This bit can only be modified when PMME = 0. The CKCN register bit settings determine the system clock source and clock divider as described in Table 4-4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 4-4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES Table 5-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 5-2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 5-2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 5-2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 5-3.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 5-3.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE The MAXQ2010 provides up to 55 port pins for general-purpose I/O that are grouped into logical ports P0 to P6. Each of these port pins has the following features: • CMOS output drivers • Schmitt trigger inputs • Optional weak pullup to DVDD when operating in input mode Many of the port pins on the MAXQ2010 are also multiplexed with special and alternate functions as listed below.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 6-1. Port Pin Special and Alternate Functions (continued) PORT PIN FUNCTION TYPE P2.3 Special Analog LCD Segment SEG19 DPE = 1 and PCF2 = 1 P2.4 Special Analog LCD Segment SEG20 DPE = 1 and PCF2 = 1 P2.5 Special Analog LCD Segment SEG21 DPE = 1 and PCF2 = 1 P2.6 Special Analog LCD Segment SEG22 DPE = 1 and PCF2 = 1 P2.7 Special Analog LCD Segment SEG23 DPE = 1 and PCF2 = 1 P3.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 6-1. Port Pin Special and Alternate Functions (continued) PORT PIN FUNCTION TYPE P5.5 Special P5.6 Alternate P5.6 Special P5.6 FUNCTION ENABLED WHEN SCLK: SPI Clock Output (Master Mode) SPIEN = 1 and MSTM = 1 External Interrupt 14 (EIE1.6) EX14 = 1 MISO: SPI Slave Output (Slave Mode) SPIEN = 1 and MSTM = 0 Alternate MISO: SPI Master Input (Master Mode) SPIEN = 1 and MSTM = 1 P6.0 Alternate JTAG Interface: TAP Clock (TCK) (SC.
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MAXQ Family User’s Guide: MAXQ2010 Supplement The port pins on the MAXQ2010 operate the same as standard MAXQ port pins, with input/output states defined in Table 6-2. Table 6-2. Port Pin Input/Output States (in Standard Mode) PDx.y POx.y PORT PIN MODE 0 0 Input PORT PIN (Px.y) STATE Three-State 0 1 Input Weak pullup high 1 0 Output Strong drive low 1 1 Output Strong drive high 6.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.3 Port 2 Direction Register (PD2, M0[12h]) Bit # 7 6 5 4 Name 3 2 1 0 PD2 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each of the bits in this register controls the input/output direction of a port pin (P2.0 to P2.7) as follows: 0 = The port pin is in input mode, either with a weak pullup (if PO = 1) or three-stated (if PO = 0). 1 = The port pin is in output mode, with the output level to drive given by PO. 6.1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.6 Port 5 Direction Register (PD5, M1[11h]) Bit # 7 Name — 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access r rw rw rw rw rw rw rw PD5 Each of the bits in this register controls the input/output direction of a port pin (P5.0 to P5.6) as follows: 0 = The port pin is in input mode, either with a weak pullup (if PO = 1) or three-stated (if PO = 0). 1 = The port pin is in output mode, with the output level to drive given by PO. 6.1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.10 Port 2 Output Register (PO2, M0[02h]) Bit # 7 6 5 4 Name 3 2 1 0 PO2 Reset 1 1 1 1 1 1 1 1 Access rw rw rw rw rw rw rw rw Bits 7:0: Port 2 Output. This register stores the data that is output on any of the pins of port 2 that have been defined as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.14 Port 6 Output Register (PO6, M1[02h]) Bit # 7 6 5 4 Name 3 2 1 0 PO6 Reset 1 1 1 1 1 1 1 1 Access rw rw rw rw rw rw rw rw Bits 7:0: Port 6 Output. This register stores the data that is output on any of the pins of port 6 that have been defined as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.18 Port 3 Input Register (PI3, M0[0Bh]) Register Name PI3 Register Description Port 3 Input Register Register Address M0[0Bh] Bit # 7 6 5 4 Name 3 2 1 0 PI3 Reset s s s s s s s s Access r r r r r r r r Each of the read-only bits in this register reflects the logic state present at the corresponding port pin. 6.1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.22 External Interrupt Flag 0 Register (EIF0, M0[04h]) Bit # Name 7 6 5 4 3 2 1 0 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register is set when a negative or positive edge (depending on the ITn bit setting) is detected on the corresponding interrupt pin.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.24 External Interrupt Flag 2 Register (EIF2, M1[06h]) Bit # Name 7 6 5 4 3 2 1 0 IE22 IE21 IE20 IE19 IE18 IE17 IE16 IE15 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register is set when a negative or positive edge (depending on the ITn bit setting) is detected on the corresponding interrupt pin.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.26 External Interrupt Enable 1 Register (EIE1, M1[05h]) Bit # 7 6 5 4 3 2 1 0 Name — EX14 EX13 EX12 EX11 EX10 EX9 EX8 Reset 0 0 0 0 0 0 0 0 Access r rw rw rw rw rw rw rw Each bit in this register controls the enable for one external interrupt. If the bit is set to 1, the interrupt is enabled (if it is not otherwise masked). If the bit is set to 0, its corresponding interrupt is disabled.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.28 External Interrupt Edge Select 0 Register (EIES0, M0[0Ch]) Bit # Name 7 6 5 4 3 2 1 0 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register controls the edge select mode for an external interrupt as follows: 0 = The external interrupt triggers on a rising (positive) edge. 1 = The external interrupt triggers on a negative (falling) edge.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.1.30 External Interrupt Edge Select 2 Register (EIES2, M1[0Ch]) Bit # Name 7 6 5 4 3 2 1 0 IT22 IT21 IT20 IT19 IT18 IT17 IT16 IT15 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register controls the edge select mode for an external interrupt as follows: 0 = The external interrupt triggers on a rising (positive) edge. 1 = The external interrupt triggers on a negative (falling) edge.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 6.2.3 External Interrupt Example: Handling Interrupt on INT10/P5.2 move PD5.2, #0 ; Set P5.2 to input mode move move move IV, #intHandler IMR.1, #1 EIE1.2, #1 ; Set interrupt vector ; Enable interrupts for module 1 ; Enable external interrupt 10 move nop nop nop nop EIF1.2, #0 ; Force interrupt flag cleared IC.0, #1 ; Enable interrupts globally move move move PO5.2, #1 EIES1.2, #1 sjump $ intHandler: move EIF1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULE The MAXQ2010 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULE The MAXQ2010 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULE The MAXQ2010 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 10: SERIAL I/O MODULE The MAXQ2010 provides two serial universal synchronous/asynchronous receiver-transmitter (USART) interfaces (serial 0 and 1) that operate as described in the MAXQ Family User’s Guide. 10.1 Serial USART I/O Pins and Control Registers Table 10-1. Serial USART Input and Output Pins SERIAL USART FUNCTION PIN MULTIPLEXED WITH GPIO RX0: Serial 0 Receive 68 P5.0 TX0: Serial 0 Transmit 67 P5.
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MAXQ Family User’s Guide: MAXQ2010 Supplement mainLoop: call RxChar0 call TxChar0 jump mainLoop ;============================================================================== ;= ;= TxChar0 - Outputs a character to serial port 0. ;= ;= Inputs : Acc - Character to send. ;= TxChar0: move SBUF0, Acc TxChar0_Loop: move C, SCON0.1 sjump NC, TxChar0_Loop move SCON0.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE The MAXQ2010 provides a serial peripheral interface (SPI) module, which operates as described in the MAXQ Family User’s Guide. 11.1 SPI Input/Output Pins and Control Registers Table 11-1. SPI Input and Output Pins SPI INTERFACE FUNCTION PIN MULTIPLEXED WITH GPIO SSEL: Slave Select SCLK: Slave Clock 60 P5.3 58 P5.5 MOSI: Master Out-Slave In 59 P5.4 MISO: Master In-Slave Out 57 P5.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 11.2.2 SPI Example 2: Receiving Data in Slave Mode move SPICN, #01h move SPICF, #00h call move call move call move call ; Enable SPI in slave mode ; Sample data at clock rising edge, 8 bit character getByte A[0], GR getByte A[1], GR getByte A[2], GR getByte move A[3], GR ... getByte: move C, SPICN.6 jump NC, getByte move SPICN.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 12: HARDWARE MULTIPLIER MODULE The MAXQ2010 provides a hardware multiplier module that provides the following features (detailed in the MAXQ Family User’s Guide): • Completes a 16-bit x 16-bit multiply-accumulate or multiply-subtract operation in a single cycle • Includes 48-bit accumulator • Supports seven different multiplication operations Unsigned 16-bit multiply Unsigned 16-bit multiply and accumulate Unsigned 16-bit multiply and subtrac
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 13: 1-Wire BUS MASTER The MAXQ2010 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 14: REAL-TIME CLOCK MODULE The MAXQ2010 provides a real-time clock (RTC) that operates as described in the MAXQ Family User’s Guide.
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MAXQ Family User’s Guide: MAXQ2010 Supplement RTCE RDYE WE RTC CONTROL RTRIM COMPENSATION BUSY RDY PRESCALER ASE RSSA 32K_CLK /8 ADE RTSS RAS RTS SQE FT[1:O] ALSF CLOCK OUTPUT GENERATION ALDF COMPARE SQW Figure 14-1. RTC Block Diagram 14.3 RTC Trim Operation The uncompensated accuracy of the RTC is a function of the attached crystal oscillator (and its respective temperature drift characteristics within the end system).
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MAXQ Family User’s Guide: MAXQ2010 Supplement PRESCALER 4096Hz TRIM ADJUSTMENT LOGIC TSGN 256Hz TRIM[3:0] 10-SECOND CLOCK Figure 14-2. RTC Prescaler and Trim AVERAGE = [(1 - 73.2µs) x 9 + (1 + 732µs)]/10 = 1s 1s - 73.2µs 1s - 73.2µs 1s - 73.2µs 1s + 732µs 1Hz OUTPUT TIME (t) 1 2 10 3 11 12 SECONDS ADJUSTMENT MADE HERE (TSGN = 1) Figure 14-3. RTC Trim Adjustment (TSGN = 1) AVERAGE = [(1s + 73.2µs) x 9 + (1 - 732µs)]/10 = 1s 1s + 73.2µs 1s - 732µs 1s + 73.2µs 1s + 73.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 14.4 RTC Register Descriptions Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows: • Name: Symbolic names of bits or bit fields in this register. • R eset: The value of each bit in this register following a standard reset.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bit 15: RTC Write Enable (WE). This register bit serves as a protection mechanism against undesirable writes to the RTCE bit and RTRM register. This bit must be set to a 1 to give write access to the RTRM register and the RTCE bit; otherwise (when WE bit = 0) these protected bits are read-only. Bit 14: Reserved. Read returns 1 after reset, or last written value (when BUSY = 0). Bit 13: Alternate Clock Select (ACS).
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MAXQ Family User’s Guide: MAXQ2010 Supplement 14.4.3 Real-Time Subsecond Counter Register (RTSS, M0[1Ah]) 7 6 5 4 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # Name 3 2 1 0 RTSS Note 1: This register is cleared by power-on reset only. Note 2: Read accessible when RDY = 1. Note 3: Write accessible when RTCE = 0 and BUSY = 0. Bits 7:0: RTC Subsecond Counter Register.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 14.4.6 RTC Subsecond Alarm Register (RSSA, M0[1Dh]) Bit # 7 6 5 4 Name 3 2 1 0 RSSA Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Note: Write accessible when BUSY = 0 and either ASE = 0 or RTCE = 0. Bits 7:0: RTC Subsecond Alarm Register. This register contains the reload value for the subsecond alarm. The ALSF bit is set when an autoreload occurs. 14.4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 14.5 RTC Example: Starting and Setting the Clock move RCNT, #08000h ;RTC write enable call move move move ;Call subroutine to verify RCNT.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP) The JTAG/TAP port on the MAXQ2010 is multiplexed with port pins P6.0, P6.1, P6.2, and P6.3. These pins default to the JTAG/TAP function on reset, which means that the part is always ready for in-circuit debugging or in-circuit programming operations following any reset. Once an application has been loaded and starts running, the JTAG/TAP port can still be used for in-circuit debugging operations.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 16: IN-CIRCUIT DEBUG MODE The MAXQ2010 provides an in-circuit debugging interface through the debug port as described in the MAXQ Family User’s Guide.
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MAXQ Family User’s Guide: MAXQ2010 Supplement • Registers SPIB, I2CBUF, and ADDATA are not read, and their values are returned as 0000h. The first byte output by this command is the value 144 (090h), which represents the number of peripheral register words output. Table 16-1 lists the remaining 352 bytes output by this command. Table 16-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) The MAXQ2010 provides a JTAG-compatible debug port interface for in-system programming (bootloader) operations. In order to use this interface for in-system programming, the SPE bit must be set through the debug port. This is done while the device is held in reset, using the system programming instruction as described in the MAXQ Family User’s Guide. 17.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 17.2 Family 0 Commands (Not Password Protected) Command 00h—No Operation I/O BYTE 1 Input 00h Output Command 01h—Exit Loader This command causes the bootloader command loop to exit. Upon exit, the MAXQ2010 clears the SPE bit and resets itself internally. Following the internal reset, execution jumps to the beginning of application code at address 0000h.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 17-2. Bootloader Status Flags FLAG BIT FUNCTION 0 Password Lock 0 = The password is unlocked or had a default value; password-protected commands can be used. 1 = The password is locked. Password-protected commands cannot be used. 1 Word/Byte Mode 0 = The bootloader is currently in byte mode for memory reads/writes. 1 = The bootloader is currently in word mode for memory reads/writes. (Note: The MAXQ2010 supports byte mode only.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Command 08h—Get Loader Version I/O BYTE 1 BYTE 2 Input 08h 00h Output BYTE 3 BYTE 4 BYTE 5 00h 00h 00h VersionL VersionH 03Eh BYTE 4 BYTE 5 Command 09h—Get Utility ROM Version I/O BYTE 1 BYTE 2 Input 09h 00h Output BYTE 3 00h 00h 00h VersionL VersionH 03Eh Command 0Ah—Set Word/Byte-Mode Access The mode byte should be 0 to set byte-access mode or 1 to set word-access mode.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Command 11h—Load Data Variable Length This command writes (Length) bytes of data into the data SRAM starting at byte address (AddressH:AddressL). I/O BYTE 1 BYTE 2 BYTE 3 BYTE 4 (LENGTH) BYTES BYTE LENGTH+5 Input 11h Length AddressL AddressH Data to load 00h BYTE LENGTH+6 00h 03Eh Output 17.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 17.5 Family 3 Commands: CRC Variable Length (Password Protected) Command 30h—CRC Code Variable Length This command has a slightly different format depending on the length of the CRC requested. It returns the CRC-16 value (CrcH:CrcL) of the program flash - (Length) or (LengthH:LengthL) bytes/words starting at (AddrH:AddrL).
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MAXQ Family User’s Guide: MAXQ2010 Supplement 17.7 Family 5 Commands: Load and Verify Variable Length (Password Protected) Command 50h—Load and Verify Code Variable Length This command combines the functionality of the “Load Code Variable Length” and “Verify Code Variable Length” commands.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDENDUM TO SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY Refer to the MAXQ Family User’s Guide. Table 18-1 from the MAXQ Family User’s Guide is reproduced here. Table 18-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 18-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement SECTION 19: ANALOG-TO-DIGITAL CONVERTER (SPECIFIC TO MAXQ2010) The MAXQ2010 provides a 12-bit, successive approximation analog-to-digital converter (ADC) with an integrated analog multiplexer. The ADC can perform either single-ended conversions from one of eight channels or differential conversions from one of four channel pairs.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 19.2 Analog-to-Digital Pins and Control Registers Tables 19-1 and 19-2 list the pins and control registers dedicated to the ADC. Note that all ADC pins are dedicated, so none of them is multiplexed with GPIO port pins. Addresses for all registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal).
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 19-2. ADC Control Registers (continued) REGISTER ADDRESS FUNCTION ADCFG[4] ADDATA[14h] ADC Sequence Configuration Register 4 ADCFG[5] ADDATA[15h] ADC Sequence Configuration Register 5 ADCFG[6] ADDATA[16h] ADC Sequence Configuration Register 6 ADCFG[7] ADDATA[17h] ADC Sequence Configuration Register 7 ADBUF[0] ADDATA[00h] ADC Sample Buffer Register 0. Read-only register containing ADC conversion result.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bit 7: Internal Reference OK (REFOK). This read-only status bit indicates whether the internal reference is ready for use by the ADC. 0 = The internal reference is either disabled (IREFEN = 0) or is still warming up. 1 = The internal reference is ready for use. Bit 6: ADC Start Conversion (ADCONV). Writing this bit to 1 starts the ADC conversion sequence.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 19.2.2 ADC Conversion Sequence Address Register (ADADDR, M4[07h]) Bit # 15 14 13 12 Name — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r rw* rw* rw* rw* Bit # 7 6 5 4 3 2 1 0 Name — Reset 0 0 0 0 0 0 0 0 Access r rw* rw* rw* r rw* rw* rw* SEQSTART[2:0] 11 10 9 8 SEQSTORE[3:0] — SEQEND[2:0] *Can only be written when ADCONV = 0.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bits 9:8: ADC Clock Divider (ADCLK[1:0]).
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bits 3:0: ADC Sample Acquisition Time Extend (ADACQ[3:0]). These bits set the extended sample acquisition time period. For a given conversion, sample acquisition time is extended if the ADACQEN bit is set in the conversion configuration (ADCFG) register. If this bit is set, the acquisition time is extended by: 16 x (ADACQ[3:0] + 1) x ADC clock period 19.2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 19.2.6 ADC Conversion Configuration Registers (ADCFG[0] to ADCFG[7], ADDATA[10h] to ADDATA[17h]) Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name — ADREF ADACQEN ADALGN ADDIFF ADCH2 ADCH1 ADCH0 Reset 0 0 0 0 0 0 0 0 Access r rw* rw* rw* rw* rw* rw* rw* *Can only be written when ADCONV = 0.
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MAXQ Family User’s Guide: MAXQ2010 Supplement ADDIFF ADCH2 ADCH1 ADCH0 1 X 0 0 Differential conversion: (AN0–AN1) ADC CONVERSION TYPE 1 X 0 1 Differential conversion: (AN2–AN3) 1 X 1 0 Differential conversion: (AN4–AN5) 1 X 1 1 Differential conversion: (AN6–AN7) 19.3 Analog-to-Digital Converter Code Examples 19.3.
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MAXQ Family User’s Guide: MAXQ2010 Supplement move move move move move move move move move move 19-10 A[6], A[7], A[8], A[9], A[10], A[11], A[12], A[13], A[14], A[15], ADDATA ADDATA ADDATA ADDATA ADDATA ADDATA ADDATA ADDATA ADDATA ADDATA
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MAXQ Family User’s Guide: MAXQ2010 Supplement SECTION 20: LCD CONTROLLER (SPECIFIC TO MAXQ2010) 20.1 LCD Controller Overview The MAXQ2010 provides an on-board LCD controller module that can generate segment and common signals for an LCD based on display memory content. Once the LCD controller settings and display memory have been initialized, the LCD segment and common signals are generated automatically at the selected display frequency.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 20.2 LCD Controller Register Descriptions The following peripheral registers are used to control the LCD display controller. Addresses for all registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows: • N ame: Symbolic names of bits or bit fields in this register.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bit 1: Operation Mode (OPM). This bit determines whether the LCD controller is operating (driving SEG and COM lines) or suspended (with its clock gated off). 0 = The LCD controller is suspended. 1 = The LCD controller is in normal operating mode. Bit 0: Display Enable (DPE). When the LCD controller is in normal operating mode, this bit controls whether the display register data is used to drive the LCD.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bits 3:0: LCD Register Adjust (LRA[3:0]). These bits control the resistance of the internal LCD resistor RADJ. The approximate resistance can be determined as: RADJ = LCRA[3:0] x 5.33kI The following registers contain display memory for the LCD controller. 20.2.3 LCD Display Register 0 (LCD0, M2[0Bh]) Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 0 20.2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 20.2.9 LCD Display Register 6 (LCD6, M2[11h]) Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 0 20.2.10 LCD Display Register 7 (LCD7, M2[12h]) Bit # 7 6 5 4 3 2 1 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 0 20.2.11 LCD Display Register 8 (LCD8, M2[13h]) Bit # 7 6 5 4 3 2 1 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 3 2 1 0 20.2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 20.2.15 LCD Display Register 12 (LCD12, M2[17h]) Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 0 20.2.16 LCD Display Register 13 (LCD13, M2[18h]) Bit # 7 6 5 4 3 2 1 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 0 20.2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 20.2.21 LCD Display Register 18 (LCD18, M2[1Dh]) Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 3 2 1 0 20.2.22 LCD Display Register 19 (LCD19, M2[1Eh]) Bit # 7 6 5 4 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 20.2.23 LCD Display Register 20 (LCD20, M2[1Fh]) Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw 20.
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MAXQ Family User’s Guide: MAXQ2010 Supplement STATIC DISPLAY 1/2 BIAS 1/3 BIAS VLCD VLCD R VLCD R R VLCD1 VLCD1 R VLCD1 R R VLCD2 VLCD2 R VLCD2 R R VADJ VADJ RADJ VADJ RADJ LRIG RADJ LRIG DGND LRIG DGND DGND Figure 20-2. LCD Drive Voltage Generation Table 20-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement STATIC DISPLAY STATIC DISPLAY VLCD VLCD R R VLCD1 VLCD1 R R VLCD2 VLCD2 R R VADJ VADJ RADJ REXT RADJ LRIG = 1 LRIG = 0 DGND DGND Figure 20-3. LCD Internal and External Display Contrast Adjustment 20.8 LCD Frame Frequency The LCD controller clock frequency (fLCD) can be sourced from either the 32kHz clock or the high-frequency clock divided by 128 as specified by the LCCS bit.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 20-2. Approximate LCD Frame Frequencies (Hz) (continued) fLCD = 32,768Hz/2 FRM[3:0] fLCD = 19,531Hz (10MHz/512) 1, 1/2, 1/4 1/3 1, 1/2, 1/4 1/3 8 29 19 34 23 9 26 17 31 21 10 24 16 28 19 11 22 14 26 17 12 20 13 24 16 13 19 12 22 15 14 17 12 21 14 15 16 11 19 13 20.9 LCD Display Memory The LCD0 to LCD20 registers provide 21 bytes of display memory.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 20-4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 20-5. LCD Display Memory Map (1/3 Duty) (continued) BIT 6 COM2 BIT 5 COM1 BIT 4 COM0 LCD17 SEG35 SEG35 LCD18 SEG37 SEG37 LCD19 SEG39 SEG39 REGISTER BIT 7 BIT 2 COM2 BIT 1 COM1 BIT 0 COM0 SEG35 SEG34 SEG34 SEG34 SEG37 SEG36 SEG36 SEG36 SEG39 SEG38 SEG38 SEG38 SEG40 SEG40 SEG40 BIT 3 LCD20 Table 20-6.
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MAXQ Family User’s Guide: MAXQ2010 Supplement In x4 multiplexed mode, also known as 1/4 duty cycle mode, each segment pin can drive up to four LCD segments. There are four common backplane signals, driven by COM0, COM1, COM2, and COM3. Each on segment is only driven for 1/4 the frame period. In each of the following examples, the LCD controller is driving a “2” to the display. This is a conventional 7-segment display, and the “2” consists of on segments a, b, d, e, g, and DP as shown in Figure 20-4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 20-7. Static Drive Example Common Signal Selection COM0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 On On On On Off On On Off COM1 COM2 COM3 According to the static memory map table, a value of 0F6h should be written to the LCD0 register as shown in Table 20-8. Table 20-8.
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MAXQ Family User’s Guide: MAXQ2010 Supplement SEG0 SEG1 SEG2 SEG3 COM0 COM1 Figure 20-7. 1/2 Duty Drive Example Display Connection Table 20-9. 1/2 Duty Drive Example Common Signal Selection SEG3 SEG2 SEG1 SEG0 COM0 SEG7 SEG6 SEG5 SEG4 On On On Off COM1 On Off On On COM2 COM3 Table 20-10. 1/2 Duty Drive Example Register Content LCD0 BIT 7 COM1 BIT 6 COM0 BIT 5 COM1 BIT 4 COM0 BIT 3 COM1 BIT 2 COM0 BIT 1 COM1 BIT 0 COM0 1 1 0 1 1 1 1 0 LCD1 LCD2 LCD3 20.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 1 FRAME (fFRAME) COM0 VLCD VLCD1 GND COM1 VLCD VLCD1 GND SEG0 VLCD VLCD1 GND SEG1 VLCD VLCD1 GND SEG2 VLCD VLCD1 GND SEG3 VLCD VLCD1 GND COM0–SEG0 (OFF) VLCD 1/2 VLCD GND -1/2 VLCD -VLCD COM0–SEG1 (ON) VLCD 1/2 VLCD GND -1/2 VLCD -VLCD Figure 20-8. 1/2 Duty Drive Example Waveform Timing COM2 COM1 SEG0 SEG1 Figure 20-9.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Table 20-11. 1/3 Duty Drive Example Common Signal Selection SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 On On On COM1 Off On Off COM2 On On (Don’t Care) COM3 Table 20-12.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 20.14 LCD Controller 1/4 Duty Cycle Drive Example In this example, SEG0 and SEG1 are used to drive the LCD segments. The segments and common signals are connected as shown in Figure 20-11. According to the 1/4 duty drive memory map table, LCD0 should be set to 0D7h as shown in Table 20-14. COM3 COM2 COM1 SEG0 COM0 SEG1 Figure 20-11. 1/4 Duty Drive Example Display Connection Table 20-13.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 1 FRAME (fFRAME) COM0 VLCD VLCD1 VLCD2 GND COM1 VLCD VLCD1 VLCD2 GND COM2 VLCD VLCD1 VLCD2 GND COM3 VLCD VLCD1 VLCD2 GND SEG0 VLCD VLCD1 VLCD2 GND SEG1 VLCD VLCD1 VLCD2 GND COM3–SEG0 (OFF) VLCD 2/3 VLCD 1/3 VLCD GND -1/3 VLCD -2/3 VLCD -VLCD COM3–SEG1 (ON) VLCD 2/3 VLCD 1/3 VLCD GND -1/3 VLCD -2/3 VLCD -VLCD Figure 20-12. 1/4 Duty Drive Example Waveform Timing 20.
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MAXQ Family User’s Guide: MAXQ2010 Supplement SECTION 21: TIMER/COUNTER B MODULE (SPECIFIC TO MAXQ2010) The MAXQ2010 provides three Type B timer/counter modules that operate as described in this section. Table 21-1 and Table 21-2 list the associated pins and registers for these timer/counter modules. Table 21-1. Type B Timer/Counter Input and Output Pins TIMER/COUNTER FUNCTION PIN MULTIPLEXED WITH GPIO TB0A: Timer 0 I/O Pin A 67 P5.1 TB0B: Timer 0 I/O Pin B 68 P5.0 TB1A: Timer 1 I/O Pin A 25 P6.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 21.1 Timer/Counter B Register Descriptions The following peripheral registers are used to control the LCD display controller. Addresses for all registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows: • Name: Symbolic names of bits or bit fields in this register.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 21.1.3 Timer B Timer/Counter 0/1/2 Control Register (TB0CN, TB1CN, TB2CN; M4[08h], M4[0Ah], M4[0Ch]) 15 14 13 12 11 10 9 8 Name C/TB — — TBCS TBCR TBPS2 TBPS1 TBPS0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name TFB EXFB TBOE DCEN EXENB TRB ETB CP/RLB Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # Bit 15: Counter/Timer Select (C/TB).
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bit 5: Timer B Output Enable (TBOE). Setting this bit to 1 enables the clock output function on the TBA pin if C/TB = 0. Timer B rollovers do not cause interrupts. Clearing this bit to 0 allows the TBA pin to function as either a standard port pin or a counter input for Timer B. Bit 4: Down-Count Enable (DCEN). This bit, in conjunction with the TBB pin, controls the direction that Timer B counts in 16-bit autoreload mode.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 21.2 Timer/Counter B Operation Timer/Counter B is a 16-bit programmable device that supports clock input prescaling and set/reset/toggle PWM/output control functionality not found on other MAXQ timer implementations. A new register, TBnC, supports certain PWM/ output control functions in some implementations.
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MAXQ Family User’s Guide: MAXQ2010 Supplement TBnR 0 SYSTEM CLOCK TBPS[2:0] = TBnCN[10:8] 2(2 x TBPS[2:0]) TFB = TBnCN.7 COMPARE C/TB = TBnCN.15 0 /CLK TBnV 1 TBA PIN RELOAD TRB = TBnCN.2 TBB PIN 15 0 FALLING EDGE 15 0000h EXFB = TBnCN.6 EXENB = TBnCN.3 TIMER B INTERRUPT Figure 21-1. Timer B Autoreload Mode Block Diagram SYSTEM CLOCK TBPS[2:0] = TBnCN[10:8] 2(2 x TBPS[2:0]) C/TB = TBnCN.15 0 /CLK 0 TBA PIN 15 CAPTURE TRB = TBnCN.2 TBB PIN TFB = TBnCN.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 21.2.3 Timer B 16-Bit Up/Down Count with Autoreload Mode The 16-bit up/down-count autoreload mode is enabled by clearing the capture/reload bit CP/RLB of the control register (TBnCN.0) to 0 and setting the down-count enable bit, DCEN (TBnCN.4), to 1. This mode is illustrated in Figure 21-3. When DCEN is set to 1, Timer B counts up from 0000h or down from the value contained in the TBnR register as controlled by the state of the TBB pin.
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MAXQ Family User’s Guide: MAXQ2010 Supplement TBnR 0 15 TBPS[2:0] = TBnCN[10:8] SYSTEM CLOCK COMPARE 2(2 x TBPS[2:0]) /CLK TBnV TRB = TBnCN.2 C/TB = TBnCN.15 = 0 0 15 0000h TBA PIN DIVIDE BY 2 TBA PIN TBB PIN FALLING EDGE TIMER INTERRUPT EXFB = TBnCN.6 EXENB = TBnCN.3 Figure 21-4. Timer B Clock Output Mode Block Diagram 21.2.4 Timer B Clock Output Mode Timer B can be configured to drive a clock output on the TBA pin as shown in Figure 21-4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement When the timer is not running (i.e., TRB = 0), the initial output state of the TBB pin is established as low or high, respectively, if the reset function (TBCR = 1,TBCS = 0) or set function (TBCR = 0, TBCS = 1) is configured. Invoking the toggle function does not change the already defined starting state for TBB, thus a fixed high or low starting state can be defined for the toggle mode by first passing through the set or reset mode.
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MAXQ Family User’s Guide: MAXQ2010 Supplement TBnC > TBnR TBnR TBnC < TBnR 0000 TBnC < TBnR TBCS, TBCR = TBB PIN 10 (SET) 01 (SET) 11 (TOGGLE) TBnC > TBnR TBCS, TBCR = TBB PIN 10 (SET) 01 (SET) 11 (TOGGLE) Figure 21-6. Timer B PWM/Output Control Mode Waveform (Count Up) 21.2.7 16-Bit Up/Down Count PWM/Output Control Mode Figure 21-7 shows a functional diagram of the up/down-count PWM/output control mode.
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MAXQ Family User’s Guide: MAXQ2010 Supplement (DOWN-COUNTING RELOAD VALUE) TBnR TBnC 0 SYSTEM CLOCK TBPS[2:0] = TBnCN[10:8] 2(2 x TBPS[2:0]) 15 COMPARE C/TB = TBnCN.15 0 /CLK TBB PIN TBnV 1 TBA PIN TRB = TBnCN.2 0 15 0000h (UP-COUNTING RELOAD VALUE) FALLING EDGE TFB = TBnCN.7 TIMER B INTERRUPT EXFB = TBnCN.6 EXENB = TBnCN.3 Figure 21-7.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 21.2.8 EXENB Control During PWM/Output Control Mode The TBB input function (EXENB = 1) and the PWM/output control function (TBCS:TBCR<>00b) can be enabled at the same time. However, the input function changes slightly when this is done. In this configuration, the detection of a falling edge on the TBB pin results in setting of the EXFB interrupt flag, but does not force an autoreload. 21.3 Timer B Examples 21.3.
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MAXQ Family User’s Guide: MAXQ2010 Supplement SECTION 22 : I2C BUS INTERFACE (SPECIFIC TO MAXQ2010) The MAXQ2010 provides an inter-IC (I2C) communications module that includes master and slave modes. The associated pins and registers for this interface are listed in Table 22-1 and Table 22-2. Table 22-1. I2C Input and Output Pins I2C INTERFACE FUNCTION PIN MULTIPLEXED WITH GPIO SCL: Clock 24 P6.6 SDA: Data 23 P6.7 Table 22-2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 22.1.1.1 I2C Data Read and Write Data for I2C transfer is read and written to this location. The I2C transmit and receive buffers are internally stored separately; however, both are accessed through this buffer. 22.1.1.2 I2C Address Transmission When transmitting an I2C address, the address should be loaded into I2CBUF[6:0]. I2CBUF[7] is ignored and is not part of the I2C address. 22.1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bit 4: I2C Timeout Interrupt Flag (I2CTOI). This bit is set to 1 if either the I2C controller cannot generate a START condition or the I2C SCL low time has expired the timeout value specified in the I2CTO register. This happens when the I2C controller is operating in master mode and some other device on the bus is using the bus or holding SCL low for an extended period of time. This bit must be cleared to 0 by software once set.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Stretch Interrupt Enable (I2CSTRIE). Setting this bit to 1 generates an interrupt to the CPU when the clock stretch interrupt flag is set (I2CSTRI = 1). Clearing this bit disables the clock stretch interrupt from generating. Bit 2: I2C Receive Ready Interrupt Enable (I2CRXIE). Setting this bit to 1 causes an interrupt to the CPU when the receive interrupt flag is set (I2CRXI = 1). Clearing this bit to 0 disables the receive interrupt from generating.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Note that this bit has no effect when the I2C is operating in slave mode (I2CMST = 0) and is reset to 0 when I2CMST = 0 or I2CEN = 0. Also, the I2CSTART and I2CSTOP are mutually exclusive. If both bits are set at the same time, it is considered as an invalid operation and the I2C controller ignores the request and resets both bits to 0. Setting the I2CSTART bit to 1 while I2CSTOP = 1 is an invalid operation and is ignored, leaving the I2CSTART bit cleared to 0.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bits 7:0: I2C Clock Low (I2CCKL[7:0]). These bits define the I2C SCL low period in number of system clock, with bit 7 as the most significant bit. The duration of SCL low time is calculated using the following equation: I2C Low Time Period = System Clock x (I2CCKL[7:0] + 1) When operating in master mode, I2CCKL must be set to a minimum value of 4 to ensure proper operation. Any value less than 4 is set to 4. 22.1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 22.2 I2C Code Examples 22.2.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 22.2.3 I2C Example 3: Slave Mode Receive ; I2C configured as slave with address 1ah ; Setup for Slave Mode Receive move move call I2CSLA, #01ah I2CCN, #0001h wait_start ; ; ; ; I2C Slave Address = 01ah I2CEN = 1, I2CMST = 0, I2CMODE = 0, I2CSTART = 0 Polling routine to wait for I2CSTART to be set, indicating a received START ;; Check for address match move and cmp jump move call ACC, I2CST #0020h #0020h ne, no_match I2CIE.
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MAXQ Family User’s Guide: MAXQ2010 Supplement SECTION 23: SUPPLY VOLTAGE MONITOR AND POWER CONTROL (SPECIFIC TO MAXQ2010) The MAXQ2010 provides a number of features to allow monitoring and control of its on-board power supplies. The supply voltage monitor register (SVM) monitors the DVDD power supply and can alert the processor through an interrupt if DVDD falls below a programmable threshold.
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MAXQ Family User’s Guide: MAXQ2010 Supplement Bits 14:10: Reserved Bits 9:8: 32kHz Oscillator Mode (32KMD[1:0]). These two bits determine the 32kHz oscillator operating mode as follows: • 32KMD[1:0] = 00b: Always operate in noise immune mode. • 32KMD[1:0] = 01b: Always operate in quiet mode. • 3 2KMD[1:0] = 10b: Operate in noise immune mode normally and switch to quiet mode on stop mode entry. Wait for the 32kHz oscillator to warm up before exiting stop mode.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 23.1.2 Supply Voltage Monitor Register (SVM, M1[0Dh]) Bit # 15 14 13 12 11 10 9 8 Name — — — — SVTH3 SVTH2 SVTH1 SVTH0 Reset 0 0 0 0 0 1 1 1 Access r r r r rw* rw* rw* rw* Bit # 7 6 5 4 3 2 1 0 Name — — — SVMSTOP SVMI SVMIE SVMRDY SVMEN Reset 0 0 0 0 0 0 0 0 Access r r r rw rw rw r rw *SVTH[3:0] can only be written when the SVM is not running (SVMEN = 0).
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MAXQ Family User’s Guide: MAXQ2010 Supplement SECTION 24: UTILITY ROM (SPECIFIC TO MAXQ2010) 24.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 24.2 In-Application Programming Functions 24.2.1 UROM_flashWrite Function: UROM_flashWrite Summary: Inputs: Programs a single word of flash memory. Outputs: Carry: Set on error and cleared on success. Destroys: PSF, LC[1] A[0]: Word address in program flash memory to write to. A[1]: Word value to write to flash memory. Notes: • This function uses one stack level to save and restore values.
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MAXQ Family User’s Guide: MAXQ2010 Supplement PROGRAM SPACE DATA SPACE (BYTE MODE, CDA0 = 0) FFFFh DATA SPACE (BYTE MODE, CDA0 = 1) FFFFh DATA SPACE (WORD MODE) FFFFh FFFFh A3FFh 1K x 16 DATA SRAM EXECUTING FROM A000h 32K x 8 LOWER HALF (PAGE 0) OF PROGRAM FLASH MEMORY 32K x 8 UPPER HALF (PAGE 1) OF PROGRAM FLASH MEMORY 32K x 16 PROGRAM FLASH 87FFh 2K x 16 UTILITY ROM 8000h 8000h 8000h 8000h 7FFFh 16K x 16 PROGRAM FLASH (PAGE 1) 4000h 3FFFh 16K x 16 PROGRAM FLASH (PAGE 0) 07FFh 0000h 07
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MAXQ Family User’s Guide: MAXQ2010 Supplement 24.3.1 UROM_moveDP0 Function: UROM_moveDP0 Summary: Reads the byte/word value pointed to by DP[0]. Inputs: DP[0]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 24-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 24.3.4 UROM_moveDP1 Function: UROM_moveDP1 Summary: Reads the byte/word value pointed to by DP[1]. Inputs: DP[1]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 24-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 24.3.7 UROM_moveBP Function: UROM_moveBP Summary: Reads the byte/word value pointed to by BP[OFFS]. Inputs: BP[OFFS]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 24-1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 24.3.10 UROM_copyBuffer Function: UROM_copyBuffer Summary: Inputs: Copies LC[0] bytes/words (up to 256) from DP[0] to BP[OFFS]. Outputs: Destroys: DP[0]: Address to copy from. BP[OFFS]: Address to copy to. LC[0]: Number of bytes or words to copy. OFFS is incremented by LC[0]. DP[0] is incremented by LC[0]. LC[0] Notes: • T his function can be used to copy from program flash to data RAM, or from one part of data RAM to another.
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MAXQ Family User’s Guide: MAXQ2010 Supplement 24.4.
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MAXQ Family User’s Guide: MAXQ2010 Supplement APPENDIX 1: SAMPLE MAXQ2010 DEVICE INCLUDE FILE FOR MAX-IDE #define #define #define #define #define #define ; ; #define #define #define #define #define ; ; #define PO0 PO1 PO2 PO3 EIF0 EIE0 M0[00h] M0[01h] M0[02h] M0[03h] M0[04h] M0[05h] M0[06h] M0[07h] M0[08h] M0[09h] M0[0Ah] M0[0Bh] M0[0Ch] M0[0Dh] M0[0Eh] M0[0Fh] ; ; ; ; ; ; Port 0 Output Port 1 Output Port 2 Output Port 3 Output External Interrupt Flag 0 External Interrupt Enable 0 ; ; ; ; ; Port 0 Inp
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MAXQ Family User’s Guide: MAXQ2010 Supplement #define #define #define ; ; #define #define #define ; ; #define #define #define EIES1 EIES2 SVM #define #define #define #define #define #define #define ; #define #define #define #define #define #define #define #define MCNT MA MB MC2 MC1 MC0 LCFG #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define A1-2 M1[0Bh] M1[0Ch] M1[0Dh] M1[0Eh] M1[0Fh] M1[10h] M1[11h] M1[12h] M1[13h] M1[14h] M
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MAXQ Family User’s Guide: MAXQ2010 Supplement #define #define #define ; #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define I2CBUF I2CST I2CIE SCON0 SBUF0 SCON1 SBUF1 SMD0 PR0 SMD1 PR1 I2CCN I2CCK I2CTO I2CSLA TB0R TB0C TB1R TB1C TB2R TB2C ADST ADADDR TB0CN TB0V TB1CN TB1V TB2CN TB2V ADCN ADDATA #define NUL M3[00h] M3[01h] M3[02h] M3[0
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MAXQ Family User’s Guide: MAXQ2010 Supplement INDX_moveDP1inc INDX_moveDP1dec INDX_moveBP INDX_moveBPinc INDX_moveBPdec INDX_copyBuffer INDX_stopMode equ equ equ equ equ equ equ 7 8 9 10 11 12 13 ;====================================================================== ;= ;= Utility ROM Entry Points (MAXQ2010 Loader 1.
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MAXQ Family User’s Guide: MAXQ2010 Supplement REVISION HISTORY REVISION NUMBER REVISION DATE SECTION NUMBER 0 6/09 — DESCRIPTION Initial release. PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.