Users Guide: MAXQ8913 Supplement User guide

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Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

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EVALUATION KIT AVAILABLE

MAXQ FAMILY USER’S GUIDE:

MAXQ8913 SUPPLEMENT

Rev 0; 8/09

10-BIT

DAC

MAXQ8913

OUTA

AIN2

INA-

INA+

DAC1

RIN+

RIN-

OUTB

AIN3

INB-

INB+

OUTC

AIN4

INC-

INC+

OUTD

REFA

DAC3

AIN5

REF

AVDD

AIN6

CURRENT SINK

8-BIT

IND-

IND+

AIN0

AIN1

HFXIN

HFXOUT

SINK1

AIN2

AIN3

AIN4

AIN5

AIN6

12-BIT

SAR DAC

8-BIT DAC

1.5V

REFERENCE

MUX

TEMP

SENSOR

FLASH

64KB

SRAM

4KB

UTILITY ROM

4KB

CLOCK GENERATOR

RC OSC, HF CRYSTAL OSC,

1MHz RING OSC

DAC4

CURRENT SINK

8-BIT

SINK2

8-BIT DAC

MAXQ20

16-BIT RISC

CORE

CLASS

D-AMP

CONTROL

WATCHDOG

TIMER

POWER-ON

RESET,

BROWNOUT

MONITOR

1.8V CORE

LDO REG

AGND

JTAG

16 x 16

HARDWARE MULTIPLY

ACCUMULATE UNIT

4-WIRE

(SPI)

INTERFACE

PORT 0

AND

INTERRUPT

REG18

SYNCIN

FAULT

SHDNR

SHDNL

DVDD

DGND

AVDD

AGND

RST

P0.0/INT0/TCK

P0.1/INT1/TDI

P0.2/INT2/TMS

P0.3/INT3/TDO

P0.4/INT4/SSEL

P0.5/INT5/SCLK

P0.6/INT6/MOSI

P0.7/INT7/MISO

USART

TIMER B

PORT 1

AND

INTERRUPT

P1.0/INT8/SCL/TX

P1.1/INT9/SDA/RX

P1.2/INT10/TB0A

P1.3/INT11/TB0B

10-BIT

DAC

DAC2

LIN+

LIN-

Summary of content (114 pages)

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EVALUATION KIT AVAILABLE MAXQ FAMILY USER’S GUIDE: MAXQ8913 SUPPLEMENT OUTA MAXQ20 16-BIT RISC CORE INAAIN2 INA+ DAC1 OUTB INB- RIN+ RIN- 10-BIT DAC AIN3 INB+ OUTC INC- DAC2 AIN4 INC+ LIN+ LIN- 10-BIT DAC OUTD INDAIN5 IND+ 1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement TABLE OF CONTENTS ADDENDUM TO SECTION 1: OVERVIEW 1-1 1.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ADDENDUM TO SECTION 2: ARCHITECTURE 2-1 2.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement TABLE OF CONTENTS (continued) 6.1.3 Port 0 Input Disable Register (PID0, M0[0Dh]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.4 Port 0 Output Register (PO0, M0[00h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.5 Port 1 Output Register (PO1, M0[01h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ8913 Supplement TABLE OF CONTENTS (continued) ADDENDUM TO SECTION 16: IN-CIRCUIT DEBUG MODE 16-1 16.1 Register Read and Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2 Data Memory Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.3 Data Memory Write Command . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ8913 Supplement TABLE OF CONTENTS (continued) SECTION 21: TIMER/COUNTER B MODULE (SPECIFIC TO MAXQ8913) 21-1 21.1 Timer/Counter B Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1 Timer B Timer/Counter Capture/Reload Register (TBR, M2[07h]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.2 Timer B Timer/Counter Compare Register (TBC, M2[0Bh]) . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ8913 Supplement TABLE OF CONTENTS (continued) SECTION 24: INPUT/OUTPUT AMPLIFIERS (SPECIFIC TO MAXQ8913) 24-1 24.1 Input/Output Amplifier Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.2 Amplifier Control Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement LIST OF FIGURES Figure 2-1. MAXQ8913 System and Peripheral Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2-2. Memory Map When Executing from Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-3. Memory Map When Executing from Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-4.
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MAXQ Family User’s Guide: MAXQ8913 Supplement LIST OF TABLES Table 2-1. System Clock Generation and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Table 2-2. Interrupt Sources and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Table 2-3. System Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 1: OVERVIEW This document is provided as a supplement to the MAXQ Family User’s Guide, covering new or modified features specific to the MAXQ8913. This document must be used in conjunction with the MAXQ Family User’s Guide, available on our website at www.maxim-ic.com/MAXQUG. Addenda are arranged by section number, which correspond to sections in the MAXQ Family User’s Guide.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 2: ARCHITECTURE The MAXQ8913 shares the common architecture features with other members of the MAXQ microcontroller family. Details are discussed in the following sections. 2.1 Instruction Set This device uses the standard 16-bit MAXQ20 core instruction set as described in the MAXQ Family User’s Guide. 2.2 Harvard Memory Architecture Program memory, data memory, and register space follow the Harvard architecture model.
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MAXQ Family User’s Guide: MAXQ8913 Supplement REGISTER MODULE M1 M2 M3 M8 M9 PO0 SCON MCNT ADST AP A[O] O1h PO1 SBUF MA ADADDR APC A[1] SP O2h EIFO SPICN0 MB DAC1OUT A[2] IV O3h EIEO SPIB0 MC2 DAC2OUT A[3] M12 M13 M14 M15 OFFS DP[O] IP PFX DPC O4h EIF1 I2CCN MC1 DAC3OUT PSF A[4] O5h EIE1 I2CST MC0 DAC4OUT IC A[5] O6h SVM I2CBUF TB0CN AMPCN IMR A[6] LC[0] GRL I2CIE TBOR ISINKCN A[7] LC[1] BP O7h REGISTER INDEX M4 M11 M0 OOh A[8] GRS
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MAXQ Family User’s Guide: MAXQ8913 Supplement 2.4 Memory Organization As with all MAXQ microcontrollers, the MAXQ8913 contains logically separate program and data memory spaces. All memory is internal, and physical memory segments (other than the stack and register memories) can be accessed as either program memory or as data memory, but not both at once. The MAXQ8913 contains the following physical memory segments. 2.4.
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MAXQ Family User’s Guide: MAXQ8913 Supplement DATA SPACE (BYTE MODE) PROGRAM SPACE FFFFh 2K x 16 DATA SRAM DATA SPACE (WORD MODE) FFFFh FFFFh 8FFFh 87FFh A7FFh A000h 87FFh 4K x 8 UTILITY ROM 2K x 16 UTILITY ROM 2K x 16 UTILITY ROM 8000h 8000h 8000h EXECUTING FROM 7FFFh 32K x 16 PROGRAM FLASH 0000h 4K x 8 DATA SRAM 0FFFh 2K x 16 DATA SRAM 0000h 07FFh 0000h Figure 2-2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement PROGRAM SPACE DATA SPACE (BYTE MODE, CDA0 = 0) EXECUTING FROM FFFFh DATA SPACE (BYTE MODE, CDA0 = 1) DATA SPACE (WORD MODE) FFFFh FFFFh FFFFh 8FFFh 8FFFh 87FFh A7FFh 2K x 16 DATA SRAM A000h 87FFh 2K x 16 UTILITY ROM 2K x 8 UTILITY ROM 4K x 8 UTILITY ROM 4K x 8 UTILITY ROM 8000h 8000h 8000h 8000h 7FFFh 7FFFh 7FFFh 7FFFh 16K x 16 PROGRAM FLASH (PAGE 1) 4000h 3FFFh 16K x 16 PROGRAM FLASH (PAGE 0) 32K x 8 LOWER HALF (PAGE 0) OF PROGRAM FLAS
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MAXQ Family User’s Guide: MAXQ8913 Supplement POWER-ON RESET RESET STOP XDOG STARTUP TIMER RWT RESET DOG XDOG COUNT RESET WATCHDOG TIMER WATCHDOG RESET WATCHDOG INTERRUPT XDOG DONE CLK INPUT CRYSTAL KLL HF CRYSTAL MAXQ8913 POWER-ON RESET CLOCK DIVIDER ENABLE CLOCK GENERATION SYSTEM CLOCK DIV 1 DIV 2 DIV 4 DIV 8 PMM ENABLE GLITCH-FREE MUX 1MHz INTERNAL RING OSC GLITCH-FREE MUX STOP SWB SWITCHBACK SOURCES RESET SELECTOR DEFAULT RING SELECT STOP INPUT CRYSTAL MONITOR RGSL ENABLE RG
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 2-1. System Clock Generation and Control Registers REGISTER ADDRESS BIT(S) FUNCTION CKCN M8[0Eh] [2:0]—PMME, CD[1:0] 000: System clock = high-frequency clock divided by 1. 001: System clock = high-frequency clock divided by 2. 010: System clock = high-frequency clock divided by 4. 011: System clock = high-frequency clock divided by 8. 1xx: System clock = high-frequency clock/256.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 2-2. Interrupt Sources and Control Bits MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG Watchdog Interrupt INTERRUPT IMS (IMR.7) EWDI (WDCN.6) WDIF (WDCN.3) External Interrupt 0 (P0.0) IM0 (IMR.0) EX0 (EIE0.0) IE0 (EIF0.0) External Interrupt 1 (P0.1) IM0 (IMR.0) EX1 (EIE0.1) IE1 (EIF0.1) External Interrupt 2 (P0.2) IM0 (IMR.0) EX2 (EIE0.2) IE2 (EIF0.2) External Interrupt 3 (P0.3) IM0 (IMR.0) EX3 (EIE0.3) IE3 (EIF0.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SUPPLY AT VDVDD VRST T1 T1 = STARTUP TIME PLUS 10 RING OSCILLATOR CYCLES 1MHz RING OSCILLATOR INTERNAL RESET T2 T2 = 8192 EXTERNAL OSCILLATOR CYCLES RGMD Figure 2-6. Power-On Reset Timing 2.8.1 Power-On Reset When power is first applied to the MAXQ8913, or when the supply voltage at DVDD drops below the VRST level, the processor is held in a power-on reset state. See Figure 2-6.
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MAXQ Family User’s Guide: MAXQ8913 Supplement CLOCK RST RESET SAMPLING INTERNAL RESET FIRST INSTRUCTION FETCH Figure 2-7. External Reset Timing 2.9 Power-Management Features The MAXQ8913 provides the following features to assist in power management: • Divide-by-256 (PMM) mode to reduce current consumption. • Switchback mode to exit PMM mode automatically when rapid processing is required. • Ultra-low-power stop mode. • Selective regulator and brownout detection disable during stop mode.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 2.9.1 Divide-by-256 Mode (PMM) In this power-management mode, all operations continue as normal, but at a reduced clock rate (the selected clock source divided by 256). This power-management mode is entered by setting the PMME bit (CKCN.2) to 1 and CD[1:0] to 0. When PMM mode is exited (either by clearing the PMME bit or as a result of a switchback trigger), system operation reverts to divideby-1 mode. 2.9.
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MAXQ Family User’s Guide: MAXQ8913 Supplement When the processor exits stop mode, program execution resumes using the previously selected clock source following a 10-ring oscillator cycle delay plus any additional delay time required to enable the internal regulator and other circuitry (refer to the IC data sheet for details). • If RGSL = 1, the processor continues running from the ring oscillator indefinitely.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 3: PROGRAMMING Refer to Section 3: Programming of the MAXQ Family User’s Guide for examples of general program operations involving the MAXQ core. The MAXQ8913 contains the MAXQ20 (16-bit accumulator version) of the MAXQ core.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 4: SYSTEM REGISTER DESCRIPTIONS Refer to Section 4: System Register Descriptions of the MAXQ Family User’s Guide for functional descriptions of the registers and bits in Table 4-1. Table 4-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 4-2. System Register Bit Functions (continued) REG BIT 15 14 13 12 11 10 9 8 7 6 5 4 OFFS DPC — — — — — — — GR — — GR.7 BP 1 0 — — GR.6 GR.5 WBS2 WBS1 WBS0 SDPS1 SDPS0 GR.4 GR.3 GR.2 GR.1 GR.0 GR.0 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 GR.7 GR.0 BP (16 bits) GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GRH GRXL 2 GR (16 bits) GRL GRS 3 OFFS (8 bits) GR.7 GR.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 4.1 System Register Descriptions This section details the functionality of any system register contained in the MAXQ8913 that operates differently from its description in the MAXQ Family User’s Guide. Addresses for all system and peripheral registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal).
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MAXQ Family User’s Guide: MAXQ8913 Supplement 4.1.3 System Control Register (SC, M8[08h]) 7 6 5 4 3 2 1 0 Name TAP — — CDA0 — — PWL — Reset 1 0 0 0 0 0 Unchanged 0 POR 1 0 0 0 0 0 1 0 Access rw r r r r r rw r Bit # Bit 7: Test Access (Debug) Port Enable (TAP) 0 = Debug port functions are disabled, and P0.0 to P0.3 can be used as general-purpose I/O pins. 1 = Port pins P0.0 to P0.3 are enabled to act as debug port (JTAG) inputs and outputs.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 4.1.5 System Clock Control Register (CKCN, M8[0Eh]) Bit # 7 6 5 4 3 2 1 0 Name — RGSL RGMD STOP SWB PMME CD1 CD0 Reset 1 0 0 0 0 0 0 0 Access r rw r rw rw rw rw* rw* *Unrestricted read access. This bit can only be modified when PMME = 0. The CKCN register bit settings determine the system clock source and clock divider as described in Table 4-4.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 4-4.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULES Table 5-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 5-2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 5-2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 5-3.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE The MAXQ8913 provides up to 12 port pins for general-purpose I/O that are grouped into logical ports P0 and P1. Each of these port pins has the following features: • CMOS output drivers • Schmitt trigger inputs • Optional weak pullup to DVDD when operating in input mode For the eight GPIO pins located in port 0 (P0.0 to P0.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 6-1. Port Pin Special and Alternate Functions (continued) PORT PIN FUNCTION TYPE FUNCTION ENABLED WHEN Mode 0: REN set to 1 (until serial transmission completes) Mode 1/2/3: SBUF is written (until serial transmission completes) P1.1 Special Serial Port 0 Transmit/Clock P1.1 Special SDA—I2C Data Line I2CEN = 1 (overrides serial port Tx) P1.2 Alternate External Interrupt 10 (EIE1.2) EX10 = 1 P1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 6.1 GPIO and External Interrupt Register Descriptions The following peripheral registers are used to control the general-purpose I/O and external interrupt features specific to the MAXQ8913. Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal).
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MAXQ Family User’s Guide: MAXQ8913 Supplement 6.1.4 Port 0 Output Register (PO0, M0[00h]) 7 6 5 4 Reset 1 1 1 1 1 1 1 1 Access rw rw rw rw rw rw rw rw Bit # Name 3 2 1 0 PO0 This register stores the data that is output on any of the pins of port 0 that have been defined as output pins. If the port pins are in input mode, this register controls the weak pullup for each pin.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 6.1.8 External Interrupt Flag 0 Register (EIF0, M0[02h]) 7 6 5 4 3 2 1 0 Name IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # Each bit in this register is set when a negative or positive edge (depending on the ITn bit setting) is detected on the corresponding interrupt pin.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 6.1.10 External Interrupt Enable 0 Register (EIE0, M0[03h]) Bit # Name 7 6 5 4 3 2 1 0 EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register controls the enable for one external interrupt. If the bit is set to 1, the interrupt is enabled (if it is not otherwise masked). If the bit is set to 0, its corresponding interrupt is disabled.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 6.1.12 External Interrupt Edge Select 0 Register (EIES0, M0[0Ah]) Bit # Name 7 6 5 4 3 2 1 0 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register controls the edge select mode for an external interrupt as follows: 0 = The external interrupt triggers on a rising (positive) edge. 1 = The external interrupt triggers on a negative (falling) edge.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 6.2 Port Pin Examples 6.2.1 Port Pin Example 1: Driving Outputs on Port 0 move PO0, #000h move PD0, #0FFh ; Set all outputs low ; Set all P0 pins to output mode 6.2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULE The MAXQ8913 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 8: TIMER/COUNTER 1 MODULE The MAXQ8913 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 9: TIMER/COUNTER 2 MODULE The MAXQ8913 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 10: SERIAL I/O MODULE The MAXQ8913 provides one serial universal synchronous/asynchronous receiver-transmitter (USART) interface that operates as described in the MAXQ Family User’s Guide. 10.1 Serial USART I/O Pins and Control Registers Table 10-1. Serial USART Input and Output Pins SERIAL USART FUNCTION PIN MULTIPLEXED WITH GPIO RX: Serial Receive M3 P1.1 TX: Serial Transmit N4 P1.0 Table 10-2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ;============================================================================== ;= ;= TxChar - Outputs a character to serial port. ;= ;= Inputs : Acc - Character to send. ;= TxChar: move SBUF, Acc TxChar_Loop: move C, SCON.1 sjump NC, TxChar_Loop move SCON.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE The MAXQ8913 provides a serial peripheral interface (SPI) module, which operates as described in the MAXQ Family User’s Guide with the following additions: • The maximum clock rate when operating in slave mode is the system clock divided by 4. • T he SPI configuration register (SPICF) contains an additional bit, slave active select (SAS, SPICF.6).
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MAXQ Family User’s Guide: MAXQ8913 Supplement 11.2.2 SPI Example 2: Receiving Data in Slave Mode move SPICN, #01h move SPICF, #00h call move call move call move call ; Enable SPI in slave mode ; Sample data at clock rising edge, 8 bit character getByte A[0], GR getByte A[1], GR getByte A[2], GR getByte move A[3], GR ... getByte: move C, SPICN.6 jump NC, getByte move SPICN.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 12: HARDWARE MULTIPLIER MODULE The MAXQ8913 provides a hardware multiplier module that provides the following features (detailed in the MAXQ Family User’s Guide): • Completes a 16-bit x 16-bit multiply-accumulate or multiply-subtract operation in a single cycle • Includes 48-bit accumulator • Supports seven different multiplication operations: Unsigned 16-bit multiply Unsigned 16-bit multiply and accumulate Unsigned 16-bit multiply and subtra
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 13: 1-Wire BUS MASTER The MAXQ8913 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 14: REAL-TIME CLOCK MODULE The MAXQ8913 does not provide this peripheral module.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP) The JTAG/TAP port on the MAXQ8913 is multiplexed with port pins P0.0, P0.1, P0.2, and P0.3. These pins default to the JTAG/TAP function on reset, which means that the part is always ready for in-circuit debugging or in-circuit programming operations following any reset. Once an application has been loaded and starts running, the JTAG/TAP port can still be used for in-circuit debugging operations.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 16: IN-CIRCUIT DEBUG MODE The MAXQ8913 provides an in-circuit debugging interface through the debug port as described in the MAXQ Family User’s Guide.
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MAXQ Family User’s Guide: MAXQ8913 Supplement The first byte output by this command is the value 160 (0A0h), which represents the number of peripheral register words output. Table 16-1 lists the remaining 352 bytes output by this command. Values shown as “—” are don’t care values that should be ignored by the debugging host. Table 16-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) The MAXQ8913 provides a JTAG-compatible debug port interface for in-system programming (bootloader) operations. In order to use this interface for in-system programming, the SPE bit must be set through the debug port. This is done while the device is held in reset, using the system programming instruction as described in the MAXQ Family User’s Guide. 17.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 17.2 Family 0 Commands (Not Password Protected) Command 00h—No Operation I/O BYTE 1 Input 00h Output Command 01h—Exit Loader This command causes the bootloader command loop to exit. Upon exit, the MAXQ8913 clears the SPE bit and resets itself internally. Following the internal reset, execution jumps to the beginning of application code at address 0000h.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 17-2. Bootloader Status Flags FLAG BIT FUNCTION 0 Password Lock 0 = The password is unlocked or had a default value; password-protected commands can be used. 1 = The password is locked. Password-protected commands cannot be used. 1 Word/Byte Mode 0 = The bootloader is currently in byte mode for memory reads/writes. 1 = The bootloader is currently in word mode for memory reads/writes. (Note: The MAXQ8913 supports byte mode only.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Command 08h—Get Loader Version I/O BYTE 1 BYTE 2 Input 08h 00h Output BYTE 3 BYTE 4 BYTE 5 00h 00h 00h VersionL VersionH 03Eh BYTE 4 BYTE 5 Command 09h—Get Utility ROM Version I/O BYTE 1 BYTE 2 Input 09h 00h Output BYTE 3 00h 00h 00h VersionL VersionH 03Eh Command 0Ah—Set Word/Byte-Mode Access The mode byte should be 0 to set byte-access mode or 1 to set word-access mode.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Command 11h—Load Data Variable Length This command writes (Length) bytes of data into the data SRAM starting at byte address (AddressH:AddressL). I/O BYTE 1 BYTE 2 BYTE 3 BYTE 4 (LENGTH) BYTES BYTE LENGTH+5 Input 11h Length AddressL AddressH Data to load 00h BYTE LENGTH+6 00h 03Eh Output 17.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 17.5 Family 3 Commands: CRC Variable Length (Password Protected) Command 30h—CRC Code Variable Length This command has a slightly different format depending on the length of the CRC requested. It returns the CRC-16 value (CrcH:CrcL) of the program flash: (Length) or (LengthH:LengthL) bytes/words starting at (AddrH:AddrL).
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MAXQ Family User’s Guide: MAXQ8913 Supplement 17.7 Family 5 Commands: Load and Verify Variable Length (Password Protected) Command 50h—Load and Verify Code Variable Length This command combines the functionality of the “Load Code Variable Length” and “Verify Code Variable Length” commands.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDENDUM TO SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY Refer to the MAXQ Family User’s Guide. Table 18-1 from the MAXQ Family User’s Guide is reproduced here. Table 18-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 18-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SECTION 19: ANALOG-TO-DIGITAL CONVERTER (SPECIFIC TO MAXQ8913) The MAXQ8913 provides a 12-bit, successive approximation analog-to-digital converter (ADC) with an integrated analog multiplexer. The ADC can perform either single-ended conversions from one of six external input channels (and an additional channel reserved for an internal temperature sensor) or differential conversions from one of three external channel pairs.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 19.2 Analog-to-Digital Pins and Control Registers Tables 19-1 and 19-2 list the pins and control registers dedicated to the ADC. Note that all ADC pins are dedicated, so none of them is multiplexed with GPIO port pins. Addresses for all registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the register index (from 00h to 1Fh hexadecimal).
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MAXQ Family User’s Guide: MAXQ8913 Supplement Table 19-2. ADC Control Registers (continued) REGISTER ADDRESS ADCFG[6] ADDATA[16h] ADC Sequence Configuration Register 6 ADCFG[7] ADDATA[17h] ADC Sequence Configuration Register 7 ADBUF[0] ADDATA[00h] ADC Sample Buffer Register 0. Read-only register containing ADC conversion result. ADBUF[1] ADDATA[01h] ADC Sample Buffer Register 1. Read-only register containing ADC conversion result. ADBUF[2] ADDATA[02h] ADC Sample Buffer Register 2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bit 7: Internal Reference OK (REFOK). This read-only status bit indicates whether the internal reference is ready for use by the ADC. 0 = The internal reference is either disabled (IREFEN = 0) or is still warming up. 1 = The internal reference is ready for use. Bit 6: ADC Start Conversion (ADCONV). Writing this bit to 1 starts the ADC conversion sequence.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 19.2.2 ADC Conversion Sequence Address Register (ADADDR, M3[01h]) Bit # 15 14 13 12 Name — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r rw* rw* rw* rw* Bit # 7 6 5 4 3 2 1 0 Name — Reset 0 0 0 0 0 0 0 0 Access r rw* rw* rw* r rw* rw* rw* SEQSTART[2:0] 11 10 9 8 SEQSTORE[3:0] — SEQEND[2:0] *Can only be written when ADCONV = 0.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bits 9:8: ADC Clock Divider (ADCLK[1:0]).
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bits 3:0: ADC Sample Acquisition Time Extend (ADACQ[3:0]). These bits set the extended sample acquisition time period. For a given conversion, sample acquisition time is extended if the ADACQEN bit is set in the conversion configuration (ADCFG) register. If this bit is set, the acquisition time is extended by: 16 x (ADACQ[3:0] + 1) x ADC clock period 19.2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 19.2.6 ADC Conversion Configuration Registers (ADCFG[0] to ADCFG[7], ADDATA[10h] to ADDATA[17h]) Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name — ADREF ADACQEN ADALGN ADDIFF ADCH2 ADCH1 ADCH0 Reset 0 0 0 0 0 0 0 0 Access r rw* rw* rw* rw* rw* rw* rw* *Can only be written when ADCONV = 0.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ADDIFF ADCH2 ADCH1 ADCH0 1 X 0 0 Differential conversion: (AIN0, AIN1) ADC CONVERSION TYPE 1 X 0 1 Differential conversion: (AIN2, AIN3) 1 X 1 0 Differential conversion: (AIN4, AIN5) 1 X 1 1 Reserved 19.2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement waitConvert: move C, ADST.5 jump NC, waitConvert ; Wait for 16 samples to be captured (ADDAI=1) move ADST.6, #0 move ADST.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SECTION 20: DIGITAL-TO-ANALOG CONVERTERS (SPECIFIC TO MAXQ8913) 20.1 DAC Overview The MAXQ8913 provides six independent digital-to-analog converter (DAC) channels. Four of these DAC channels produce voltage outputs, while the other two channels act as programmable current sinks.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 20.2.1 DAC 1 Output Register (DAC1OUT, M3[02h]) Bit # 15 14 13 12 11 10 9 8 Name — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r rw rw Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Name DAC1OUT DAC1OUT Bits 15:10: Reserved Bits 9:0: DAC 1 Output Value.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 20.2.3 DAC 3 Output Register (DAC3OUT, M3[04h]) 7 6 5 4 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # Name 3 2 1 0 DAC3OUT Bits 7:0: DAC 3 Output Value. This register sets the voltage output value for the DAC3 channel between zero (DAC3OUT = 00000000b) and full scale (DAC3OUT = 11111111b). For this register value to be effective, DACEN.2 (DACEN3) must be set to 1 to enable the voltage output at pin DAC3.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SECTION 21: TIMER/COUNTER B MODULE (SPECIFIC TO MAXQ8913) The MAXQ8913 provides one Type B timer/counter module that operates as described in this section. Table 21-1 and Table 21-2 list the associated pins and registers for these timer/counter modules. Table 21-1. Type B Timer/Counter Input and Output Pins TIMER/COUNTER FUNCTION PIN MULTIPLEXED WITH GPIO TB0A: Timer B I/O Pin A K3 P1.2 TB0B: Timer B I/O Pin B L2 P1.3 Table 21-2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 21.1.2 Timer B Timer/Counter Compare Register (TBC, M2[0Bh]) Bit # 15 14 13 12 Name 11 10 9 8 TBC Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name TBC Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bits 15:0: Timer B Compare Register. This register is used for comparison vs. the TBV value when Timer B is operated in compare mode. 21.1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bit 7: Timer B Overflow Flag (TFB). This bit is set when Timer B overflows from TBR or the count is equal to 0000h in down-count mode. It must be cleared by software. Bit 6: External Timer B Trigger Flag (EXFB). When configured as a timer (C/TB = 0), a negative transition on the TB0B pin causes this flag to be set if (CP/RLB = EXENB = 1) or (CP/RLB = DCEN = 0 and EXENB = 1) or (CP/RLB = 0 and EXENB = 1 and TBCS:TBCR<>00b).
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MAXQ Family User’s Guide: MAXQ8913 Supplement 21.2 Timer/Counter B Operation Timer/Counter B is a 16-bit programmable device that supports clock input prescaling and set/reset/toggle PWM/output control functionality not found on other MAXQ timer implementations. A new register, TBC, supports certain PWM/ output control functions in some implementations.
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MAXQ Family User’s Guide: MAXQ8913 Supplement TBR 0 SYSTEM CLOCK TBPS[2:0] = TBCN[10:8] 2(2 x TBPS[2:0]) TFB = TBCN.7 COMPARE C/TB = TBCN.15 0 /CLK TBV 1 TB0A PIN RELOAD TRB = TBCN.2 TB0B PIN 15 0 FALLING EDGE 15 0000h EXFB = TBCN.6 EXENB = TBCN.3 TIMER B INTERRUPT Figure 21-1. Timer B Autoreload Mode Block Diagram SYSTEM CLOCK TBPS[2:0] = TBCN[10:8] 2(2 x TBPS[2:0]) C/TB = TBCN.15 0 /CLK 0 TB0A PIN 15 CAPTURE TRB = TBCN.2 TB0B PIN TFB = TBCN.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 21.2.3 Timer B 16-Bit Up/Down Count with Autoreload Mode The 16-bit up/down-count autoreload mode is enabled by clearing the capture/reload bit CP/RLB of the control register (TBCN.0) to 0 and setting the down-count enable bit, DCEN (TBCN.4), to 1. This mode is illustrated in Figure 21-3. When DCEN is set to 1, Timer B counts up from 0000h or down from the value contained in the TBR register as controlled by the state of the TB0B pin.
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MAXQ Family User’s Guide: MAXQ8913 Supplement TBR 0 15 TBPS[2:0] = TBCN[10:8] SYSTEM CLOCK COMPARE 2(2 x TBPS[2:0]) /CLK TBV TRB = TBCN.2 C/TB = TBCN.15 = 0 0 15 0000h TB0A PIN DIVIDE BY 2 TB0A PIN TB0B PIN FALLING EDGE TIMER INTERRUPT EXFB = TBCN.6 EXENB = TBCN.3 Figure 21-4. Timer B Clock Output Mode Block Diagram 21.2.4 Timer B Clock Output Mode Timer B can be configured to drive a clock output on the TB0A pin as shown in Figure 21-4.
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MAXQ Family User’s Guide: MAXQ8913 Supplement When the timer is not running (i.e., TRB = 0), the initial output state of the TB0B pin is established as low or high, respectively, if the reset function (TBCR = 1,TBCS = 0) or set function (TBCR = 0, TBCS = 1) is configured. Invoking the toggle function does not change the already defined starting state for TB0B, thus a fixed high or low starting state can be defined for the toggle mode by first passing through the set or reset mode.
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MAXQ Family User’s Guide: MAXQ8913 Supplement TBC > TBR TBR TBC < TBR 0000 TBC < TBR TBCS, TBCR = TB0B PIN 10 (SET) 01 (SET) 11 (TOGGLE) TBC > TBR TBCS, TBCR = TB0B PIN 10 (SET) 01 (SET) 11 (TOGGLE) Figure 21-6. Timer B PWM/Output Control Mode Waveform (Count Up) 21.2.7 16-Bit Up/Down Count PWM/Output Control Mode Figure 21-7 shows a functional diagram of the up/down-count PWM/output control mode.
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MAXQ Family User’s Guide: MAXQ8913 Supplement (DOWN-COUNTING RELOAD VALUE) TBR TBC 0 SYSTEM CLOCK TBPS[2:0] = TBCN[10:8] 2(2 x TBPS[2:0]) 15 COMPARE C/TB = TBCN.15 0 /CLK TB0B PIN TBV 1 TB0A PIN TRB = TBCN.2 0 15 0000h (UP-COUNTING RELOAD VALUE) FALLING EDGE TFB = TBCN.7 TIMER B INTERRUPT EXFB = TBCN.6 EXENB = TBCN.3 Figure 21-7.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 21.2.8 EXENB Control During PWM/Output Control Mode The TB0B input function (EXENB = 1) and the PWM/output control function (TBCS:TBCR<>00b) can be enabled at the same time. However, the input function changes slightly when this is done. In this configuration, the detection of a falling edge on the TB0B pin results in setting of the EXFB interrupt flag, but does not force an autoreload. 21.3 Timer B Examples 21.3.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SECTION 22 : I2C BUS INTERFACE (SPECIFIC TO MAXQ8913) The MAXQ8913 provides an inter-IC (I2C) communications module that includes master and slave modes. The associated pins and registers for this interface are listed in Table 22-1 and Table 22-2. Table 22-1. I2C Input and Output Pins I2C INTERFACE FUNCTION PIN MULTIPLEXED WITH GPIO SCL: Clock N4 P1.0 SDA: Data M3 P1.1 Table 22-2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 22.1.1 I2C Data Buffer Register (I2CBUF, M1[06h]) Bit # 15 14 13 12 11 10 Name — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r w* w* Bit # 7 6 5 4 3 2 1 0 Name Reset Access 9 8 I2CBUF I2CBUF 0 0 0 0 0 0 0 0 rw* rw* rw* rw* rw* rw* rw* rw* Note: ADCONV cannot be written when PMME = 1 and SWB = 0. *Can be written only when I2CBUSY = 0.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bit 9: I2C Receiver Overrun Flag (I2CROI). This bit indicates a receive overrun when set to 1. This bit is set to 1 if the receiver has already received two bytes since the last CPU read. This bit is cleared to 0 by software reading the I2CBUF. Setting this bit to 1 by software causes an interrupt if enabled. Writing 0 to this bit does not clear the interrupt. Bit 8: I2C General Call Interrupt Flag (I2CGCI).
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bit 9: I2C Receiver Overrun Interrupt Enable (I2CROIE). Setting this bit to 1 causes an interrupt to the CPU when a receiver overrun condition is detected (I2ROI = 1). Clearing this bit to 0 disables receiver overrun detection interrupt from generating. Bit 8: I2C General Call Interrupt Enable (I2CGCIE). Setting this bit to 1 generates an I2CGCI (general call interrupt) to the CPU when general call is enabled (I2CGCEN = 1).
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bit 8: I2C General Call Enable (I2CGCEN). Setting this bit to 1 enables the I2C to respond to a general call address (address = 0000 0000). Clearing this bit to 0 prevents the I2C from responding to the general call address. Bit 7: I2C STOP Enable (I2CSTOP). Setting this bit to 1 generates a STOP condition. This bit automatically is selfcleared to 0 after the STOP condition has been generated.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 22.1.5 I2C Clock Control Register (I2CCK, M1[0Ch]) Bit # 15 14 13 12 Name 11 10 9 8 I2CCKH Reset 0 0 0 0 0 0 1 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name I2CCKL Reset 0 0 0 0 0 1 0 0 Access rw rw rw rw rw rw rw rw Note 1: Write to this register is ignored when I2CBUSY = 0. Note 2: This register has no function in slave mode. Bits 15:8: I2C Clock High (I2CCKH[7:0]).
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MAXQ Family User’s Guide: MAXQ8913 Supplement 22.1.7 I2C Slave Address Register (I2CSLA, M1[0Eh]) Bit # 15 14 13 12 11 10 Name — — — — — — 9 8 I2CSLA Reset 0 0 0 0 0 0 1 0 Access r r r r r r rw rw Bit # 7 6 5 4 3 2 1 0 Name I2CSLA Reset 0 0 0 0 0 1 0 0 Access rw rw rw rw rw rw rw rw Bits 15:10: Reserved. Read returns zero. Bits 9:7: I2C Slave Address Register Extended Bits.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 22.2.2 I2C Example 2: Master Mode Receive ; I2C configured as master, receive from slave address 08h: ; Setup for Master Mode Receive move I2CCN, #047h call wait_start call wait_busy ; I2CEN = 1, I2CMST = 1, I2CMODE = 1, I2CSTART = 1 ; Polling routine to wait for I2CSTART to clear ; Polling routine to wait for I2CBUSY to clear move move call call ; ; ; ; I2CIE.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 22.2.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SECTION 23: SUPPLY VOLTAGE MONITOR AND POWER CONTROL (SPECIFIC TO MAXQ8913) The MAXQ8913 provides a number of features to allow monitoring and control of its on-board power supplies. The supply voltage monitor register (SVM) monitors the DVDD power supply and can alert the processor through an interrupt if DVDD falls below a programmable threshold.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bit 0: High-Frequency Crystal Oscillator Disable (HFXD). Setting this bit to 1 disables the high-frequency crystal oscillator on the MAXQ8913. However, a high-frequency external clock can still be provided at HFXIN. Clearing this bit to 0 enables the high-frequency crystal oscillator. 23.1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SECTION 24: INPUT/OUTPUT AMPLIFIERS (SPECIFIC TO MAXQ8913) 24.1 Input/Output Amplifier Overview The MAXQ8913 controls two amplifier stages as described in this section. The input amplifier stage consists of four internal, uncommitted op amps that can be used to amplify and/or filter the inputs to the ADC. The output stage consists of an external Class D amplifier that can be used to postprocess the outputs from DAC1 and DAC2. Table 24-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement Bit 1: Amplifier 1 Enable (AMPEN1). This bit controls the active-high SHDNR output signal for the right-side motor driver as follows: 0 = Disabled. SHDNR output is driven high. 1 = Enabled. SHDNR output is driven low to enable motor driver. Bit 0: Amplifier 0 Enable (AMPEN0). This bit controls the active-high SHDNL output signal for the left-side motor driver as follows: 0 = Disabled. SHDNL output is driven high. 1 = Enabled.
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MAXQ Family User’s Guide: MAXQ8913 Supplement SECTION 25: UTILITY ROM (SPECIFIC TO MAXQ8913) 25.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 25.2 In-Application Programming Functions 25.2.1 UROM_flashWrite Function: UROM_flashWrite Summary: Inputs: Programs a single word of flash memory. Outputs: Carry: Set on error and cleared on success. Destroys: PSF, LC[1] A[0]: Word address in program flash memory to write to. A[1]: Word value to write to flash memory. Notes: • This function uses one stack level to save and restore values.
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MAXQ Family User’s Guide: MAXQ8913 Supplement PROGRAM SPACE DATA SPACE (BYTE MODE, CDA0 = 0) FFFFh DATA SPACE (BYTE MODE, CDA0 = 1) FFFFh DATA SPACE (WORD MODE) FFFFh FFFFh A7FFh 2K x 16 DATA SRAM EXECUTING FROM A000h 32K x 8 LOWER HALF (PAGE 0) OF PROGRAM FLASH MEMORY 32K x 8 UPPER HALF (PAGE 1) OF PROGRAM FLASH MEMORY 32K x 16 PROGRAM FLASH 87FFh 2K x 16 UTILITY ROM 8000h 8000h 8000h 8000h 7FFFh 16K x 16 PROGRAM FLASH (PAGE 1) 4000h 3FFFh 16K x 16 PROGRAM FLASH (PAGE 0) 0FFFh 0000h 0F
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MAXQ Family User’s Guide: MAXQ8913 Supplement 25.3.1 UROM_moveDP0 Function: UROM_moveDP0 Summary: Reads the byte/word value pointed to by DP[0]. Inputs: DP[0]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 25-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 25.3.4 UROM_moveDP1 Function: UROM_moveDP1 Summary: Reads the byte/word value pointed to by DP[1]. Inputs: DP[1]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 25-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 25.3.7 UROM_moveBP Function: UROM_moveBP Summary: Reads the byte/word value pointed to by BP[OFFS]. Inputs: BP[OFFS]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 25-1.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 25.3.10 UROM_copyBuffer Function: UROM_copyBuffer Summary: Inputs: Copies LC[0] bytes/words (up to 256) from DP[0] to BP[OFFS]. Outputs: Destroys: DP[0]: Address to copy from. BP[OFFS]: Address to copy to. LC[0]: Number of bytes or words to copy. OFFS is incremented by LC[0]. DP[0] is incremented by LC[0]. LC[0] Notes: • T his function can be used to copy from program flash to data RAM, or from one part of data RAM to another.
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MAXQ Family User’s Guide: MAXQ8913 Supplement 25.4.
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MAXQ Family User’s Guide: MAXQ8913 Supplement APPENDIX 1: MAXQ8913 DEVICE INCLUDE FILE FOR MAX-IDE ;============================================================================== ;= ;= Copyright (C) 2009 Maxim Integrated Products. ;= All rights Reserved. Printed in U.S.A.
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MAXQ Family User’s Guide: MAXQ8913 Supplement ;==================================================================== ;= Module 0 = ;==================================================================== #define PO0 M0[0] ; Port 0 Output #define EIF0 M0[2] ; External Interrupt Flag 0 EIF1 M0[4] #define #define #define #define #define PO1 EIE0 EIE1 SVM ; Reserved M0[1] M0[3] M0[5] M0[6] *M0[7] #define PI0 #define EIES0 M0[10] #define #define #define #define PI1 PWCN PID0 ; Reserved #def
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MAXQ Family User’s Guide: MAXQ8913 Supplement #define SPICN M1[2] ; SPI Control #define I2CCN M1[4] ; I2C Control #define #define #define #define #define #define #define #define #define #define #define SPIB I2CST M1[3] M1[5] I2CBUF M1[6] I2CIE M1[7] PR M1[9] SMD M1[8] SPICF M1[10] I2CCK M1[12] SPICK I2CTO M1[11] M1[13] I2CSLA M1[14] ; Reserved *M1[15] ; Reserved *M1[17] ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved
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MAXQ Family User’s Guide: MAXQ8913 Supplement #define TBR #define MC0R #define #define #define M2[7] ; Timer B Capture/Reload M2[9] ; Multiplier Read Register 0 MC1R M2[8] TBV M2[10] TBC M2[11] ; Reserved *M2[12] ; Reserved *M2[14] ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Multiplier Read Register 1 ; Timer B Value ; Timer B Compar
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MAXQ Family User’s Guide: MAXQ8913 Supplement ; Reserved *M3[13] ; Reserved *M3[15] ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved ; Reserved *M3[14] *M3[16] *M3[17] *M3[18] *M3[19] *M3[20] *M3[21] *M3[22] *M3[23] *M3[24] *M3[25] *M3[26] *M3[27] *M3[28] *M3[29] *M3[30] *M3[31] ;==================================================================== ;= Utility ROM Functions = ;
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MAXQ Family User’s Guide: MAXQ8913 Supplement #define UROM_flashEraseAll #087C1h #define UROM_moveDP0inc #087D3h #define #define #define #define #define #define #define #define #define A1-6 UROM_moveDP0 #087D0h UROM_moveDP0dec #087D6h UROM_moveDP1 #087D9h UROM_moveDP1inc #087DCh UROM_moveDP1dec #087DFh UROM_moveBP #087E2h UROM_moveBPinc #087E5h UROM_moveBPdec #087E8h UROM_copyBuffer #087EBh Maxim Integrated
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MAXQ Family User’s Guide: MAXQ8913 Supplement REVISION HISTORY REVISION NUMBER REVISION DATE SECTION NUMBER 0 8/09 — DESCRIPTION Initial release. PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.