Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFN 32 EP (5x5) 16-Bit 12 MHz I/O number 24

MAXQ610

16-Bit Microcontroller with Infrared Module

8 _______________________________________________________________________________________

Pin Description

32 TQFN 40 TQFN 44 TQFN

NAME FUNCTION

POWER PINS

15, 29 18, 38 19, 41 V

Supply Voltage

13, 22, 30 —

17, 20,

28, 42

GND

Ground. These pins must be directly connected to the ground plane. The 40-pin

TQFN package does not have any ground pins and connects to ground through

the exposed pad.

14 17 18 REGOUT

Regulator Capacitor. This pin must be connected to ground through a 1.0μF

external ceramic-chip capacitor. The capacitor must be placed as close to this

pin as possible. No devices other than the capacitor should be connected to

this pin.

— — — EP

Exposed Pad. For the 32-pin TQFN package, leave unconnected.

For the 40-pin TQFN package, the exposed pad is internally connected to GND.

Connect to the ground plane.

For the 44-pin TQFN package, the EP has no internal connection to the device.

Leave unconnected. Not intended as an electrical connection point.

RESET PINS

28 37 40 RESET

Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin

is low and begins executing from the reset vector when released. The pin

includes pullup current source and should be driven by an open-drain, external

source capable of sinking in excess of 4mA. This pin is driven low as an output

when an internal reset condition occurs.

CLOCK PINS

18 21 23 HFXIN

19 22 24 HFXOUT

High-Frequency Crystal Input. Connect external crystal or resonator between

HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is

the input for an external, high-frequency clock source when HFXOUT is

unconnected.

IR FUNCTION PINS

31 39 43 IRTX

IR Transmit Output. IR transmit pin capable of sinking 25mA. This pin defaults

to high-impedance input with the weak pullup disabled during all forms of reset.

Software must configure this pin after release from reset to remove the high-

impedance input condition.

32 40 44 IRRX

IR Receive Input. IR receive pin. This pin defaults to high-impedance input with

the weak pullup disabled during all forms of reset. Software must configure this

pin after release from reset to remove the high-impedance input condition.