Datasheet

10 Maxim Integrated
16-Bit Microcontrollers with
Infrared Module and Optional USB
MAXQ612/MAXQ622
Figure 1. Series Resistors (R
S
) for Protecting Against High-Voltage Spikes
Note 15:
For USB operation, both V
DD
and V
BUS
must be connected.
Note 16: FRCVDD is the force V
DD
power-supply bit (PWCN.10). When FRCVDD = 1, V
DDB
power switching is disabled, and V
DD
is always used as the core 3V power supply.
Note 17: The ESD protection scheme is in production on existing parts. The 1FF capacitor on V
BUS
is intended to protect that
pin from ESD damage (rather than DP or DM) since it is externally exposed. The ESD test uses 150pF charged to 15kV
applied to the 1FF capacitor creating a delta V of approximately 2.25V and limiting the voltage on V
BUS
.
Note 18: Devices that use nonstandard supply voltages that do not conform to the intended I
2
C bus system levels must relate their
input levels to the voltage to which the pullup resistors R
P
are connected.
Note 19: The maximum fall time, t
F_I2C
of 300ns for the SDA and SCL bus lines is longer than the specificed maximum t
OF_I2C
of
250ns for the output stages. This allows series protection resistors (R
S
) to be connected between the SDA/SCL pins and
the SDA/SCL bus lines as shown in I
2
C Bus Controller Timing without exceeding the maximum specified fall time.
Note 20: C
B
= Capacitance of one bus line in pF.
Note 21: All values referred to V
IH_I2C(MIN)
and V
IL_I2C (MAX)
.
Note 22: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH_I2C(MIN)
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 23: The maximum t
HD:DAT
need only be met if the device does not stretch the low period (t
LOW_I2C
) of the SCL signal.
Note 24: A fast-mode I
2
C bus device can be used in a standard-mode I
2
C bus system, but the requirement t
SU:DAT
R 250ns must
be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
R_I2C(MAX)
+ t
SU:DAT
=
1000 + 250 = 1250ns (according to the standard-mode I
2
C specification) before the SCL line is released.
Note 25: AC electrical specifications are guaranteed by design and are not production tested.
Figure 2. I
2
C Bus Controller Timing Diagram
SDA
P0.3
SCL
P0.4
R
S
R
S
I
2
C
DEVICE
R
S
R
S
I
2
C
DEVICE
R
P
R
P
V
DD
MAXQ612
MAXQ622
SDA
SCL
SSRP
S
t
F_I2C
t
R_I2C
t
LOW_I2C
t
HIGH_I2C
t
HD:STA
t
SU:DAT
t
SU:STA
t
SU:STO
t
BUF
t
HD:DAT
NOTE: TIMING REFERENCED TO V
IH_I2C(MIN)
AND V
IL_I2C(MAX).