MAXQ612/MAXQ622 USER’S GUIDE MAXQ612/MAXQ622 REGULATOR VOLTAGE MONITOR GPIO USB SIE* TXCVR 16-BIT MAXQ RISC CPU 6KB ROM SECURE MMU CLOCK 128KB FLASH WATCHDOG 6KB SRAM 2x 16-BIT TIMER 8kHz NANO RING IR DRIVER IR TIMER 2x SPI 2x USART I2C *MAXQ622 ONLY. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
MAXQ612/MAXQ622 User’s Guide TABLE OF CONTENTS SECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2: Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 1: OVERVIEW The MAXQM family of 16-bit reduced instruction set computing (RISC) microcontrollers is targeted towards low-cost, low-power embedded application designs. The flexible, modular architecture design used in these microcontrollers allows development of targeted designs for specific applications with minimal effort. 1.1 Instruction Set The MAXQ612/MAXQ622 microcontrollers use an instruction set where all instructions are fixed in length (16 bits).
MAXQ612/MAXQ622 User’s Guide Peripheral registers (module 0 to module 5) on the MAXQ612/MAXQ622 contain registers that are used to access the peripherals, including: • General-purpose I/O ports • External interrupts • Timers/counters • USART ports • Serial peripheral interface (SPI™) port • USB (MAXQ622 only) SPI is a trademark of Motorola, Inc.
MAXQ612/MAXQ622 User’s Guide SECTION 2: ARCHITECTURE This section contains the following information: 2.1 Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2 Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide 2.11.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.11.3 Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.11.
MAXQ612/MAXQ622 User’s Guide SECTION 2: ARCHITECTURE The MAXQ612/MAXQ622 are designed to be modular and expandable. Top-level instruction decoding is extremely simple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the system register and peripheral register groups. Figure 2-1 illustrates the modular architecture and the basic transport possibilities.
MAXQ612/MAXQ622 User’s Guide Memory access from the MAXQ612/MAXQ622 is based on a Harvard architecture with separate address spaces for program and data memory. The simple instruction set and transport-triggered architecture allow the MAXQ612/ MAXQ622 to decode and execute nearly all instructions in a single clock cycle. Data memory is accessed through one of three data pointer registers. Two of these data pointers, DP[0] and DP[1], are stand-alone 16-bit pointers.
MAXQ612/MAXQ622 User’s Guide The MAXQ instruction set is designed to be highly orthogonal. All arithmetic and logical operations that use two registers can use any register along with the accumulator. Data can be transferred between any two registers in a single instruction. 2.2 Register Space The MAXQ612/MAXQ622 provide a total of 16 register modules. Each of these modules contains 32 registers.
MAXQ612/MAXQ622 User’s Guide Table 2-1. Register-to-Register Transfer Operations SOURCE REGISTER SIZE (BITS) DESTINATION REGISTER SIZE (BITS) PREFIX SET? DESTINATION SET TO VALUE HIGH 8 BITS LOW 8 BITS 8 8 — 8 16 No 00h Source[7:0] Source[7:0] 8 16 Yes Prefix[7:0] Source[7:0] 16 8 — 16 16 No Source[7:0] Source[15:8] Source[7:0] 2.
MAXQ612/MAXQ622 User’s Guide Following each reset, the processor automatically starts execution at address 8000h in the utility ROM, allowing utility ROM code to perform any necessary system support functions. Next, the SPE bit is examined to determine whether system programming should commence or whether that code should be bypassed, instead forcing execution to vector to the start of user program code.
MAXQ612/MAXQ622 User’s Guide 2.3.4 Stack Memory The MAXQ612/MAXQ622 implement a soft stack that uses the on-chip data memory (SRAM) for storage of program return addresses and general-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced; it can also be used explicitly to store and retrieve data by using the PUSH, POP, and POPI instructions.
MAXQ612/MAXQ622 User’s Guide DATA SPACE (BYTE MODE) PROGRAM SPACE DATA SPACE (WORD MODE) 88FFh 3K x 16 UTILITY ROM 8000h FFFFh 64K x 16 PROGRAM FLASH 17FFh x8 DATA SRAM 0000h 08FFh x 16 DATA SRAM 0000h 0000h Figure 2-3. MAXQ612/MAXQ622 Memory Map (64KB Program Space) Table 2-2. CDA Bits to Access Program Space as Data CDA[1:0] SELECTED PAGE IN BYTE MODE SELECTED PAGE IN WORD MODE 00 P0 P0 and P1 01 P1 P0 and P1 10 P2 P2 and P3 11 P3 P2 and P3 2.5.
MAXQ612/MAXQ622 User’s Guide WORD MODE MEMORY MAP (UPA = 0, EXECUTING FROM UTILITY ROM) DATA MEMORY PROGRAM MEMORY 15 xFFFF LOGICAL SPACE 0 15 0 P3 P2 xA000 UTILITY ROM CDA1 = 1 x8000 x8000 PHYSICAL PROGRAM (P1) x4000 0 1= A CD PHYSICAL PROGRAM (P0) PHYSICAL DATA x0000 x0000 WORD MODE MEMORY MAP (UPA = 0, EXECUTING FROM PHYSICAL DATA MEMORY) PROGRAM MEMORY 15 xFFFF DATA MEMORY LOGICAL SPACE 0 15 0 xFFFF P3 LOGICAL SPACE LOGICAL DATA MEMORY P2 xA000 LOGICAL UTILITY ROM UTILITY ROM x
MAXQ612/MAXQ622 User’s Guide BYTE MODE MEMORY MAP (EXECUTING FROM UTILITY ROM) xFFFF 15 PROGRAM MEMORY 0 7 DATA MEMORY 0 LOGICAL SPACE xFFFF xA000 UTILITY ROM x8000 C PHYSICAL PROGRAM (P1) x8000 1 ]=0 1:0 DA[ PHYSICAL DATA 0 :0 A[1 PHYSICAL PROGRAM (P0) CD 0 ]= x0000 x0000 BYTE MODE MEMORY MAP (EXECUTING FROM PHYSICAL DATA MEMORY) PROGRAM MEMORY xFFFF 15 DATA MEMORY 0 7 0 LOGICAL SPACE xFFFF LOGICAL SPACE xA000 UTILITY ROM x8000 x8000 PHYSICAL PROGRAM (P1) PHYSICAL PROG
MAXQ612/MAXQ622 User’s Guide CODE POINTER ACCESS OF WORD MODE MEMORY MAP PHYSICAL PROGRAM MEMORY 15 0 CODE POINTER MAP 15 0 xFFFF xFFFF PHYSICAL PROGRAM (P3) PHYSICAL PROGRAM (P3) PHYSICAL PROGRAM (P2) PHYSICAL PROGRAM (P2) PHYSICAL PROGRAM (P1) PHYSICAL PROGRAM (P1) PHYSICAL PROGRAM (P0) PHYSICAL PROGRAM (P0) x0000 x0000 CODE POINTER OF BYTE MODE MEMORY MAP PHYSICAL PROGRAM MEMORY 15 0 CODE POINTER MAP 7 0 xFFFF xFFFF PHYSICAL PROGRAM (P3) PHYSICAL PROGRAM (P2) PHYSICAL PROGRAM (P1) CP A
MAXQ612/MAXQ622 User’s Guide MAXQ612/MAXQ622 MEMORY MAP (DEFAULT, UPA = 0) DATA MEMORY PROGRAM MEMORY 15 xFFFF 0 0 15 xFFFF LOGICAL SPACE P3 P2 xA000 UTILITY ROM x8000 x8000 PHYSICAL PROGRAM (P1) LOGICAL SPACE x4000 PHYSICAL PROGRAM (P0) PHYSICAL DATA x0000 x0000 MAXQ612/MAXQ622 MEMORY MAP (UPA = 1) 15 PROGRAM MEMORY xFFFF 0 DATA MEMORY 15 0 xFFFF PHYSICAL PROGRAM (P3) PHYSICAL PROGRAM (P2) LOGICAL UTILITY ROM x8000 x8000 PHYSICAL PROGRAM (P1) LOGICAL SPACE x4000 PHYSICAL PROGR
MAXQ612/MAXQ622 User’s Guide 2.5.3 Memory Mapping Rules When executing program code in a particular memory segment, the same memory segment cannot be simultaneously accessed as data. The following is a summary of the memory mapping rules. • When executing from the normal user code segment: The lower 32KWords program space (P0 and P1) is always executable as program. The upper half of the code segment (P2 and P3) is accessible as program when UPA is set to 1.
MAXQ612/MAXQ622 User’s Guide 2.5.4 Code Examples Because the MAXQ622 uses the maximum allowed program flash supported by this core, the most extreme example of data pointer access would be the final bytes of the flash in byte mode. This can be accomplished by executing from data memory (requiring the UPA bit to be cleared) and setting the CDA bits to map program segment P3 to the data memory area. Code to read the final 3 bytes of the flash is shown below.
MAXQ612/MAXQ622 User’s Guide 2.6 Memory Protection The MAXQ612/MAXQ622 support privilege levels for code. When enabled, code memory is separated into three areas. Each area has an associated privilege level. RAM/utility ROM are assigned privilege levels as well: • C ode in the system area can be confidential. Code in the user areas can be prevented from reading and writing system code. • The user loader can be protected from user application code. Table 2-4.
MAXQ612/MAXQ622 User’s Guide This means that when using PRIVT0/PRIVT1, the privilege level cannot be raised unless all code between the writes to PRIVT0 and PRIVT1 executes. Writing to PRIV automatically resets PRIVT0 to low. 2.6.
MAXQ612/MAXQ622 User’s Guide • A system library function that checks arguments before raising the privilege level must do so in an atomic fashion using PRIVT0 and PRIVT1 to prevent short-circuiting the check (the rule about disabling interrupts also applies). Example: system_library: move IGE, #0 move PRIVT0, #HIGH … ; check jump ne, exit
; … action ret move PRIVT1, #HIGH exit: move PRIV, #LOW move IGE, #1 2.6.
MAXQ612/MAXQ622 User’s Guide This is no different for instructions that operate on data pointers. For example, a pointer to pointer move such as MOVE @DP[1], @DP[0] first requires the read pointer to be activated. Architecturally, this strobes the chip enable and read signals on the memory mapped to the location in DP[0]. This value is latched internally so that it is available when @ DP[0] is used as the source operand. At that time, the internally latched data is transferred to the destination register.
MAXQ612/MAXQ622 User’s Guide Next, the RAM routine calls into the flash function. Once we are executing out of flash, we can activate the DP[0] pointer without causing a memory fault because the MMU now maps RAM into address range 0–7FFFh and ROM to higher addresses. None of this space is MPE protected.
MAXQ612/MAXQ622 User’s Guide TOP (128KB) USER APPL +10h USR APP PASSWORD STARTUP UAPP USER LDR +10h ULDR USR APP START SYSTEM IVT IVT IVT IVT IVT IVT 20h 10h 0000 USR LDR PASSWORD STARTUP SYS PASSWORD RESET/STARTUP DEBUG LOCK USR LDR START Figure 2-8. Overview of Memory Regions Figure 2-8 shows the code memory with passwords and the location of the values that are programmed into the ULDR/ UAPP registers.
MAXQ612/MAXQ622 User’s Guide 2.6.7 Loader Access Control As stated previously, the MAXQ612/MAXQ622 have three memory regions: system, user loader, and application. The loader maintains a context register to determine which of the regions is to be the target of the loader commands. Family 0 and Family F commands have no context. They are global in scope.
MAXQ612/MAXQ622 User’s Guide 2.6.8 Disabling MAXQ612/MAXQ622-Specific Memory Access Features The MAXQ612/MAXQ622 memory-protection features are specific to the MAXQ612/MAXQ622 family of parts and can cause some confusion in the way that they impact debugging and bootloader commands when compared to MAXQ parts.
MAXQ612/MAXQ622 User’s Guide POWER-ON RESET RESET STOP RESET DOG WATCHDOG TIMER XDOG STARTUP TIMER XDOG DONE RWT RESET WATCHDOG RESET WATCHDOG INTERRUPT CLK INPUT CRYSTAL KILL HF CRYSTAL MAXQ612 MAXQ622 STOP POWER-ON RESET CLOCK GENERATION SYSTEM CLOCK WAKE-UP TIMER DIV 1 DIV 2 DIV 4 DIV 8 PMM 8kHz RING ENABLE GLITCH-FREE MUX CLOCK DIVIDER SWB INTERRUPT/SERIAL PORT RESET SELECTOR DEFAULT STOP Figure 2-9.
MAXQ612/MAXQ622 User’s Guide Crystal specifications, operating temperature, operating voltage, and parasitic capacitance must be considered when designing the internal oscillator. The MAXQ612/MAXQ622 are designed to operate at a 12MHz maximum frequency. To further reduce the effects of external noise, a guard ring can be placed around the oscillator circuitry. Pins HFXIN and HFXOUT are protected by clamping devices against on-chip electrostatic discharge.
MAXQ612/MAXQ622 User’s Guide 2.8.1 Using the Wake-Up Timer to Exit Stop Mode To use the wake-up timer to exit stop mode after a predefined period of time, the following conditions must be met before entering stop mode: • The WUT register must be written to define the countdown interval value. • The WTE bit must be written to 1 to start the wake-up timer. • T he IGE (IC.0) bit must be set to 1 to enable global interrupts.
MAXQ612/MAXQ622 User’s Guide 2) The IPS bits are set to 11b to re-enable interrupt handling. 3) The instruction pointer is set to the return address that was popped off the stack. 4) The CPU continues execution of the main program. Pending interrupt requests do not interrupt a RETI instruction; a new interrupt is serviced after first being acknowledged in the execution cycle that follows the RETI instruction and then after the standard one stall cycle of interrupt latency.
MAXQ612/MAXQ622 User’s Guide Table 2-8. Interrupt Priority INTERRUPT Power Fail VECTOR ADDRESS (HEX) NATURAL PRIORITY 20h 0 PFI (PWCN.2) PFIE (PWCN.1) IVP0[1:0] (IPR0[1:0]) MPE (SC.10) IVP1[1:0] (IPR0[3:2]) FLAG ENABLE* PRIORITY CONTROL Memory Fault 28h 1 PULRF (IC.4), PULWF (IC.5), PSYRF (IC.6), PSYWF (IC.7) External INT[7:0] 30h 2 IE[7:0] (EIF0) EX[7:0] (EIE0) IVP2[1:0] (IPR0[5:4]) IR Timer 38h 3 IROV (IRCNB.0), IRIF (IRCNB.1) IRIE (IRCNB.2) IVP3[1:0] (IPR0[7:6]) RI (SCON0.
MAXQ612/MAXQ622 User’s Guide 2.9.5 Interrupt Exception Window An interrupt exception window is a noninterruptible execution cycle. During this cycle, the interrupt handler does not respond to any interrupt requests. All interrupts that would normally be serviced during an interrupt exception window are delayed until the next execution cycle. Interrupt exception windows are used when two or more instructions must be executed consecutively without any delays in between.
MAXQ612/MAXQ622 User’s Guide The MAXQ612/MAXQ622 support power-fail detection where an on-chip bandgap and reference comparator constantly monitor the supply voltage VDD to ensure that it is within acceptable limits. If VDD is below the power-fail level warning level, an interrupt is generated to the CPU if enabled. If VDD falls further to below the operating condition, the power monitor initiates a reset condition.
MAXQ612/MAXQ622 User’s Guide 2.11.3 Watchdog Timer Reset The watchdog timer is a programmable hardware timer that can be set to reset the processor in the case of a software lockup or other unrecoverable error. Once the watchdog is enabled in this manner, the processor must reset the watchdog timer periodically to avoid a reset. If the processor does not reset the watchdog timer before it elapses, the watchdog initiates a reset state.
MAXQ612/MAXQ622 User’s Guide If switchback is enabled, a processor running under power-management mode automatically clears the PMME bit to 0 and returns to normal mode when any of the following conditions occur: • An external interrupt condition occurs on an INTn pin and the corresponding external interrupt is enabled. • A n active-low transition occurs on the USART serial receive input line (modes 1, 2, and 3) and data reception is enabled.
MAXQ612/MAXQ622 User’s Guide SECTION 3: PROGRAMMING This section contains the following information: 3.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 Prefix Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide 3.9.2 Data Pointer Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.10 Using the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 3: PROGRAMMING This section provides a programming overview of the MAXQ612/MAXQ622. For full details on the instruction set as well as the system register and peripheral register detailed bit descriptions, see the appropriate sections later in this document. 3.1 Addressing Modes The instruction set for the MAXQ612/MAXQ622 provides three different addressing modes: direct, indirect, and immediate. System and peripheral registers are referenced by direct addressing only.
MAXQ612/MAXQ622 User’s Guide However, the operation: move DP[0], #0055h does not require a prefixing operation even though the register DP[0] is 16 bits. This is because the prefix value defaults to zero, so the following line is not required: move PFX[0], #00h 3.3 Reading and Writing Registers All functions in the MAXQ612/MAXQ622 are accessed through registers, either directly or indirectly.
MAXQ612/MAXQ622 User’s Guide 3.3.4 Moving Values Between Registers of Different Sizes Before covering some transfer scenarios that might arise, a special register must be introduced that is used in many of these cases. The 16-bit general register (GR) is expressly provided for performing byte singulation of 16-bit words. The high and low bytes of GR are individually accessible in the GRH and GRL registers, respectively.
MAXQ612/MAXQ622 User’s Guide 3.3.8 Low (16-Bit Destination) ← 8-Bit Source To modify only the low byte of a given 16-bit destination, the 16-bit register should be moved into the GR register such that the high byte can be singulated and the low byte written exclusively. An additional cycle is required if the destination index is greater than 0Fh.
MAXQ612/MAXQ622 User’s Guide Register bits can be set or cleared individually using the MOVE instruction as follows: move IGE, #1 move APC.6, #0 ; set IGE (Interrupt Global Enable) bit ; clear IDS bit (APC.6) As with other instructions, prefixing is required to select destination registers beyond index 07h. The MOVE instruction can also be used to transfer any one of the lowest 8 bits from a register source or any active accumulator (Acc) bit to the carry flag.
MAXQ612/MAXQ622 User’s Guide • SRA4 (Arithmetic shift right active accumulator 4 bit positions) • RL (Rotate active accumulator left) • RLC (Rotate active accumulator left through carry flag) • RR (Rotate active accumulator right) • RRC (Rotate active accumulator right through carry flag) • SR (Logical shift active accumulator right) • MOVE Acc, src (Copy data from source to active accumulator) • MOVE dst, Acc (Copy data from active accumulator to destination) • MOVE Acc,
MAXQ612/MAXQ622 User’s Guide • Increment modulo 8: AP = AP[3] + ((AP[2:0] + 1) mod 8) • Decrement modulo 8: AP = AP[3] + ((AP[2:0] - 1) mod 8) • Increment modulo 16: AP = (AP + 1) mod 16 • Decrement modulo 16: AP = (AP - 1) mod 16 For this example, assume that all 16 accumulator registers are initially set to zero.
MAXQ612/MAXQ622 User’s Guide sra ; Shift accumulator right arithmetically once sra4 ; Shift accumulator right arithmetically 4 times sra2 xchn xch ; Shift accumulator right arithmetically twice ; Swap low and high nibbles of each Acc byte ; Swap low byte and high byte of Acc 3.5.5 ALU Bit Operations Using Only the Active Accumulator The following operations operate on single bits of the current active accumulator in conjunction with the carry flag.
MAXQ612/MAXQ622 User’s Guide 3.6.2 Zero Flag The zero flag (PSF.7) is a dynamic flag that reflects the current state of the active accumulator Acc. If all bits in the active accumulator are zero, the zero flag equals 1. Otherwise, it equals 0. Because the zero flag is a dynamic reflection of (Acc = 0), any instruction that changes the value in the active accumulator can potentially change the value of the zero flag.
MAXQ612/MAXQ622 User’s Guide • MOVE Acc., C (Set selected active accumulator bit to carry) • AND Acc. (Carry = carry AND selected active accumulator bit) • OR Acc. (Carry = carry OR selected active accumulator bit) • XOR Acc. (Carry = carry XOR selected active accumulator bit) • JUMP C, src (Jump if carry flag is set) • JUMP NC, src (Jump if carry flag is cleared) 3.6.5 Overflow Flag The overflow flag (PSF.
MAXQ612/MAXQ622 User’s Guide 3.7.3 Conditional Jumps Conditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S). Except where noted for JUMP E and JUMP NE, the absolute and relative operands allowed are the same as for the unconditional JUMP command.
MAXQ612/MAXQ622 User’s Guide When the supplied loop address is outside the relative jump range, the prefix register (PFX[0]) is used to supply the high byte of the loop address as required. move LC[1], #10h LoopTop: call LoopSub ...
MAXQ612/MAXQ622 User’s Guide 3.7.7 Conditional Return from Interrupt Similar to the conditional returns, the MAXQ612/MAXQ622 microcontrollers also support a set of conditional return from interrupt operation. Based upon the value of one of the status flags, the CPU can conditionally pop the stack, set the IPS bits to 11b, and begin execution at the address popped from the stack.
MAXQ612/MAXQ622 User’s Guide Because the stack is 16 bits wide, it is possible to store two 8-bit register values on it in a single location. This allows more efficient use of the stack if it is being used to save and restore registers at the start and end of a subroutine. SubOne: move PFX[0], IC push PSF ; store IC:PSF on the stack pop ; 16-bit register ... GR move IC, GRH move PSF, GRL ret ; IC was stored as high byte ; PSF was stored as low byte 3.
MAXQ612/MAXQ622 User’s Guide the current WBSn selection. Data pointer increment and decrement operations only affect those bits specific to the current word- or byte-addressing mode (e.g., incrementing a byte-mode data pointer from FFFFh does not carry into the internal high-order bit that is used only for word-mode data-pointer access). Switching from byte- to word-access mode or vice versa does not alter the data pointer contents.
MAXQ612/MAXQ622 User’s Guide move @--DP[1], @DP[1]-- move @BP[--Offs], @BP[Offs--] move @++DP[0], @DP[0]-move @++DP[1], @DP[1]-- move @BP[++Offs], @BP[Offs--] move @--DP[0], @DP[0]++ move @--DP[1], @DP[1]++ move @BP[--Offs], @BP[Offs++] move @DP[0], @DP[0]++ move @DP[1], @DP[1]++ move @BP[Offs], @BP[Offs++] move @DP[0], @DP[0]-move @DP[1], @DP[1]-- move @BP[Offs], @BP[Offs--] move DP[0], @DP[0]++ move DP[0], @DP[0]-move DP[1], @DP[1]++ move DP[1], @DP[1]-- move Offs, @BP[Offs--] move Offs, @BP[Offs++]
MAXQ612/MAXQ622 User’s Guide RWT (WDCN.0) (RESET WATCHDOG) HFXIN HFXOUT SYSTEM CLOCK MODE DIVIDE BY 215 DIVIDE BY 23 215 WD1 WD0 DIVIDE BY 23 218 221 TIMEOUT SELECTOR WDIF (WDCN.3) MAXQ612 MAXQ622 DIVIDE BY 23 224 TIMEOUT WATCHDOG INTERRUPT EWDI (WDCN.6) (ENABLE WATCHDOG INTERRUPT) 512 SYSCLK DELAY EWT (WDCN.1) (ENABLE WATCHDOG TIMER RESET) RESET WTRF (WDCN.2) Figure 3-1.
MAXQ612/MAXQ622 User’s Guide the processor to the lost position prior to the interrupt. By using the watchdog reset function, the processor is restarted from the beginning of the program and therefore placed into a known state. The watchdog timeout selection is made using bits WD1 (WDCN.5) and WD0 (WDCN.4). The watchdog has four timeout selections based on the system clock frequency as shown Figure 3-1.
MAXQ612/MAXQ622 User’s Guide SECTION 4: SYSTEM REGISTER DESCRIPTION This section contains the following information: 4.1 System Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 LIST OF TABLES Table 4-1. System Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 4: SYSTEM REGISTER DESCRIPTION Registers currently defined in the MAXQ612/MAXQ622 system register map are described in Tables 4-1, 4-2, and 4-3. Table 4-1.
MAXQ612/MAXQ622 User’s Guide Table 4-2.
MAXQ612/MAXQ622 User’s Guide Table 4-3.
MAXQ612/MAXQ622 User’s Guide 4.1 System Register Descriptions The addresses for each register are given in the format module[index], where module is the module specifier from 08h to 0Fh and index is the register subindex from 00h to 0Fh. REGISTER DESCRIPTION AP, 08h[00h] Accumulator Pointer Register (8 bits) Initialization This register is cleared to 00h on all forms of reset. Access AP.3 to AP.0 Unrestricted direct read/write access. Active Accumulator Select.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION PRIV, 08h[02h] Initialization Privilege Register (8 bits) This register is reset to 00001111b on all resets. Bits 3 and 2 are cleared by hardware when the current IP is not in utility ROM code, nor system code. Bits 1 and 0 are cleared by hardware when the current IP is not in utility ROM, system, nor user loader code. Access Bits 3 and 2 can only be modified by utility ROM code, or system code.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION PSF, 08h[04h] Processor Status Flags Register (8 bits) Initialization Access This register is cleared to 80h on all forms of reset. Bit 7 (Z) and bit 6 (S) are read-only. Bits 4, 3 (GPF1, GPF0), bit 2 (OV), bit 1 (C) and bit 0 (E) are unrestricted read/write. PSF.0 (E) Equals Flag. This bit flag is set to 1 whenever a compare operation (CMP) returns an equal result. If a CMP operation returns not equal, this bit is cleared. PSF.1 (C) Carry Flag.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION IC, 8h[5h] Interrupt and Control Register (8 bits) Initialization Access This register is cleared to 0Ch on all forms of reset. Unrestricted direct read. Write access to bits 0, 4, 5, 6, 7 only. See bit descriptions for details. IC.0 (IGE) Interrupt Global Enable If this bit is set to 1, interrupts can be enabled individually.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION SC, 08h[08h] Initialization System Control Register (16 bits) This register is reset to 000001ss100000s0b on all resets. Bits 1, 8, and 9 (PWL, PWLS, PWLL) are set to 1 on power-fail and power-on reset only. Access Bits 8, 9, and 10 have write restrictions (see bit descriptions). All other bits: unrestricted read/write access. SC.0 Reserved. All reads return 0. SC.1 (PWL) Password Lock Application.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION SC.9 (PWLL) Password Lock User Loader. This bit defaults to 1 on power-fail and power-on reset. When this bit is 1, it requires a 32-byte password to be matched with the password in the user loader program space before allowing access to the user loader password-protected in-circuit debug or bootstrap loader utility ROM routines. Clearing this bit to 0 disables the password protection for these utility ROM routines.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION IPR1, 08h[0Ah] Interrupt Priority Register One (16 bits) Initialization This register is cleared to 0000h on all forms of reset. Access IPR1[1:0] (IVP8[1:0]) Unrestricted direct read/write. Interrupt Vector 8 Priority Bits 1:0. These bits are used to specify the priority level of interrupt vector 8.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION ULDR, 08h[0Ch] Initialization User Loader Starting Page Address (16 bits) This register is reset to the first page address past the available flash program memory on all resets. On a part with 64KB of program memory with 512-byte pages, this register is reset to 0080h. Access This register can only be modified when PRIV = HIGH. Unrestricted read access. ULDR.8 to ULDR.0 User Loader Starting Page Address.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION WDCN, 08h[0Fh] Initialization Watchdog Control Register (8 bits) Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions. Access Unrestricted direct read/write access. WDCN.0 (RWT) Reset Watchdog Timer. Setting this bit to 1 resets the watchdog timer count.
MAXQ612/MAXQ622 User’s Guide REGISTER WDCN.6 (EWDI) DESCRIPTION Watchdog Interrupt Enable. If this bit is set to 1, an interrupt request can be generated when the WDIF bit is set to 1 by any means. If this bit is cleared to 0, no interrupt occurs when WDIF is set to 1, however, it does not stop the watchdog timer or prevent watchdog resets from occurring if EWT = 1. If EWT = 0 and EWDI = 0, the watchdog timer is stopped.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION IP, 0Ch[00h] Instruction Pointer Register (16 bits) Initialization This register is cleared to 8000h on all forms of reset. Access IP.15 to IP.0 Unrestricted direct read/write access. This register contains the address of the next instruction to be executed and is automatically incremented by 1 after each program fetch. Writing an address value to this register causes program flow to jump to that address.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION DPC, 0Eh[04h] Data Pointer Control Register (16 bits) Initialization This register is cleared to 005Ch on all forms of reset. Access DPC.1 to DPC.0 (SDPS1, SDPS0) Unrestricted direct read/write access. Source Data Pointer Select Bits 1:0. These bits select one of the three data pointers as the active source pointer for the load operation. A new data pointer must be selected before being used to read data memory: DPC.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION GRS, 0Eh[08h] General Register Byte-Swapped (16 bits) Initialization This register is cleared to 0000h on all forms of reset Access GRS.15 to GRS.0 Unrestricted read-only access. This register is intended primarily for supporting byte operations on 16-bit data. This 16-bit read-only register returns the byte-swapped value for the data contained in the GR register.
MAXQ612/MAXQ622 User’s Guide SECTION 5: PERIPHERAL REGISTER MODULES This section contains the following information: 5.1 Peripheral Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 LIST OF TABLES Table 5-1. Peripheral Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 5: PERIPHERAL REGISTER MODULES The MAXQ612/MAXQ622 microcontroller uses peripheral registers to control and monitor peripheral modules. These registers reside in modules 0h to 3h, with subindex values 0h to 1Fh. Table 5-1.
MAXQ612/MAXQ622 User’s Guide Table 5-2.
MAXQ612/MAXQ622 User’s Guide Table 5-2. Peripheral Register Bit Function (continued) REG BIT 15 14 13 12 11 10 — — — — I2CSPIE — 9 8 7 6 5 4 I2CBUF I2CIE 3 2 1 0 I2CTXIE I2CSRIE I2CBUF[7:0] I2CROIE I2CGCIE I2CNACKIE I2CALIE UADDR USBRW UBUSY I2CAMIE I2CTOIE I2CSTRIE I2CRXIE — UDATA UADDR[4:0] UDATA[7:0] I2CCK I2CCKH[7:0] I2CCKL[7:0] I2CTO I2CTO[7:0] I2CSLA I2CLSA[9:0] Table 5-3.
MAXQ612/MAXQ622 User’s Guide Table 5-3.
MAXQ612/MAXQ622 User’s Guide 5.1 Peripheral Register Bit Descriptions REGISTER DESCRIPTION PO0 (00h, 00h) Initialization: Port 0 Output Register (8-bit register) This register is set to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. PO0.7 to PO0.0 Port 0 Output Register Bits 7:0.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION EIF1 (06h, 00h) Initialization: External Interrupt Flag 1 Register EIF1 is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. EIF1.7 to EIF1.0 (IE[15:8]) Interrupt Edge Detect Bits 15:8. These bits are set when a negative edge (ITn = 1) or a positive edge (ITn = 0) is detected on the interrupt n pin. Setting any of the bits to 1 generates an interrupt to the CPU if the corresponding interrupt is enabled.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION PI3 (0Bh, 00h) Initialization: Port 3 Input Register The reset value for this register is dependent on the logical states of the pins. Read/Write Access: Unrestricted read. PI3.7 to PI3.0 Port 3 Input Register Bits 7:0. The PI3 register always reflects the logic state of its pins when read. Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel pullup transistor is controlled by its respective PO bits.
MAXQ612/MAXQ622 User’s Guide REGISTER PD2 (12h, 00h) Initialization: Read/Write Access: DESCRIPTION Port 2 Direction Register This register is cleared to 00h on all resets except power-fail reset. This register is unaffected by power-fail reset. Unrestricted read/write. PD2.7 to PD2.0 Port 2 Direction Register Bits 7:0. PD2 is used to determine the direction of the port 2 function. The port pins are independently controlled by their direction bit.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION PO6 (02h, 01h) Initialization: Port 6 Output Register (8-bit register) This register is set to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. PO6.7 to PO6.0 Port 6 Output Register Bits 7:0. The PO6 register stores output data for port 64 when it is defined as an output port and controls whether the internal weak p-channel pullup transistor is enabled/disabled if a port pin is defined as an input.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION PI4 (08h, 01h) Initialization: Port 4 Input Register The reset value for this register is dependent on the logical states of the pins. Read/Write Access: Unrestricted read. PI4.7 to PI4.0 Port 4 Input Register Bits 7:0. The PI4 register always reflects the logic state of its pins when read. Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel pullup transistor is controlled by its respective PO bits.
MAXQ612/MAXQ622 User’s Guide REGISTER PWCN.4 (IRTXOE) PWCN.5 (IRTXOUT) PWCN.6 (IRRXWP) PWCN.7 (PFRST) PWCN.9 to PWCN.8 (PFRCK[1:0]) DESCRIPTION IRTX Output Enable. The IRTXOE bit is used in conjunction with the IRTXOUT bit to determine the state of the IRTX pin when the IR timer is not enabled (i.e., IREN = 0). When the bit is set to 1, the IRTX pin is used as an output; data in the IRTXOUT bit is driven on the pin.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION PWCN.12 (CTM) Crystal Multiplier Enable. The CTM bit is used to enable the crystal clock multiplier. When programmed to 0, the CTM bit disables the crystal clock multiplier to save energy. When programmed to 1, the CTM bit enables the crystal clock multiplier. The crystal clock multiplier requires a startup stabilization period. Clearing the CTM to 0 automatically clears the CKRY and CTMS bits.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION TB0R (00h, 02h) Initialization: Timer B0 Capture/Reload Value Register (16-bit register) This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write. TB0R.15 to TB0R.0 Timer B0 Capture/Reload Bits 15:0. This register is used to capture the TBV value when Timer B0 is configured in capture mode. This register is also used as the 16-bit reload value when Timer B0 is configured in autoreload mode.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION TB0CN.5 (TBOE) Timer B Output Enable. Setting this bit to 1 enables the clock output function on the TBA pin if C/TB = 0. Timer B rollovers do not cause interrupts. Clearing this bit to 0 allows the TBA pin to function as either a standard port pin or a counter input for Timer B. Timer B 0 and Timer B1 share the TBA pin.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION IRCN (04h, 02h) Initialization: Infrared Control Register (16-bit register) This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write. IRCN.0 (IREN) IR Enable. This register bit enables the IR module. Setting this bit to 1 starts the operating mode as defined by IRMODE bit. Clearing this bit to 0 terminates IR operation. IR Mode. This register bit controls the IR module operation mode. IRCN.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION IRCN.12 to IRCN.10 (IRDIV[2:0]) IR Clock Divide Bits. These two bits select the divide ratio for the IR input clock. IRCN.15 to IRCN.13 IRDIV[2:0] 000 001 010 011 100 101 110 111 Reserved. Reads return 0. IRCA (05h, 02h) Initialization: IR Carrier Register (16-bit register) This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write. IRCA.7 to IRCA.0 (IRCAL[7:0]) IR Carrier Low Byte Bits 7:0.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION TB0C (08h, 02h) Initialization: Timer B0 Compare Register (16-bit register) This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write. TB0C.15 to TB0C.0 Timer B0 Compare Bits 15:0. This register is used for comparison versus the TBV value when Timer B is operated in compare mode.
MAXQ612/MAXQ622 User’s Guide REGISTER SCON0.6 (SM1) SCON0.7 (SM0/FE) DESCRIPTION Serial Port 0 Mode Bits 1:0 (when FEDE is 0). When FEDE is set to 1, this bit is the Framing Error Flag that is set upon detection of an invalid stop bit. It must be cleared by software. Modification of this bit when FEDE is set has no effect on the serial mode.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION SCON1 (02h, 03h) Initialization: Serial Port 1 Control Register The serial port control is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. SCON1.0 (RI) Receive Interrupt Flag. This bit indicates that a data byte has been received in the serial port buffer.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION SBUF1 (03h, 03h) Initialization: Serial Data Buffer 1 This buffer is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. SBUF1.7 to SBUF1.0 Serial Data Buffer 1 Bit 7:0. Data for serial port 0 is read from or written to this location. The serial transmit and receive buffers are separate but both are addressed at this location.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION SPICN1 (07h, 03h) Initialization: SPI Control Register 1 This buffer is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write except bit 7 is read-only. SPICN1.0 (SPIEN) SPI Enable. Setting this bit to 1 enables the SPI module and its baud-rate generator for SPI operation. Clearing this bit to 0 disables the SPI module and its baud-rate generator. SPICN1.1 (MSTM) Master Mode Enable.
MAXQ612/MAXQ622 User’s Guide REGISTER PR1 (0Ah, 03h) Initialization: DESCRIPTION Phase Register 1 The phase register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read/write. PR1.15 to PR1.0 SMD1 (0Bh, 03h) Initialization: Phase Register 1 Bits 15:0. This register is used to load and read the 16-bit value in the phase register that determines the baud rate for the serial port 1. Serial Port Mode Register 1 This register is cleared to 00h on all forms of reset.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION SPICF1 (0Eh, 03h) Initialization: SPI Configuration Register 1 This buffer is cleared to 00h on all forms of reset. Read/Write Access: Unrestricted read/write. SPICF1.0 (CKPOL) Clock Polarity Select. This bit is used with the CKPHA bit to determine the SPI transfer format. When the CKPOL is set to 1, the SPI uses the clock falling edge as an active edge. When the CKPOL is cleared to 0, the SPI selects the clock rising edge as an active edge.
MAXQ612/MAXQ622 User’s Guide REGISTER I2CCN.3: I2CCN.4 (I2CSTRS) DESCRIPTION Reserved. Read returns 0. I2C Clock Stretch Select. Setting this bit to 1 enables clock stretching after the falling edge of the 8th clock cycle. Clearing this bit to 0 enables clock stretching after the falling edge of the 9th clock cycle. This bit has no effect when clock stretching is disabled (I2CSTREN = 0). I2CCN.5 (I2CACK) I2C Data Acknowledge Bit.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION I2CST (01h, 04h) Initialization: I2C Status Register (16-bit register) This register is cleared to 0000h on all forms of reset. Read/Write Access: Unrestricted read. Not all the bits can be written by software. For each bit accessibility refer to individual bit description. I2CST.0 (I2CSRI) I2C START Interrupt Flag. This bit is set to 1 when a START condition (S or Sr) is detected. This bit must be cleared to 0 by software once set.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION I2CST.14 (I2CBUSY) I2C Busy. This bit is used to indicate the current status of the I2C module. The I2CBUSY is set to 1 when the I2C controller is actively participating in a transaction or when it does not have control of the bus. This bit is controlled by hardware and is read only. I2CST.15 (I2CBUS) I2C Bus Busy. This bit is set to 1 when a START/repeated START condition is detected and cleared to 0 when the STOP condition is detected.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION I2CIE.11 (I2CSPIE) I2C STOP Interrupt Enable. Setting this bit to 1 causes an interrupt to the CPU when a STOP condition is detected (I2CSPI = 1). Clearing this bit to 0 disables the STOP detection interrupt from generating. I2CIE.15 to I2CIE.12 Reserved. Reads return 0. UADDR (04h, 04h) Initialization: USB Register Address Register (8-bit register) (applicable only for the MAXQ622) This register is cleared to 00h on all forms of reset.
MAXQ612/MAXQ622 User’s Guide REGISTER DESCRIPTION I2CCK (08h, 04h) Initialization: I2C Clock Control Register (16-bit register) This register is set to 0204h on all forms of reset. Read/Write Access: Unrestricted read. Writes to this register are allowed only when I2CBUSY = 0. This register has no function when operating in slave mode and the clock generation circuitry should be disabled. I2CCK.7 to I2CCK.0 (I2CCKL[7:0]) I2C Clock Low Bits 7:0.
MAXQ612/MAXQ622 User’s Guide SECTION 6: GENERAL-PURPOSE I/O MODULE This section contains the following information: 6.1 Port Pin Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.1 Port Pin Example 1: Driving Outputs on Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 6: GENERAL-PURPOSE I/O MODULE The MAXQ612/MAXQ622 provide 38 port pins for general-purpose I/O that are grouped into eight port pins on port 0 to port 3 and six port pins on port 4. Each of these port pins has the following features: • CMOS output drivers • Schmitt trigger inputs • Optional weak pullup to VDD when operating in input mode From a software perspective, each port appears as a group of peripheral registers with unique addresses.
MAXQ612/MAXQ622 User’s Guide Table 6-1. Port Pin Special Functions (continued) PORT PIN DIRECTION P4.2 Input/Output — — P4.3 Input/Output — — P4.4 Input/Output — — P4.5 Input/Output — — P4.6 Input/Output — P4.7 Input/Output — P5.0 Input/Output SPI 1 Master Out-Slave In (MOSI1) SPIEN1 = 1 P5.1 Input/Output SPI 1 Master In-Slave Out (MISO1) SPIEN1 = 1 P5.
MAXQ612/MAXQ622 User’s Guide 6.1 Port Pin Register Descriptions The following peripheral registers are used to control the general-purpose I/O and external interrupt features specific to the MAXQ612/MAXQ622. Register Name PO0 Register Description Port 0 Output Register Register Address M0[00h] Bit # 7 6 5 4 3 2 1 0 Name PO0.7 PO0.6 PO0.5 PO0.4 PO0.3 PO0.2 PO0.1 PO0.0 Reset s s s s s s s s Access rw rw rw rw rw rw rw rw Bits 7:0: Port 0 Output.
MAXQ612/MAXQ622 User’s Guide Register Name PO3 Register Description Port 3 Output Register Register Address M0[03h] Bit # Name 7 6 5 4 3 2 1 0 PO3.7 PO3.6 PO3.5 PO3.4 PO3.3 PO3.2 PO3.1 PO3.0 Reset s s s s s s s s Access rw rw rw rw rw rw rw rw Bits 7:0: Port 3 Output. This register stores the data that is output on any of the pins of port 3 that have been defined as output pins.
MAXQ612/MAXQ622 User’s Guide Register Name PI0 Register Description Port 0 Input Register Register Address M0[08h] Bit # 7 6 5 4 3 2 1 0 Name PI0.7 PI0.6 PI0.5 PI0.4 PI0.3 PI0.2 PI0.1 PI0.0 Reset s s s s s s s s Access r r r r r r r r Bits 7:0: Port 0 Input Bits. The read values of these bits reflect the logic states present at port 0 pins P0.0 to P0.7.
MAXQ612/MAXQ622 User’s Guide Register Name PI4 Register Description Port 4 Input Register Register Address M1[08h] Bit # 7 6 5 4 3 2 1 0 Name PI4.7 PI4.6 PI4.5 PI4.4 PI4.3 PI4.2 PI4.1 PI4.0 Reset s s s s s s s s Access r r r r r r r r Bits 7:0: Port 4 Input Bits. The read values of these bits reflect the logic states present at port 4 pins P4.0 to P4.7.
MAXQ612/MAXQ622 User’s Guide Register Name PD1 Register Description Port 1 Direction Register Register Address M0[11h] Bit # Name 7 6 5 4 3 2 1 0 PD1.7 PD1.6 PD1.5 PD1.4 PD1.3 PD1.2 PD1.1 PD1.0 Reset s s s s s s s s Access rw rw rw rw rw rw rw rw Bits 7:0: Input/Output Direction for Port 1. The bits in this register control the input/output direction for port pins P1.0 to P1.7. When PD1.n is set to 0, the corresponding port pin (P1.
MAXQ612/MAXQ622 User’s Guide Register Name PD5 Register Description Port 5 Direction Register Register Address M1[11h] Bit # Name 7 6 5 4 3 2 1 0 PD5.7 PD5.6 PD5.5 PD5.4 PD5.3 PD5.2 PD5.1 PD5.0 Reset s s s s s s s s Access rw rw rw rw rw rw rw rw Bits 5:0: Input/Output Direction for Port 5. The bits in this register control the input/output direction for port pins P5.0 to P5.7. When PD5.n is set to 0, the corresponding port pin (P5.
MAXQ612/MAXQ622 User’s Guide 6.2 External Interrupt Register Descriptions Register Name EIF0 Register Description External Interrupt Flag 0 Register Register Address M0[06h] Bit # 7 6 5 4 3 2 1 0 Name IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register is set when a negative edge or a positive edge (depending on the ITn bit setting) is detected on the corresponding interrupt pin.
MAXQ612/MAXQ622 User’s Guide Register Name EIE0 Register Description External Interrupt Enable 0 Register Register Address M0[08h] Bit # Name 7 6 5 4 3 2 1 0 EX7 EX6 EX5 EX4 EX3 EX2 EX1 EX0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register controls the enable for one external interrupt. If a bit is set to 1, the corresponding interrupt is enabled (if it is not otherwise masked).
MAXQ612/MAXQ622 User’s Guide Register Name EIES0 Register Description External Interrupt Edge Select 0 Register Register Address M0[0Ch] Bit # Name 7 6 5 4 3 2 1 0 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Each bit in this register controls the edge select mode for an external interrupt, as follows: 0 = The internal interrupt triggers on a rising (positive) edge.
MAXQ612/MAXQ622 User’s Guide SECTION 7: TIMER/COUNTER TYPE B This section contains the following information: 7.1 Timer B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.1 Timer B Mode: Autoreload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 7: TIMER/COUNTER TYPE B The timer/counter module allows the MAXQ612/MAXQ622 to control a 16-bit programmable timer/counter. The MAXQ612/MAXQ622 implement two timer type B modules (“Timer B”): TB0 and TB1. 7.1 Timer B “Timer B” is an enhanced version of the MAXQ timer type 1 with modifications to support different input clock prescaling and set/reset/compare output functionality. The new timer also counts in the range 0000h to TBR instead of TBR to 0FFFFh.
MAXQ612/MAXQ622 User’s Guide 0 TBPS[2:0] SYSTEM CLOCK CLOCK PRESCALER 15 TBR C/TB TFB = 0 TBV 1 TBA PIN TRB TBB PIN FALLING EDGE 0000h 0 15 EXFB EXENB TIMER B INTERRUPT Figure 7-1. Timer B Autoreload Mode TBPS[2:0] SYSTEM CLOCK CLOCK PRESCALER C/TB 0 TFB TBV 1 TBA PIN TRB TBB PIN FALLING EDGE TBR 0 CAPTURE EXENB 15 EXFB TIMER B INTERRUPT Figure 7-2. Timer B Capture Mode 7.1.2 Timer B Mode: Capture Mode The 16-bit capture mode is invoked by setting the CP/RLB (TBCN.0) bit to 1.
MAXQ612/MAXQ622 User’s Guide (DOWN-COUNTING RELOAD) TBR TBPS[2:0] SYSTEM CLOCK CLOCK PRESCALER C/TB 0 0 15 TBV 1 TBA PIN TRB 0 15 0000h TBB PIN COUNT DIRECTION (1 = UP, 0 = DOWN) (UP-COUNTING RELOAD VALUE) TFB TIMER B INTERRUPT EXFB Figure 7-3. Timer B Up/Down Autoreload Mode 7.1.3 Timer B Mode: Up/Down Autoreload Mode The up/down-count autoreload option is enabled by the DCEN (TBCN.4) bit. When DCEN is set to 1, Timer B counts up or down as controlled by the state of TBB pin.
MAXQ612/MAXQ622 User’s Guide 0 15 TBR TBPS[2:0] SYSTEM CLOCK TFB = C/TB = 0 CLOCK PRESCALER TBV TRB 0000h 0 TBA PIN 15 TOGGLE TBOE = 1 TBB PIN FALLING EDGE EXFB TIMER B INTERRUPT EXENB TBA FREQUENCY OUT = PRESCALED SYSTEM CLOCK/(2 x (TBR + 1)) Figure 7-4. Timer B Clock Output Mode Table 7-2.
MAXQ612/MAXQ622 User’s Guide 7.1.5.1 Timer B Mode: Up-Counting PWM Output Mode The 16-bit timer/counter with autoreload mode is used for the up-counting PWM output mode to produce edge-aligned PWM output. In the 16-bit autoreload timer mode, the Timer B allows an optional external pin (TBB) triggered reload event when the EXENB bit is configured to 1.
MAXQ612/MAXQ622 User’s Guide The set and reset functions for the autoreload up-counting mode essentially provide the same functionality. They provide a 16-bit PWM with the ability to change the frequency using the TBR reload value. The toggle mode allows a 50% duty cycle waveform to be created (when the TBC register is configured to a value inside the counting range, i.e., 0 < TBC < TBR, with Timer B running).
MAXQ612/MAXQ622 User’s Guide Example TBB output waveforms for the autoreload up/down-counting modes are shown below. Up/down-count PWM duty cycle can be calculated as follows (where period = 2 x TBR): Set mode = (TBR + TBC)/(2 x TBR) Reset mode = TBC/(2 x TBR) Toggle mode = TBC/TBR or (TBR - TBC)/TBR Note that the toggle mode has two possible duty-cycle calculations and depends upon the initial pin state and starting TBV and TBC values.
MAXQ612/MAXQ622 User’s Guide Bits 12 and 11: TBB Pin Output Reset Mode, Set Mode (TBCS:TBCR). These mode bits define whether the PWM Mode output function is enabled on the TBB pin, the initial output starting state, and what compare mode output function is in effect. Note that the TBB pin still has certain input functionality when the PWM/output function is enabled. See the 7.1.5 Timer B Mode: PWM Output Function section for details on this mode. Bits 10 to 8: Timer B Clock Prescaler Bits 2:0 (TBPS[2:0].
MAXQ612/MAXQ622 User’s Guide 7.2.2 Timer B Value Register (TBV) 15 0 Timer B Value Register (TBV) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Power-On Reset and System Resets Read (r), Write (w), or Special (s) access The TBV register is a 16-bit register that holds the current Timer B value. 7.2.
MAXQ612/MAXQ622 User’s Guide SECTION 8: IR TIMER This section contains the following information: 8.1 Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 8: IR TIMER The MAXQ612/MAXQ622 microcontroller provides a dedicated IR timer/counter module to simplify support for lowspeed infrared (IR) communication. The IR timer implements two pins (IRTX and IRRX) for supporting IR transmit and receive, respectively. The IRTX pin has no corresponding port pin designation, so the standard PD, PO, and PI port control status bits are not present. However, the IRTX pin output can be manipulated high or low using the PWCN.
MAXQ612/MAXQ622 User’s Guide IRCA IRCA = 0202h IRCA = 0002h IRMT IRMT = 3 IRMT = 5 IRCA, IRMT, IRDATA SAMPLED AT END OF IRV DOWN-COUNT INTERVAL 3 2 1 0 5 4 3 2 1 0 CARRIER OUTPUT (IRV) IRDATA 0 1 0 IR INTERRUPT IRTX IRTXPOL = 1 IRTX IRTXPOL = 0 Figure 8-1.
MAXQ612/MAXQ622 User’s Guide The IR timer acts as a down counter in transmit mode. An IR transmission starts when the IREN bit is set to 1 when IRMODE = 1; when the IRMODE bit is set to 1 when IREN = 1; or when IREN and IRMODE are both set to 1 in the same instruction. The IRMT and IRCA registers, along with the IRDATA and IRTXPOL bits, are sampled at the beginning of the transmit process and every time the IR timer value reloads its value.
MAXQ612/MAXQ622 User’s Guide IRTXM (IRTXPOL = 1) IRTXM (IRTXPOL = 0) IRDATA 1 0 1 0 1 0 1 0 IR INTERRUPT IRV INTERVAL IRMT IRMT IRMT IRMT Figure 8-4. External IRTXM (Modulator) Output 8.4 IR Receive When configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX capture function. The IRRXSEL[1:0] bits define which edge(s) of the IRRX pin should trigger IR timer capture function. The IR module starts operating in the receive mode when IRMODE = 0 and IREN = 1.
MAXQ612/MAXQ622 User’s Guide On the first qualified event, it does the following: 1) C aptures the IRRX pin state and transfers its value to IRDATA. If a falling edge occurs, IRDATA = 0. If a rising edge occurs, IRDATA = 1. 2) Transfers its current IRV value to the IRMT. 3) Resets IRV content to 0000h (if IRXRL = 1). 4) Continues counting again until the next qualified event.
MAXQ612/MAXQ622 User’s Guide CARRIER FREQUENCY CALCULATION IRMT = PULSE COUNTING IRMT = PULSE COUNTING IRV = CARRIER CYCLE COUNTING IRRX IRV IRMT 1 0 2 3 4 6 7 5 0 TO 4 8 9 CAPTURE INTERRUPT (IRIF = 1) IRV ≥ IRMT IRV = 0 (IF IRXRL = 1) 5 SOFTWARE SET IRCA = CARRIER FREQUENCY. SOFTWARE SETS RXBCNT = 1 (WHICH SETS IRMT = 0001 IN HARDWARE). SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1.
MAXQ612/MAXQ622 User’s Guide 0 0 1 1 0 IRTX (IRTXPOL = 1) IRDATA 1 0 1 0 1 0 1 0 IR INTERRUPT IRMT IRMT IRMT IRMT IRRXSEL = 10b 0 0 1 0 1 1 0 1 0 IRRX IRDATA 0 1 0 IRMT CAPTURE IR INTERRUPT IRMT0 IRMT1 IRMT2 IRMT3 IRMT4 IRMT5 NOTE: 0 = HIGH-TO-LOW TRANSITION, 1 = LOW-TO-HIGH TRANSITION, BIT LENGTH FIXED. Figure 8-7.
MAXQ612/MAXQ622 User’s Guide 0 0 1 1 0 IRTX IRDATA (IRTXPOL = 1) 1 0 1 0 IRMT_T IRMT_T IRMT_T IRMT_T 1 0 1 0 1 0 IRMT_T IRMT_T IRMT_T IR INTERRUPT IRMT_2T IRMT_T IRMT_2T IRRXSEL = 10b 0 0 1 1 0 IRRX IRDATA 0 0 1 1 0 1 0 1 0 IRMT CAPTURE IR INTERRUPT IRMT_T IRMT_T IRMT_T IRMT_2T IRMT_T IRMT_2T IRMT_T IRMT_T IRMT_T NOTE: 0 = 1T HIGH, 1T LOW, 1 = 2T HIGH, 1T LOW, VARIED BIT LENGTH. Figure 8-8.
MAXQ612/MAXQ622 User’s Guide 8.7 IR Timer Peripheral Registers 8.7.1 IR Control Register (IRCN) 15 0 IR Control Register (IRCN) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Power-On Reset and System Resets Read (r), Write (w), or Special (s) access Bit 13: IRV Count Enable (IRVCEN). Setting this bit to 1, while IRMODE = 0 (receive mode), enables IRV up counting. IRCFME is used to select the clock source of the IRV in this mode.
MAXQ612/MAXQ622 User’s Guide Bits 5 and 4: IR Receive Edge Select Bits (IRRXSEL[1:0]) These bits define which edge of the input signal triggers a receive capture function when enabled. IRRXSEL[1:0] IR RECEIVE MODE 00 Trigger on falling edge. 01 Trigger on rising edge. 10 Trigger on both rising and falling edge. 11 Reserved. Bit 3: IR Data (IRDATA).
MAXQ612/MAXQ622 User’s Guide Bit 1: IR Interrupt Flag (IRIF). This flag is set to 1 during transmit when the IR timer reloads its value and in receive mode (if RXBCNT = 0), when a capture occurs. In receive mode (when RXBCNT = 1), this flag is set whenever the IRCA x 2 interval timer expires. This bit must be cleared to 0 by software once it is set. Bit 0: IR Timer Overflow Flag (IROV). This flag is set to 1 when the IR timer overflows from 0FFFFh to 0000h in receive mode.
MAXQ612/MAXQ622 User’s Guide SECTION 9: SERIAL I/O MODULE This section contains the following information: 9.1 USART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.1.1 USART Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 9: SERIAL I/O MODULE The serial I/O module provides the MAXQ612/MAXQ622 access to a universal synchronous/asynchronous receivertransmitter (USART) for serial communication with framing error detection. 9.1 USART Modes The USART supports four basic modes of operation and is capable of both synchronous and asynchronous modes, with different protocols and baud rates.
MAXQ612/MAXQ622 User’s Guide SYSTEM CLOCK DIVIDE BY 12 0 RXD PIN LATCH S0 D7 D6 D5 D4 D3 D2 D1 D0 LOAD CLOCK SBUF OUTPUT SHIFT REGISTER DIVIDE BY 4 1 DATA BUS LDSBUF RDSBUF SBUF RD RECEIVE DATA BUFFER WR SERIAL I/O CONTROL RECEIVE BUFFER LOAD DATA CLOCK RI FLAG = SCON.0 CLOCK D7 D6 D5 D4 D3 D2 D1 D0 INTS BAUD CLOCK TI FLAG = SCON.1 SHIFT READ SERIAL BUFFER LOAD SERIAL BUFFER SM2 = SCONx.
MAXQ612/MAXQ622 User’s Guide 9.1.2 USART Mode 1 This mode provides asynchronous, full-duplex communication. A total of 10 bits is transmitted, consisting of a start bit (logic 0), 8 data bits, and 1 stop bit (logic 1) as illustrated in Figure 9-2. The data is transferred LSB first. The baud rate is programmable through the baud-clock generator. Following a write to SBUF, the USART begins transmission five cycles after the first baud clock from the baud-clock generator.
MAXQ612/MAXQ622 User’s Guide 1 START SYSTEM CLOCK D7 D6 D5 D4 D3 D2 D1 D0 LOAD CLOCK STOP SBUF TRANSMIT SHIFT REGISTER TXD PIN LATCH S0 0 DIVIDE BY 4 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL BUFFER SBUF RD RI FLAG = SCON.0 SI SERIAL INTERRUPT WR RB8 = SCON.2 CLOCK TI FLAG = SCON.
MAXQ612/MAXQ622 User’s Guide Data is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses the sample divide-by-16 counter with either the clock divided by 2 or 4, thus resulting in a baud clock of either system clock/32 or system clock/64. SYSTEM CLOCK/2 1 DIVIDE BY 2 0 SMOD START LOAD CLOCK STOP D8 D7 D6 D5 D4 D3 D2 D1 D0 SBUF TRANSMIT SHIFT REGISTER LATCH S0 0 TB8 = SCON.
MAXQ612/MAXQ622 User’s Guide 9.1.4 USART Mode 3 This mode has the same operation as mode 2, except for the baud rate source. As shown in Figure 9-4, mode 3 generates baud rates through the baud-clock generator. The bit shifting and protocol are the same. 1 DIVIDE BY 4 LATCH S0 TB8 = SCON.3 1 TXD PIN 0 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL BUFFER SBUF RD RI FLAG = SCON.0 SI SERIAL INTERRUPT WR RB8 = SCON.2 CLOCK TI FLAG = SCON.
MAXQ612/MAXQ622 User’s Guide 9.2 Baud-Rate Generation Each mode of operation has a baud-rate generator associated with it. The baud-rate generation techniques are impacted by certain user options such as the power-management mode enable (PMME), serial mode 2 (SM2) select bit, and baud-rate doubler (SMOD) bit. Table 9-2 summarizes the effects of the various user options on the USART baud clock. Table 9-2.
MAXQ612/MAXQ622 User’s Guide 15 0 0 PR ADDITION 16 BAUD-CLOCK OUTPUT = CARRY OUT FROM PHASE ACCUMULATOR [16] 0 PHASE ACCUMULATOR Figure 9-5. Baud-Clock Generator The below formulas can be used to calculate the output of the baud-clock generator and the resultant mode 1, 3 baud rates. Additionally, a table has been provided giving example phase register (PR) settings needed to produce some more common baud rates at certain system clock frequencies (assuming SMOD = 1).
MAXQ612/MAXQ622 User’s Guide The FE bit is set to a 1 when a framing error occurs. It must be cleared by software. Note that the FEDE state must be 1 while reading or writing the FE bit. Also note that receiving a properly framed serial word does not clear the FE bit. This must be done in software. 9.4 USART Peripheral Registers 9.4.
MAXQ612/MAXQ622 User’s Guide Bit 0: Receive Interrupt Flag (RI). This bit indicates that a data byte has been received in the serial port buffer. The bit is set at the end of the 8th bit for mode 0, after the last sample of the incoming stop bit for mode 1 subject to the value of the SM2 bit, or after the last sample of RB8 for modes 2 and 3. This bit must be cleared by software once set. 9.4.
MAXQ612/MAXQ622 User’s Guide SECTION 10: SERIAL PERIPHERAL INTERFACE (SPI) MODULE This section contains the following information: 10.1 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 SPI Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 10: SERIAL PERIPHERAL INTERFACE (SPI) MODULE The serial peripheral interface (SPI) module of the MAXQ612/MAXQ622 microcontrollers provide an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a 4-wire full-duplex serial bus that can be operated in either master mode or slave mode.
MAXQ612/MAXQ622 User’s Guide transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and therefore also defines which clock edge is the active edge. To define a serial shift clock signal that idles in a logic-low state (active clock edge = rising), the clock polarity select bit (CKPOL; SPICF.0) should be configured to a 0, while setting CKPOL = 1 causes the shift clock to idle in a logic-high state (active clock edge = falling).
MAXQ612/MAXQ622 User’s Guide 10.2 SPI Slave Select The SPI slave-select SSEL can be configured to accept either an active-low or active-high SSEL signal through the slave active select bit (SAS) in the SPI configuration register. The SAS bit allows the selection of the SSEL asserted state. When SAS is cleared to 0, SSEL is configured to be asserted low. When SAS is set to 1, SSEL is configured to be asserted high. 10.
MAXQ612/MAXQ622 User’s Guide The application software must correct the system conflict before resuming its normal operation. The MODF flag is set automatically by hardware, but must be cleared by software or a reset once set. Setting the MODF bit to 1 by software causes an interrupt if enabled. Mode fault detection is optional and can be disabled by clearing the MODFE bit to 0.
MAXQ612/MAXQ622 User’s Guide the first clock edge or the active SSEL edge, dependent on the data transfer format. When SAS is cleared to 0, the active SSEL edge is the falling edge of SSEL, while if SAS is set to 1, the active SSEL edge is the rising edge of SSEL. The SPI slave receives data from the external master MOSI pin, most significant bit first, while simultaneously transferring the contents of its shift register to the master on the MISO pin, also most significant bit first.
MAXQ612/MAXQ622 User’s Guide Bit 3: Mode Fault Flag (MODF). This bit is the mode fault flag for SPI master mode operation. When mode fault detection is enabled (MODFE = 1) in master mode, detection of high to low transition on the SSEL pin signifies a mode fault causes MODF to be set to 1. This bit must be cleared to 0 by software once set. Setting this bit to 1 causes an interrupt if enabled. This flag has no meaning in slave mode.
MAXQ612/MAXQ622 User’s Guide 10.8.3 SPI Clock Register (SPICKn) 7 0 SPI Clock Register (SPICKn) Power-On Reset and System Resets Read (r), Write (w), or Special (s) access 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw Bits 7:0: Clock Divider Ratio Bits 7:0 (CKR[7:0]). This 8-bit value determines the system clock divide ratio to be used for SPI master mode baud-clock generation. This register has no function when operating in slave mode as the SPI clock generation circuitry is disabled.
MAXQ612/MAXQ622 User’s Guide SECTION 11: I2C INTERFACE This section contains the following information: 11.1 I2C Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.1 Master-Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 11: I2C INTERFACE The MAXQ612/MAXQ622 provide an I2C module, which is an 8-bit, bidirectional, 2-wire serial bus interface with the following characteristics: • Compliant with NXP I2C bus specification version 0.
MAXQ612/MAXQ622 User’s Guide flag is set (I2CTXI = 1). The I2CTXI flag is set after the acknowledge bit has been received from the slave. This generates an interrupt to the CPU if the transmit interrupt is enabled (I2CTXIE = 1). On receiving acknowledgement (ACK) from the slave, the master can then start transmitting data bytes to the slave. The master refrains from generating the SCL clock until data has been written to I2CBUF.
MAXQ612/MAXQ622 User’s Guide 11.1.2 Master-Receiver When operating in master mode with I2CMODE bit set to 1, the I2C module is operating in master-receiver mode. The I2C operates in a similar fashion as in master-transmitter mode. The master initiates the transfer by generating the START condition. Once START has been successfully generated, the master transmits the slave address (I2CBUF) according to address setting (I2CEA).
MAXQ612/MAXQ622 User’s Guide N BEGIN BEGIN DETECT START I2CSRI = 1 I2CBUS = 1 DETECT START I2CSRI = 1 I2CBUS = 1 RECEIVE SLAVE ADDRESS RECEIVE SLAVE ADDRESS N I2CAMI = 1? Y I2CAMI = 1? Y TRANSMIT DATA ANY MORE? RECEIVE DATA Y N ANY MORE? Y N STOP? N Y STOP? N Y DETECT STOP I2CBUS = 0 DETECT STOP I2CBUS = 0 END END (A) SLAVE TRANSMITTER (B) SLAVE RECEIVER Figure 11-5.
MAXQ612/MAXQ622 User’s Guide 11.1.4 Slave-Receiver The I2C module functions as a slave-receiver when an address match is identified (I2CAMI = 1) and the R/W bit is 0. The I2C module operates in a similar fashion as the slave-transmitter mode previously described. On detecting a START (S) condition, the I2C controller, if enabled, shifts in the address bits and compares it against its own address (I2CSLA). If the address matches, the I2CAMI flag is set to 1 and an interrupt generated if enabled.
MAXQ612/MAXQ622 User’s Guide Similarly, if an external master pulls SCL low before the I2C controller has finished counting its I2CCKH cycles, the I2C controller starts counting its I2CCKL cycles and releases SCL once the I2CCKL count has expired. Theoretically, the I2C bit rate is limited to fSYS/8 in both master mode and slave mode. Practically, the I2C specification requires minimum timing on SCL high and low periods.
MAXQ612/MAXQ622 User’s Guide 11.4 I2C Peripheral Register Descriptions The following peripheral registers are used to control the integrated I2C peripheral on the devices. 11.4.
MAXQ612/MAXQ622 User’s Guide Bit 5: I2C Data Acknowledge Bit (I2CACK). This bit selects the acknowledge bit returned by the I2C controller while acting as a receiver. Setting this bit to 1 generates a NACK (leaving SDA high). Clearing the I2CACK bit to 0 generates an ACK (pulling SDA low) during the acknowledgement cycle. This bit retains its value unless changed by software or hardware.
MAXQ612/MAXQ622 User’s Guide Bit 9: I2C Receiver Overrun Flag (I2CROI). This bit indicates a receive overrun when set to 1. This bit is set to 1 if the receiver has already received 2 bytes since the last CPU read. This bit is cleared to 0 by software reading the I2CBUF. Setting this bit to 1 by software causes an interrupt if enabled. Writing 0 to this bit does not clear the interrupt. Bit 8: I2C General Call Interrupt Flag (I2CGCI).
MAXQ612/MAXQ622 User’s Guide 11.4.
MAXQ612/MAXQ622 User’s Guide 11.4.5 I2C Clock Control Register (I2CCK) Register Name I2CCK Register Description I2C Clock Control Register Register Address M4[08h] Bit # 15 14 13 12 Name 11 10 9 8 I2CCKH[7:0] Reset 0 0 0 0 0 0 1 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 0 0 Access rw rw rw rw rw rw rw rw Name I2CCKL[7:0] Note 1: Writes to this register are ignored when I2CBUSY = 0.
MAXQ612/MAXQ622 User’s Guide 11.4.7 I2C Slave Address Register (I2CSLA) Register Name I2CSLA Register Description I2C Slave Address Register Register Address M4[0Ah] Bit # 7 6 5 4 3 2 1 0 Name — I2CSLA6 I2CSLA5 I2CSLA4 I2CSLA3 I2CSLA2 I2CSLA1 I2CSLA0 Reset 0 0 0 0 0 0 0 0 Access r rw rw rw rw rw rw rw Bit 7: Reserved. Reads returns zero. Bits 6 to 0: I2C Slave Address Register (I2CSLA[6:0]). These address bits contain the address of the I2C device.
MAXQ612/MAXQ622 User’s Guide 11.5.2 I2C Example: Master Mode, Receive I2C configured as master, receive from slave address 08h: ; Setup for Master Mode Receive move I2CCN, #047h ; I2CEN = 1, I2CMST = 1, I2CMODE = 1, I2CSTART = 1 call wait_busy ; Polling routine to wait for I2CBUSY to clear call move move call call wait_start I2CIE.
MAXQ612/MAXQ622 User’s Guide 11.5.
MAXQ612/MAXQ622 User’s Guide SECTION 12: UNIVERSAL SERIAL BUS (USB) INTERFACE This section contains the following information: 12.1 USB SIE Endpoint Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 USB SIE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 12: UNIVERSAL SERIAL BUS (USB) INTERFACE Note: This section only applies to the MAXQ622. The MAXQ622 provides a USB 2.0 full-speed interface compliant with the Universal Serial Bus Revision 2.0 Specification. The full-speed USB transceiver provides a complete USB interface between the MAXQ622 and a host USB controller. The MAXQ622 internally generates the USB clock from the 12MHz input.
MAXQ612/MAXQ622 User’s Guide SIE TIMER ENCODER DECODER DPLL EOP VPO VMO OE VPI VMI RCV PROTOCOL LOGIC MODE SUSPEND BUSACT SOF VBUSDET ENDPOINT BUFFER LOGIC TO DUAL PORT—SRAM Figure 12-3. USB SIE Block Diagram 12.
MAXQ612/MAXQ622 User’s Guide 12.3 USB Peripheral Register Descriptions The following peripheral registers are used to control the USB functions. 12.3.1 USB Register Address Register Register Name UADDR Register Description USB Register Address Register Register Address M4[04h] Bit # 7 6 5 4 3 2 1 0 USBRW UBUSY — UADDR4 UADDR3 UADDR2 UADDR1 UADDR0 Reset 0 0 0 0 0 0 0 0 Access rw r rw rw rw rw rw rw Name Note: Writes to this register are ignored when UBUSY = 1.
MAXQ612/MAXQ622 User’s Guide 12.3.2 USB Data Register (UDATA) Register Name UDATA Register Description USB Data Register Register Address M4[05h] Bit # 7 6 5 4 3 2 1 0 Name UDATA7 UDATA6 UDATA5 UDATA4 UDATA3 UDATA2 UDATA1 UDATA0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Note: Writes to this register are ignored when UBUSY = 1.
MAXQ612/MAXQ622 User’s Guide 12.4.2 USB Control Register (USBCN) Register Name USBCN Register Description USB Control Register Register Address UADDR[4:0] = 02h Bit # Name 7 6 5 4 3 2 1 0 OSCST VBGATE URST PWRDN CONNECT SIGRWU — — Reset 1 0 1 1 0 0 0 0 Access rw rw rw rw rw rw rw rw Note: This register is initialized on POR only. Bit 7: Oscillator Start (OSCST).
MAXQ612/MAXQ622 User’s Guide 12.4.4 USB Interrupt Enable Register (USBIEN) Register Name USBIEN Register Description USB Interrupt Enable Register Register Address UADDR[4:0] = 04h Bit # Name 7 6 5 4 3 2 1 0 BRSTDNIE VBUSIE NOVBUSIE SUSPIE BRSTIE BACTIE RWUDNIE DPACTIE Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Note: This register is only accessible when USBEN = 1. All bits in this register except for USBIEN.3 and USBIEN.
MAXQ612/MAXQ622 User’s Guide Bit 6: VBUS Detect (VBUS). This bit is set when the VBUSDET signal has made a 0-to-1 transition (VBUS is present). This bit remains set unless cleared by software, a USB controller reset, or a USB bus reset. Setting this bit to 1 causes an interrupt to the CPU if USB VBUS detect interrupt is enabled (VBUSIE = 1). Bit 5: No VBUS (NOVBUS). The SIE sets this bit when the VBUSDET signal has made a 1-to-0 transition (VBUS is not present).
MAXQ612/MAXQ622 User’s Guide Bit 0: EP0-IN Buffer Available Interrupt Enable (IN0BAVIE). Setting this bit to 1 causes an interrupt to the CPU when the EP0-IN buffer is available (IN0BAV = 1). Clearing this bit to 0 disables the buffer ready interrupt from generating. 12.4.
MAXQ612/MAXQ622 User’s Guide 12.4.8 Endpoint Stall Register (EPSTL) Register Name EPSTL Register Description Endpoint Stall Register Register Address UADDR[4:0] = 08h Bit # 7 6 5 4 3 2 1 0 Name — ACKSTAT STLSTAT STLEP3 STLEP2 STLEP1 STLOUT0 STLIN0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit 7: Reserved. Reads returns zero. Bit 6: Acknowledge Status Stage (ACKSTAT).
MAXQ612/MAXQ622 User’s Guide 12.4.9 Endpoint NAK Register (EPNAK) Register Name EPNAK Register Description Endpoint NAK Register Register Address UADDR[4:0] = 09h Bit # Name 7 6 5 4 3 2 1 0 EP3NAK EP2NAK EP0NAK — — — — — Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit 7: EP3-IN NAK (EP3NAK). The SIE sets this bit when the EP3-IN endpoint receives an IN request and returns the NAK handshake. This bit remains set unless cleared by software.
MAXQ612/MAXQ622 User’s Guide 12.4.11 Endpoint 0 Byte Count Register (EP0BC) Register Name EP0BC Register Description Endpoint 0 Byte Count Register Register Address UADDR[4:0] = 0Bh Bit # 7 6 5 4 3 2 1 0 Name — EP0BC6 EP0BC5 EP0BC4 EP0BC3 EP0BC2 EP0BC1 EP0BC0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit 7: Reserved. Reads returns zero. Bits 6 to 0: EP0 Byte Count (EP0BC[6:0]).
MAXQ612/MAXQ622 User’s Guide 12.4.14 Endpoint 3 IN Byte Count Register (EP3BC) Register Name EP3BC Register Description Endpoint 3 IN Byte Count Register Register Address UADDR[4:0] = 0Eh Bit # 7 6 5 4 3 2 1 0 Name — EP3BC6 EP3BC5 EP3BC4 EP3BC3 EP3BC2 EP3BC1 EP3BC0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit 7: Reserved. Reads returns zero. Bits 6 to 0: EP3-IN Byte Count.
MAXQ612/MAXQ622 User’s Guide 12.4.16 Endpoint 1 Buffer Register (EP1BUF) Register Name EP1BUF Register Description Endpoint 1 Buffer Register Register Address UADDR[4:0] = 11h Bit # 7 6 5 4 3 2 1 0 Name EP1BUF7 EP1BUF6 EP1BUF5 EP1BUF4 EP1BUF3 EP1BUF2 EP1BUF1 EP1BUF0 Reset s s s s s s s s Access rw rw rw rw rw rw rw rw Note: This register is indetermistic on POR and retains its value on all other forms of reset. Bits 7 to 0: EP1 Buffer (EP1BUF[7:0]).
MAXQ612/MAXQ622 User’s Guide 12.4.18 Endpoint 3 Buffer Register (EP3BUF) Register Name EP3BUF Register Description Endpoint 3 Buffer Register Register Address UADDR[4:0] = 13h Bit # 7 6 5 4 3 2 1 0 Name EP3BUF7 EP3BUF6 EP3BUF5 EP3BUF4 EP3BUF3 EP3BUF2 EP3BUF1 EP3BUF0 Reset s s s s s s s s Access rw rw rw rw rw rw rw rw Note: This register is indetermistic on POR and retains its value on all other forms of reset. Bits 7 to 0: EP3 Buffer (EP3BUF[7:0]).
MAXQ612/MAXQ622 User’s Guide 12.5 USB Examples 12.5.1 USB Example 1: Reading from an Internal USB Register (EPINT) To read from an internal USB register, the user will write the destination register offset to UADDR and wait for UBUSY to clear before valid data is available from UDATA. ;; reading from USB register MOV UADDR, #EPINT ; (RW=1, ADDR=00111) CHK: MOV JUMP MOV C, UADDR.6 NC, CHK ; Read EPINT register, #EPINT = 87h ; loop to check UBUSY flag ; and wait for it to clear C, UDATA.
MAXQ612/MAXQ622 User’s Guide 12.5.2 USB Example 2: Writing to an Internal USB Register (EP2BC) To write to the USB state registers, the user will write the destination register offset to UADDR, write data to UDATA register, and wait for UBUSY to clear to complete the operation. ;; writing to USB register MOV UADDR, #EP2BC ; Read EP2BC register, #EP2BC = 12h MOV UDATA, #0010h ; Write 0010h to the EP2BC register JUMP NC, CHK ; and wait for it to clear ; (RW=0, ADDR=10010 CHK: MOV C, UADDR.
MAXQ612/MAXQ622 User’s Guide SECTION 13: TEST ACCESS PORT (TAP) This section contains the following information: 13.1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 TAP State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 13: TEST ACCESS PORT (TAP) The MAXQ612/MAXQ622 microcontrollers incorporate a test access port (TAP) and TAP controller for communication with a host device across a 4-wire synchronous serial interface. The TAP can be used by MAXQ612/MAXQ622 microcontrollers to support in-system programming and/or in-circuit debug. The TAP is compatible with the JTAG IEEE standard 1149 and is formed by four interface signals as described in Table 13-1.
MAXQ612/MAXQ622 User’s Guide TEST-LOGIC-RESET 1 0 RUN-TEST-IDLE 1 SELECT-DR-SCAN 0 1 0 1 1 SELECT-IR-SCAN 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 EXIT1-DR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 0 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 1 EXIT1-IR UPDATE-IR 0 1 0 Figure 13-1. TAP Controller State Diagram 13.2.
MAXQ612/MAXQ622 User’s Guide Table 13-2. Instruction Register Content vs.
MAXQ612/MAXQ622 User’s Guide READ WRITE 7 VDD 6 5 4 3 2 DEBUG 1 0 2 SYSTEM PROGRAM s1 s0 1 0 BYPASS TDI VDD TDO INSTRUCTION REGISTER TMS TCK 2 1 TAP CONTROLLER POWER-ON RESET 0 UPDATE-DR UPDATE-DR Figure 13-2. TAP and TAP Controller Instruction register (IR[2:0]) settings other than those listed and described above are reserved for internal use.
MAXQ612/MAXQ622 User’s Guide For the host to establish a specific data communication link, a private instruction must be loaded into the IR[2:0] register. Once the instruction is latched in the instruction parallel buffer at the update-IR state, it is recognized by the TAP controller and the communication channel is established.
MAXQ612/MAXQ622 User’s Guide TCK TMS TEST-LOGIC-RESET SELECT-IR-SCAN SELECT-DR-SCAN RUN-TEST/IDLE UPDATE-DR EXIT1-DR SHIFT-DR EXIT2-DR PAUSE-DR EXIT1-DR SHIFT-DR CAPTURE-DR SELECT-DR-SCAN RUN-TEST/IDLE CONTROL STATE TDI SHIFT REGISTER DON'T CARE OR UNDEFINED PARALLEL OUTPUT INSTRUCTION REGISTER DON'T CARE OR UNDEFINED NEW DATA OLD DATA DATA REGISTER DON'T CARE OR UNDEFINED TDO ENABLE TDO Figure 13-4.
MAXQ612/MAXQ622 User’s Guide SECTION 14: IN-CIRCUIT DEBUG MODE This section contains the following information: 14.1 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2 Breakpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 14: IN-CIRCUIT DEBUG MODE Flash-based MAXQ612/MAXQ622 microcontrollers are equipped with embedded debug hardware and embedded utility ROM firmware developed for the purpose of providing in-circuit debugging capability to the user application. The in-circuit debug mode uses the JTAG-compatible TAP as its means of communication between the host and MAXQ612/ MAXQ622 microcontrollers. Figure 14-1 shows a block diagram of the in-circuit debugger.
MAXQ612/MAXQ622 User’s Guide The host now can transmit and receive serial data through the 10-bit data shift register that exists between the TDI input and TDO output during DR-scan sequences. All background and debug mode communication (commands, data input/output, and status) occurs through this serial channel. Each 10-bit exchange of data between the host and the MAXQ612/MAXQ622 internal hardware is composed of two status bits and a single byte of command or data.
MAXQ612/MAXQ622 User’s Guide Table 14-1. Background Mode Commands OP CODE COMMAND 0000–0000 No Operation 0000–0001 Read ICDC Read control data from the ICDC. The contents of the ICDC register are loaded into the debug shift register through the ICDB register for host read. This command requires one follow-on transfer cycle. 0000–0010 Read ICDF Read flags from the ICDF. The contents of the ICDF register (1 byte) are loaded into the debug shift register through the ICDB register for host read.
MAXQ612/MAXQ622 User’s Guide Table 14-1. Background Mode Commands (continued) OP CODE COMMAND OPERATION 0001–1000 Write BP3 Write data to the BP3. The contents of ICDB are loaded into the BP3 register by the debug engine at the end of data transfer cycles. Data is transferred with the least significant byte first. 0001–1001 Write BP4 Write data to the BP4. The contents of ICDB are loaded into the BP4 register by the debug engine at the end of data transfer cycles.
MAXQ612/MAXQ622 User’s Guide user program. If an address match is detected, a break occurs, allowing the debug engine to take over control of the CPU and enter debug mode. When (REGE = 1): This register serves as one of the two register breakpoints. A break occurs when the destination register address for the executed instruction matches with the specified module and index. 14.2.
MAXQ612/MAXQ622 User’s Guide 14.3 Debug Mode There are two ways to enter the debug mode from background mode: • Issuance of the debug command directly by the host through the TAP communication port or • Breakpoint matching mechanism The host can issue the debug background command to the debug engine. This direct debug mode entry is indeterministic. The response time varies dependent on system conditions when the command is issued.
MAXQ612/MAXQ622 User’s Guide reloading the debug instruction.
MAXQ612/MAXQ622 User’s Guide Table 14-2. Debug Mode Commands (continued) OP CODE 0010–0100 COMMAND Write register OPERATION Write data to a selected register. This command requires four follow-on transfer cycles, two for the register address and two for the data, starting with the LSB address and ending with the MSB data. The address is moved to the ICDA register and the data is moved to the ICDD register by the debug engine. This information is directly accessible by the utility ROM code.
MAXQ612/MAXQ622 User’s Guide 14.3.3 Single-Step Operation (Trace) The debug engine supports single step operation in debug mode by executing a trace command from the host. The debug engine allows the CPU to return to its normal program execution for one cycle and then forces a debug mode re-entry: 1) Set status to 10b (debug-busy). 2) Pop the return address from the stack. 3) Set the IGE bit to 1 if debug mode was activated when IGE = 1.
MAXQ612/MAXQ622 User’s Guide • S pecial caution should be exercised when using the write register command on register bits that globally affect system operation (e.g., IGE, STOP). If the write register command is used to invoke stop mode (setting STOP = 1), the RESET pin can be asserted to reset the debug engine and return to the background mode of operation.
MAXQ612/MAXQ622 User’s Guide Bit 5: Break-On Register Enable (REGE). The REGE bit is used to enable the break on register function. When REGE bit is set to 1, BP4 and BP 5 are used as register breakpoints. A break occurs when the content of BP4 is matched with the destination address of the current instruction. For BP5, a break occurs only on a selected data pattern for a selected destination register addressed by BP5. The data pattern is determined by the contents in the ICDA and ICDD register.
MAXQ612/MAXQ622 User’s Guide 14.4.4 In-Circuit Debug Buffer Register (ICDB) 7 0 In-Circuit Debug Buffer Register (ICDB) Power-On Reset and Test-Logic-Reset Read (r), Write (w), or Special (s) access 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw This register serves as the parallel holding buffer for the debug shift register of the TAP. Data is read from or written to ICDB for serial communication between the debug routines and the external host. 14.4.
MAXQ612/MAXQ622 User’s Guide SECTION 15: IN-SYSTEM PROGRAMMING (JTAG) This section contains the following information: 15.1 JTAG Bootloader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 Password-Protected Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 15: IN-SYSTEM PROGRAMMING (JTAG) Internal nonvolatile (flash) memory of MAXQ612/MAXQ622 microcontrollers can be initialized through bootstrap-loader mode. To enable the bootstrap loader and establish a desired communication channel, the system programming instruction (100b) must be loaded into the TAP instruction register using the IR-scan sequence.
MAXQ612/MAXQ622 User’s Guide 15.2 Password-Protected Access Some applications require preventive measures to protect against simple access and viewing of program code memory. To address this need for code protection, any MAXQ612/MAXQ622 microcontroller equipped with a utility ROM that permits in-system programming, in-application programming, or in-circuit debugging grants full access to those utilities only after a password has been supplied.
MAXQ612/MAXQ622 User’s Guide SECTION 16: MAXQ612/MAXQ622 INSTRUCTION SET SUMMARY Table 16-1.
MAXQ612/MAXQ622 User’s Guide Table 16-1.
MAXQ612/MAXQ622 User’s Guide ADD/ADDC src Add/Add with Carry Description: The ADD instruction sums the active accumulator (Acc or A[AP]) and the specified src data and stores the result back to the active accumulator. The ADDC instruction additionally includes the Carry (C) Status Flag in the summation. For the complete list of src specifiers, reference the MOVE instruction. The PFX[n] register may be used to supply the high byte of data for 8-bit sources.
MAXQ612/MAXQ622 User’s Guide AND src Logical AND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. The PFX[n] register may be used to supply the high byte of data for 8-bit sources.
MAXQ612/MAXQ622 User’s Guide {L/S}CALL src {Long/Short} Call to Subroutine Description: Performs a call to the subroutine destination specified by src. The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words). The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute long CALL.
MAXQ612/MAXQ622 User’s Guide CMP src Compare Accumulator Description: Compare for equality between the active accumulator and the least significant byte of the specified src. The PFX[n] register may be used to supply the high byte of data for 8-bit sources.
MAXQ612/MAXQ622 User’s Guide Encoding: 15 0 f10n Example(s): 1101 ssss MOVE LC[1], #10h Loop: ADD @DP[0]++ DJNZ LC[1], Loop ssss ; counter = 10h ; add data memory contents to Acc, post-inc DP[0] ; 16 times before falling through {L/S} JUMP src Unconditional {Long/Short} Jump Description: Performs an unconditional jump as determined by the src specifier. The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words).
MAXQ612/MAXQ622 User’s Guide {L/S} JUMP C/{L/S} JUMP NC, src {L/S} JUMP Z/{L/S} JUMP NZ, src Conditional {Long/Short} Jump on Status Flag {L/S} JUMP E/{L/S} JUMP NE, src {L/S} JUMP S, src Description: Performs conditional branching based upon the state of a specific processor status flag. JUMP C results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear. JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear.
MAXQ612/MAXQ622 User’s Guide JUMP E Operation: Encoding: Example(s): Special Notes: JUMP NE Operation: Encoding: Example(s): Special Notes: JUMP S Operation: Encoding: E=1: IP ← IP + src (relative) –or— src (absolute) E=0: IP ← IP + 1 15 0011 ssss ssss JUMP E, label1 ; E=1, branch taken The src specifier must be immediate data.
MAXQ612/MAXQ622 User’s Guide Table 16-2.
MAXQ612/MAXQ622 User’s Guide Table 16-3.
MAXQ612/MAXQ622 User’s Guide Data Transfer Rules dst (16-bit) ← src (16-bit): dst (8-bit) ← src (8-bit): dst (16-bit) ← src (8-bit): dst (8-bit) ← src (16-bit): dst[15:0] ← src[15:0] dst[7:0] ← src[7:0] dst[15:8] ← 00h * dst[ 7:0] ← src[7:0] dst[7:0] ← src[7:0] * Note: The PFX[0] register may be used to supply a separate high order data byte for this type of transfer.
MAXQ612/MAXQ622 User’s Guide MOVE C, src. Move Bit to Carry Flag Description: Status Flag: Operation: Replaces the Carry (C) status flag with the specified source bit src.. C Encoding: 15 fbbb C ← src. 0 0111 ssss ssss ; M0[0] = FEh; C=1 (assume M0[0] is an 8-bit register) ; C=0 Example(s): MOVE C, M0[0].0 Clear Carry Flag MOVE C, #0 Description: Status Flag: Operation: Clears the Carry (C) processor status flag.
MAXQ612/MAXQ622 User’s Guide MOVE dst., #1 Set Bit Description: Status Flags: Operation: Sets the bit specified by dst.. C, E (if dst is PSF) Encoding: 15 1ddd dst. ← 1 0 dddd 1bbb 0111 ; M0[0] = 00h MOVE M0[0].1, #1 ; M0[0] = 02h MOVE M0[0].7, #1 ; M0[0] = 82h Special Notes: Only system module 8 and peripheral modules (0 to 5) are supported by MOVE dst., #1.
MAXQ612/MAXQ622 User’s Guide OR Acc. Logical OR Carry Flag with Accumulator Bit Description: Performs a logical-OR between the Carry (C) status flag and a specified bit of the active accumulator (Acc.) and returns the result to the Carry. Status Flags: Operation: C Encoding: 15 1010 Example(s): C ← C OR Acc. 0 1010 bbbb OR Acc.1 OR Acc.2 1010 ; Acc.1=0 → C=0 ; Acc.
MAXQ612/MAXQ622 User’s Guide PUSH src Push Word to the Stack Description: Increases the stack depth (decments the stack pointer SP) and pushes a single word specified by src to the stack (@SP).
MAXQ612/MAXQ622 User’s Guide RET C/RET NC Conditional Return on Status Flag RET Z/RET NZ RET S Description: Performs conditional return (RET) based upon the state of a specific processor status flag. RET C returns if the Carry flag is set while RET NC returns if the Carry flag is clear. RET Z returns if the Zero flag is set while RET NZ returns if the Zero flag is clear. RET S returns if the Sign flag is set. See RET for additional information on the return operation.
MAXQ612/MAXQ622 User’s Guide RET S Operation: S=1: IP ← @SP-S=0: IP ← IP + 1 Encoding: 15 1100 Example(s): 0 1100 0000 RET S 1101 ; S=0, return (RET) does not occur Return from Interrupt RETI Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). Additionally, RETI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
MAXQ612/MAXQ622 User’s Guide RETI NC Operation: C=0: IP ← @SP-IPS ← 11b C=1: IP ← IP +1 Encoding: 15 1110 Example(s): 0 1100 1000 RETI NC 1101 ; C=1, return from interrupt (RETI) does not occur RETI Z Operation: Z=1: IP ← @SP-IPS ← 11b Z=0: IP ← IP + 1 Encoding: 15 1001 Example(s): 0 1100 1000 RETI Z 1101 ; Z=0, return from interrupt (RETI) does not occur RETI NZ Operation: Z=0: IP ← @SP-IPS ← 11b Z=1: IP ← IP + 1 Encoding: 15 1101 Example(s): 0 1100 1000 RETI NZ 1101 ; Z=0, re
MAXQ612/MAXQ622 User’s Guide Rotate Left Accumulator Carry Flag Exclusive/Inclusive RL/RLC Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msbit of the accumulator (bit 15) back to the lsbit (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 15 Active Accumulator (Acc) 0 ← Acc.[15:1] ← Acc.[14:0]; Acc.0 ← Acc.
MAXQ612/MAXQ622 User’s Guide Rotate Right Accumulator Carry Flag Exclusive/Inclusive RR/RRC Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsbit of the accumulator (bit 0) back to the msbit (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: → 15 Active Accumulator (Acc) 0 Acc.[14:0] ← Acc.[15:1]; Acc.15 ← Acc.
MAXQ612/MAXQ622 User’s Guide Shift Accumulator Left Arithmetically One, Two, or Four Times SLA/SLA2/SLA4 Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iteration, a 0 is shifted into the lsbit and the msbit is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
MAXQ612/MAXQ622 User’s Guide Shift Accumulator Right Shift Accumulator Right Arithmetically One, Two, or Four Times SR SRA/SRA2/SRA4 Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times respectively for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msbit while the SRA, SRA2, and SRA4 instructions effectively shift a copy of the current msbit into the accumulator, thereby preserving any sign orientation.
MAXQ612/MAXQ622 User’s Guide SRA4 Operation: 15 Active Accumulator (Acc) → 0 Carry Flag → → Acc.[11:0] ← Acc.[15:4] Acc.[15:12] ← Acc.15 C ← Acc.3 Encoding: 15 1000 0 1010 1011 1010 ; Acc = 9878h, C=0, Z=0 ; Acc = F987h, C=1, Z=0 ; Acc = FF98h, C=0, Z=0 Example(s): SRA4 SRA4 SUB/SUBB src Description: Subtract/Subtract with Borrow Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumulator.
MAXQ612/MAXQ622 User’s Guide Exchange Accumulator Bytes XCH Description: Exchanges the upper and lower bytes of the active accumulator. Status Flags: S Operation: Acc.[15:8] ← Acc.[7:0] Acc.[7:0] ← Acc.[15:8] Encoding: 15 1000 0 1010 1000 1010 ; Acc = 2345h ; Acc = 4523h Example(s): XCH Exchange Accumulator Nibbles XCHN Description: Exchanges the upper and lower nibbles in the active accumulator byte(s). Status Flags: S Operation: Acc.[7:4] ← Acc.[3:0] Acc.[3:0] ← Acc.[7:4] Acc.[15:12] ← Acc.
MAXQ612/MAXQ622 User’s Guide XOR Acc. Description: Logical XOR Carry Flag with Accumulator Bit Performs a logical-XOR between the Carry (C) status flag and a specified bit of the active accumulator (Acc.) and returns the result to the Carry. Status Flags: C Operation: C ← C XOR Acc. Encoding: 15 1011 bbbb 1010 ; Acc = 2345h, C=1 at start Example(s): XOR Acc.1 XOR Acc.2 16-26 0 1010 ; Acc.1=0 → C=1 ; Acc.
MAXQ612/MAXQ622 User’s Guide SECTION 17: UTILITY ROM This section contains the following information: 17.1 In-Application Programming Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.1.1 UROM_flashWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ612/MAXQ622 User’s Guide SECTION 17: UTILITY ROM The MAXQ612/MAXQ622 utility ROM includes routines that provide the following functions to application software.
MAXQ612/MAXQ622 User’s Guide 17.1 In-Application Programming Functions 17.1.1 UROM_flashWrite Function: UROM_flashWrite Summary: Programs a single word of flash memory. Inputs: A[0]: Word address in program flash memory to write to. A[1]: Word value to write to flash memory. Outputs: Carry: Set on error and cleared on success. Destroys: PSF, LC[1] Notes: • This function uses one stack level to save and restore values.
MAXQ612/MAXQ622 User’s Guide 17.2 Data Transfer Functions 17.2.1 UROM_moveDP0 Function: UROM_moveDP0 Summary: Reads the byte/word value pointed to by DP[0]. Inputs: DP[0]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 2-4 and Figure 2-5.
MAXQ612/MAXQ622 User’s Guide 17.2.4 UROM_moveDP1 Function: UROM_moveDP1 Summary: Reads the byte/word value pointed to by DP[1]. Inputs: DP[1]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 2-4 and Figure 2-5.
MAXQ612/MAXQ622 User’s Guide 17.2.7 UROM_moveFP Function: UROM_moveFP Summary: Lookup table access using BP[OFFS]. Inputs: BP[OFFS]: Location to read from in data space. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 2-4 and Figure 2-5.
MAXQ612/MAXQ622 User’s Guide 17.2.10 UROM_moveBP Function: UROM_moveBP Summary: Reads the byte/word value pointed to by BP[OFFS]. Inputs: BP[OFFS]: Address to read from. Outputs: GR: Data byte/word read. Destroys: None. Notes: • Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode. • T he address passed to this function should be based on the data memory mapping for the utility ROM, as shown in Figure 2-4 and Figure 2-5.
MAXQ612/MAXQ622 User’s Guide 17.4 ROM Example 1: Calling A Utility ROM Function Directly This example shows the direct addressing method for calling utility functions, using the function moveDP1inc to read a static string from code space. Note the equate UROM_MOVEDP1INC. UROM_MOVEDP1INC EQU 087DBh Text: DB “Hello World!”,0 ; Define a string in code space.
MAXQ612/MAXQ622 User’s Guide 17.5 ROM Example 2: Calling A Utility ROM Function Indirectly The second example shows the indirect addressing method (lookup table) for calling utility functions. We use the same function (UROM_MoveDP1Inc) to read our static string, but this time we must figure out the address we want dynamically. Note the inserted code where we before had a direct call to the function. Also note that the function index of moveDP1inc is 7.
MAXQ612/MAXQ622 User’s Guide APPENDIX 1: DATA POINTER USAGE EXAMPLES IMPORTANT: MAXQ20 family pointer mode (DPC.WBS) bits and source select Writing immediate values to DPC (e.g. MOVE DPC, #4) (DPC.SDPS) bits should not be changed simultaneously. without knowing the previous contents can implicitly setup a situation where the mode and select bits are changed simultaneously. A function call with foo: push DPC ;... move DPC, #4 ;...
MAXQ612/MAXQ622 User’s Guide ; execute function code here ; move DPC, #4 ; restore the pop DP[0] ; word mode version of DP[0] move DPC, #0 ; restore the pop DP[0] ; byte mode version of DP[0] pop DPC ; restore DPC ret ; or reti ; ; HINT: If your application is written entirely in assembly code, you can avoid the extra work required to save and restore all 17 bits of each pointer by generating your own set of programming guidelines.
MAXQ612/MAXQ622 User’s Guide Pointer deactivation Any time a pointer is activated another is deactivated. 1) Writing addresses to two pointers. move DP[0], #1234h ; activates pointer DP[0] move DP[1], #4567h ; pointer DP[0] deactivated, activates pointer DP[1] 2) Auto-Incrementing Pointers (buffer access).
MAXQ612/MAXQ622 User’s Guide move ACC, @DP[1] ; DP[1] is now properly configured properly to read **************************************************************************** Example 1a, Incorrect Basic Single Pointer configuration Assumptions: Same as Example 1 **************************************************************************** move DPC, #BP_WORD_MODE_OR_MASK|BP_WORD_MODE_OR_MASK|DP1_SELECT ; *WRONG*.
MAXQ612/MAXQ622 User’s Guide move DP[1], DP[1] ; select DP[1] as the active source pointer by ; writing to the pointer register move ACC, @DP[1] ; DP[1] is now properly configured properly to read **************************************************************************** Example 4, Basic Single Pointer Configuration in a function call. Assumptions: We DO NOT know the contents of DPC. DPC needs to be preserved across the call. DP[1] can be destroyed.
MAXQ612/MAXQ622 User’s Guide move DPC, ACC ; write the new mode value push DP[1] ; save byte mode bits move DP[1], DP[1] ; select DP[1] as the active source pointer by ; writing to the pointer register move ACC, @DP[1] ; DP[1] is now properly configured properly to read ; ;... perform other operations here ; pop DP[1] ; pop byte mode bits move ACC, DPC ; get the current DPC value or #DP1_WORD_MODE_OR_MASK ; change DP[1] to word mode by setting DPC.
MAXQ612/MAXQ622 User’s Guide ; pointer as the active source. move ACC, @DP[1] ; *WRONG* DP[1] is *NOT* properly configured properly move ACC, @DP[0] ; DP[0] is now properly configured properly to read END All of the single pointer examples can be extended to multiple pointer versions. It is assumed that those operations can be extrapolated from the given examples. Conclusions: - pointer mode and pointer selection/activation need to be preformed in separate instructions.
MAXQ612/MAXQ622 User’s Guide INDEX C I N 2-23, 2-25, 3-18, 3-19, 3-20, 6-2, 6-3, 7-2, 7-4, 7-8, 7-9, 8-2, 8-4, 8-5, 8-6, 8-10, 9-2, 9-4, 9-6, 9-7, 9-8, 9-9, 9-10, 9-11, 10-2, 10-3, 10-4, 10-5, 10-6, 10-7, 10-8, 11-2, 11-3, 11-4, 11-6, 11-7, 11-8, 11-9, 11-10, 11-11, 11-12, 12-2, 13-2, 14-10, 14-11 clock cycle 2-4, 2-7, 2-25, 2-26, 2-29, 2-31, 7-2, 11-8, 11-9 2-3, 11-2, 11-3, 11-4, 115, 11-6, 11-7, 11-8, 11-9, 11-10, 11-11, 11-12, 11-13, 11-14, 11-15 2 I C interface 11-2 instruction set 1-1, 2-4, 2-5,
MAXQ612/MAXQ622 User’s Guide INDEX (continued) S U SIE 12-3 SPI 1-2, 2-3, 2-31, 2-32, 6-2, 6-3, 10-2, 10-3, 10-4, 10-5, 10-6, 10-7, 10-8, 16-2, 16-10 SPI interface 10-2 SRAM 2-7, 2-8, 2-30, 3-15, 12-3 6KB 2-7, 2-8 T TAP 4-3, 4-9, 6-2, 13-2, 13-3, 13-4, 13-5, 13-6, 14-2, 14-3, 14-6, 14-7, 14-11, 14-12, 14-13, 15-2, 15-3 test access port 4-9, 13-2 timer 1-2, 2-4, 2-23, 2-25, 2-26, 2-27, 2-29, 2-31, 2-32, 3-18, 4-13, 6-2, 7-2, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, 8-2, 8-4, 8-5, 8-6, 8-11, 8-12, 11-7, 11-8, 11-1
MAXQ612/MAXQ622 User’s Guide REVISION HISTORY REVISION NUMBER REVISION DATE SECTION NUMBER 0 6/10 — Initial release 12 Changed USBCFG bits 2:1 from SOFO and BACTO to reserved in Section 12.4.3: USB Configuration Register (USBCFG); added a note about the self-clearing mechanism for USBIEN and EPIEN bits to Section 12.4.4: USB Interrupt Enable Register (USBIEN) and Section 12.4.6: Endpoint Interrupt Enable Register (EPIEN). 14 Added two bullet points to Section 14.3.
