Datasheet

30 Maxim Integrated
16-Bit Microcontrollers with
Infrared Module and Optional USB
MAXQ612/MAXQ622
nanopower ring-oscillator cycles. If V
DD
> V
RST
during
detection, V
DD
is monitored for an additional nanopower
ring-oscillator period. If V
DD
remains above V
RST
for
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the CPU
exits the reset state in less than 20 crystal cycles after
the reset source is removed.
Table 5. Power-Fail Detection States During Normal Operation
STATE POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMMENTS
A On Off Off — V
DD
< V
POR
.
B On On On —
V
POR
< V
DD
< V
RST
.
Crystal warmup time, t
XTAL_RDY
.
CPU held in reset.
C On On On —
V
DD
> V
RST
.
CPU normal operation.
D On On On —
Power drop too short.
Power-fail not detected.
E On On On —
V
RST
< V
DD
< V
PFW
.
PFI is set when V
RST
< V
DD
< V
PFW
and
maintains this state for at least t
PFW
, at
which time a power-fail interrupt is gener-
ated (if enabled).
CPU continues normal operation.
F
On
(Periodically)
Off Off Yes
V
POR
< V
DD
< V
RST
.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
G On On On —
V
DD
> V
RST
.
Crystal warmup time, t
XTAL_RDY
.
CPU resumes normal operation from
8000h.
H
On
(Periodically)
Off Off Yes
V
POR
< V
DD
< V
RST
.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
I Off Off Off —
V
DD
< V
POR
.
Device held in reset. No operation allowed.