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AIN0

AIN2

AIN4

AIN6

AIN8

AIN10

AIN12

AIN14

AIN1

AIN3

AIN5

AIN7

AIN8

AIN11

AIN13

AIN15

MAXQ7665/

MAXQ7666

12-BIT

DAC

DACOUT

I I

M M

ROTATION

SHAFT

MAGNET MAGNETIC FIELD

DIRECTION

ANISOTROPIC

MAGNETORESISTIVE

SENSOR

MAXQ7665

R+ΔR

V-

CAN

2.0B

BUS

ELECTRONIC

STABILITY

CONTROL

V+

R-ΔR

R+ΔR

12-BIT

ADC

512B

DATA RAM

UP TO 128kB

PROGRAM FLASH,

UP TO 256B

DATA FLASH

CLOCK

GEN/XTAL

INPUT

16-BIT MAXQ20 RISC

(WITH 16 x 16

HARDWARE

MULTIPLIER)

CAN

2.0B

DIGITAL

I/O

UART

(LIN 2.0)

JTAG

TEMP

SENSOR

VOLTAGE

REGULATOR

POWER

MGMT

16-BIT

TIMERS (3)

MUX

PGA

48-TQFN

7mm x 7mm

-40

C to +125

MAXQ7665/MAXQ7666 USER’S GUIDE

Rev 0; 12/07

Summary of content (386 pages)

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MAXQ7665/MAXQ7666 USER’S GUIDE V- MAGNET MAGNETIC FIELD DIRECTION M I R+ΔR I R-ΔR CAN 2.0B BUS S SHAFT I N ROTATION M M R-ΔR POWER MGMT 16-BIT TIMERS (3) V+ TEMP SENSOR UART (LIN 2.0) JTAG DIGITAL I/O CAN 2.
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MAXQ7665/MAXQ7666 User’s Guide For the modulo increment or decrement operation, the selected range of bits in AP are incremented or decremented. However, if these bits roll over or under, they simply wrap around without affecting the remaining bits in the accumulator pointer.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 1: MAXQ7665/MAXQ7666 CORE ARCHITECTURE This section contains the following information: 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5 1.1.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5 1.1.2 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide 1.3.3.1 Loading an 8-Bit Register with an Immediate Value . . . . . . . . . . . . . . . . . . . . .1-30 1.3.3.2 Loading a 16-Bit Register with a 16-Bit Immediate Value . . . . . . . . . . . . . . . . .1-30 1.3.3.3 Moving Values Between Registers of the Same Size . . . . . . . . . . . . . . . . . . . .1-30 1.3.3.4 Moving Values Between Registers of Different Sizes . . . . . . . . . . . . . . . . . . . .1-30 1.3.3.4.1 8-Bit Destination ← Low Byte (16-Bit Source) . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide 1.3.10 Accessing Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-41 1.4 System Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-43 1.4.1 Accumulator Pointer Register (AP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-46 1.4.2 Accumulator Pointer Control Register (APC) . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 1-1. MAXQ7665/MAXQ7666 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5 Figure 1-2. MAXQ7665/MAXQ7666 Transport-Triggered Architecture . . . . . . . . . . . . . . . . . . . . .1-7 Figure 1-3. Instruction Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8 Figure 1-4. Pseudo-Von Neumann Memory Map (MAXQ7665/MAXQ7666 Default) . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 1: MAXQ7665/MAXQ7666 CORE ARCHITECTURE 1.1 Overview The MAXQ7665/MAXQ7666 are low-power, high-performance, 16-bit RISC microcontrollers based on the MAXQ® architecture. They include support for integrated, in-system-programmable flash memory and a wide range of peripherals including a 12-bit 500ksps SAR ADC with a programmable gain amplifier (PGA) and a full CAN 2.0B controller supporting transfer rates up to 1Mbps.
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1.1.2 Instruction Set As part of the MAXQ family, the MAXQ7665/MAXQ7666 use the standard 16-bit MAXQ20 instruction set, with all instructions a fixed 16 bits in length. A register-based, transport-triggered architecture allows all instructions to be coded as simple transfer operations. All instructions reduce to either writing an immediate value to a destination register or memory location or moving data between registers and/or memory locations.
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MAXQ7665/MAXQ7666 User’s Guide 1.2 Architecture The MAXQ7665/MAXQ7666 architecture is designed to be modular and expandable. Top-level instruction decoding is extremely simple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the system register and peripheral register groups. Figure 1-2 illustrates the modular architecture and the basic transport possibilities.
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MAXQ7665/MAXQ7666 User’s Guide Memory access from the MAXQ7665/MAXQ7666 is based on a Harvard architecture with separate address spaces for program and data memory. The simple instruction set and transport-triggered architecture allow the MAXQ7665/MAXQ7666 to run in a nonpipelined execution mode where each instruction can be fetched from memory, decoded, and executed in a single clock cycle. Data memory is accessed through one of three data pointer registers.
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MAXQ7665/MAXQ7666 User’s Guide 1.2.2 Register Space The MAXQ7665/MAXQ7666 architecture provides a total of 16 register modules. Each of these modules contains 32 registers. Of these possible 16 register modules, only 13 are used on the MAXQ7665/MAXQ7666—seven for system registers and six for peripheral registers.
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MAXQ7665/MAXQ7666 User’s Guide The MAXQ7665/MAXQ7666 peripheral register space (modules 0 to 5) contains registers that access the following peripherals: • General-purpose, 8-bit, I/O port (P0) • External interrupts (up to 8) • Three programmable Type 2 timer/counters • Serial UART interface • SPI • CAN interface • Analog input/output module • Hardware multiplier • JTAG debug engine The lower 8 bits of all registers in modules 0 to 5 (as well as the AP module M8) are bit addressable. Table 1-2.
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MAXQ7665/MAXQ7666 User’s Guide Table 1-2.
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MAXQ7665/MAXQ7666 User’s Guide Table 1-3.
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MAXQ7665/MAXQ7666 User’s Guide Table 1-5. MAXQ7666 Data Flash Features FEATURE MAXQ7666 Flash Type Type F Data Flash Size 256B (128 x 16) 128 Pages Data Flash Organization (Regular Mode) 1 Page = 2B (1 x 16) 4000h (Page 0) 4001h (Page 1) Data Flash Page Address (Regular Mode) 4002h (Page 2) ….
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MAXQ7665/MAXQ7666 User’s Guide 1.2.3.2 Utility ROM A utility ROM (4k x 16) is placed in the upper 32kWord program memory space starting at address 8000h. This utility ROM provides the following system utility functions: • Reset vector • Bootstrap function for system initialization • In-application programming • In-circuit debug Following each reset, the processor automatically starts execution at address 8000h in the utility ROM, allowing ROM code to perform any necessary system support functions.
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MAXQ7665/MAXQ7666 User’s Guide 1.2.3.4 Stack Memory The MAXQ7665/MAXQ7666 provide a 16 x 16 hardware stack to support subroutine calls and system interrupts. A 16-bit wide on-chip stack is provided by the MAXQ7665/MAXQ7666 for storage of program return addresses and general-purpose use.
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MAXQ7665/MAXQ7666 User’s Guide MAXQ7665/MAXQ7666 MEMORY MAP (DEFAULT CONDITION, UPA = 0) PROGRAM MEMORY 15 MAXQ7665/MAXQ7666 MEMORY MAP (UPA = 1, CDA IS DON’T CARE) PROGRAM MEMORY DATA MEMORY 0 15 0 LOGICAL SPACE A100h 0 15 FFFFh FFFFh DATA MEMORY 0 15 FFFFh FFFFh LOGICAL SPACE P3 PHYSICAL PROGRAM (P3) Physical Program (P0) P2 A000h PHYSICAL PROGRAM (P2) LOGICAL SPACE 9000h 9000h 9000h LOGICAL UTILITY ROM UTILITY ROM 8000h 8000h PHYSICAL PROGRAM (P1) 8000h 8000h PHYSICAL PROGRAM
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MAXQ7665/MAXQ7666 User’s Guide • The utility ROM can be accessed as data with offset at 8000h. • One page (byte access mode) or two pages (word access mode) can be accessed as data with offset at 0000h as determined by the CDA1:0 bits. 1.2.3.7 Data Alignment To support merged program and data memory operation while maintaining efficiency on memory space usage, the data memory must be able to support both byte-wide and word-wide accessing.
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MAXQ7665/MAXQ7666 User’s Guide MAXQ7665/MAXQ7666 MEMORY MAP (UPA = 0, EXECUTING FROM UTILITY ROM) PROGRAM MEMORY 15 DATA MEMORY 0 15 0 FFFFh LOGICAL SPACE P3 A100h LOGICAL DATA P2 A000h LOGICAL SPACE 9000h CDA1 = 1 UTILITY ROM 8000h 8000h PHYSICAL PROGRAM (P1) 0100h A1 PHYSICAL PROGRAM (P0) =0 CD PHYSICAL DATA 0000h 0000h MAXQ7665/MAXQ7666 MEMORY MAP (UPA = 0, EXECUTING FROM LOGICAL DATA MEMORY) PROGRAM MEMORY 15 DATA MEMORY 0 0 15 FFFFh LOGICAL SPACE A100h FFFFh P3 LOGICAL SPACE
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MAXQ7665/MAXQ7666 User’s Guide EXECUTING FROM UTILITY ROM (UPA = 0, ONLY P1, P2 PRESENT) PROGRAM MEMORY 15 DATA MEMORY 0 7 0 FFFFh FFFFh LOGICAL SPACE A100h LOGICAL DATA MEMORY A000h LOGICAL SPACE 9000h UTILITY ROM 8000h 8000h 1 A0 = LOGICAL SPACE CD PHYSICAL PROGRAM (P1) 0200h A0 =0 PHYSICAL DATA CD PHYSICAL PROGRAM (P0) 0000h 0000h EXECUTING FROM LOGICAL DATA MEMORY (UPA = 0, ONLY P1, P2 PRESENT) PROGRAM MEMORY 15 DATA MEMORY 7 0 0 FFFFh FFFFh LOGICAL SPACE LOGICAL SPACE A100h LO
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MAXQ7665/MAXQ7666 User’s Guide 1.2.3.9 Program and Data Memory Mapping Example 1: MAXQ7665B Figures 1-7, 1-8, and 1-9 show the mapping of physical memory segments into the program and data memory space for the MAXQ7665B with 32k x 16 (64kB) program flash memory. In this case and all cases when program flash memory size is ≤ 32k x 16, the memory mapping is straightforward as there is no overlapping among the program, utility ROM, and data memory segments.
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MAXQ7665/MAXQ7666 User’s Guide DATA SPACE (BYTE MODE) PROGRAM SPACE DATA SPACE (WORD MODE) FFFFh 256 x 16 DATA SRAM A0FFh A000h FFFFh 32k x 8 PROGRAM FLASH 32k x 16 PROGRAM FLASH PAGE 0 (IF CDA0 = 0) EXECUTING FROM PAGES 0 AND 1 8FFFh PAGE 1 (IF CDA0 = 1) 4k x 16 UTILITY ROM 8000h 8000h 8000h 7FFFh 32k x 16 PROGRAM FLASH 0000h 512 x 8 DATA SRAM 01FFh 0000h 256 x 16 DATA SRAM 00FFh 0000h Figure 1-8.
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MAXQ7665/MAXQ7666 User’s Guide 1.2.3.10 Program and Data Memory Mapping Example 2: MAXQ7666 Figures 1-10, 1-11, and 1-12 show the mapping of physical memory segments into the program and data memory space for the MAXQ7666 with 8k x 16 (16kB) program flash memory, 256B data flash memory, and 512B data RAM.
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MAXQ7665/MAXQ7666 User’s Guide DATA SPACE (BYTE MODE) EXECUTING FROM PROGRAM SPACE DATA SPACE (WORD MODE) A0FFh 256 x 16 DATA RAM A000h 8FFFh 4k x 16 UTILITY ROM 8000h 407Fh 128 x 16 DATA FLASH 4000h 4k x 16 UTILITY ROM 8000h 256 x 8 DATA FLASH (CDA0 = 1) 1FFFh 0000h 8000h 00FFh 407Fh 128 x 16 DATA FLASH 0000h 4000h 3FFFh 1FFFh 16k x 8 PROGRAM FLASH (CDA0 = 0) 8k x 16 PROGRAM FLASH 8FFFh 9FFFh 8kxx16 8 4k UTILITY ROM 8k x 16 PROGRAM FLASH 0000h 0000h Figure 1-12.
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MAXQ7665/MAXQ7666 User’s Guide 1.2.4.2 Interrupt System Operation The interrupt handler hardware responds to any interrupt event when it is enabled. An interrupt event occurs when an interrupt flag is set. All interrupt requests are sampled at the rising edge of the clock and can be serviced by the processor one clock cycle later, assuming the request does not hit the interrupt exception window.
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MAXQ7665/MAXQ7666 User’s Guide SYSTEM MODULES WDIF (WATCHDOG) EWDI (LOCAL ENABLE) IMS (SYSTEM ENABLE) MODULE 0 IE0 ƒ IE1 ƒ IE7 ƒ EX0-EX7 IM0 (MODULE 0 ENABLE) INS (INTERRUPT IN SERVICE) RI INTERRUPT VECTOR TI ESI (LOCAL ENABLES) IGE (GLOBAL ENABLE) MODULE 1 SPIC ROVR WCOL MODF ESPII (LOCAL ENABLE) IM1 (MODULE 1 ENABLE) MODULE 2 T2CL TF2CL TCC2 TF2 ET2L, ET2 (LOCAL ENABLES) IM2 (MODULE 2 ENABLE) NOTE: ONLY A FEW OF THE MANY POSSIBLE MAXQ PERIPHERAL MODULES ARE SHOWN IN THIS INTERRUPT HIERA
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MAXQ7665/MAXQ7666 User’s Guide 1.2.4.4 Interrupt Prioritization by Software All interrupt sources of the MAXQ7665/MAXQ7666 microcontrollers naturally have the same priority. However, when CPU operation vectors to the programmed Interrupt Vector address, the order in which potential interrupt sources are interrogated is left entirely up to the user, as this often depends upon the system design and application requirements.
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MAXQ7665/MAXQ7666 User’s Guide Table 1-6. MAXQ7665/MAXQ7666 Interrupt Sources and Control Bits MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG Watchdog Interrupt INTERRUPT IMS (IMR.7) EWDI (WDCN.6) WDIF (WDCN.3) External Interrupt 0 IM0 (IMR.0) EX0 (EIE0.0) IE0 (EIF0.0) External Interrupt 1 IM0 (IMR.0) EX1 (EIE0.1) IE1 (EIF0.1) External Interrupt 2 IM0 (IMR.0) EX2 (EIE0.2) IE2 (EIF0.2) External Interrupt 3 IM0 (IMR.0) EX3 (EIE0.3) IE3 (EIF0.3) External Interrupt 4 IM0 (IMR.
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MAXQ7665/MAXQ7666 User’s Guide Table 1-6. MAXQ7665/MAXQ7666 Interrupt Sources and Control Bits (continued) INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG CAN 0 Message Center 3 Receive IM4 (IMR.4) ERI (C0M3C.5) INTRQ (C0M3C.4) CAN 0 Message Center 3 Transmit IM4 (IMR.4) ETI (C0M3C.6) INTRQ (C0M3C.4) CAN 0 Message Center 4 Receive IM4 (IMR.4) ERI (C0M4C.5) INTRQ (C0M4C.4) CAN 0 Message Center 4 Transmit IM4 (IMR.4) ETI (C0M4C.6) INTRQ (C0M4C.
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MAXQ7665/MAXQ7666 User’s Guide Table 1-6. MAXQ7665/MAXQ7666 Interrupt Sources and Control Bits (continued) INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG Digital Brownout IM5 (IMR.5) DVBIE (AIE.4) DVBI (ASR.4) I/O Voltage Brownout IM5 (IMR.5) VIOBIE (AIE.5) VIOBI (ASR.5) High-Frequency Oscillator Failure IM5 (IMR.5) HFFIE (AIE.6) HFFINT (ASR.6) 1.3 Programming The following section provides a programming overview of the MAXQ7665/MAXQ7666.
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MAXQ7665/MAXQ7666 User’s Guide Generally, prefixing operations can be inserted automatically by the assembler as needed, so that (for example) move DP[0], #1234h actually assembles as move PFX[0], #12h move DP[0], #34h However, the operation move DP[0], #0055h does not require a prefixing operation even though the register DP[0] is 16-bit. This is because the prefix value defaults to zero, so the line move is not required. PFX[0], #00h 1.3.
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MAXQ7665/MAXQ7666 User’s Guide 1.3.3.4.1 8-Bit Destination ← Low Byte (16-Bit Source) The simplest transfer possibility would be loading an 8-bit register with the low byte of a 16-bit register. This transfer does not require use of GR and requires a prefix only if the destination or source register are outside of the single cycle write or read regions, 0–7h and 0–Fh, respectively.
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MAXQ7665/MAXQ7666 User’s Guide If the high byte needs to be cleared to 00h, the operation can be shortened by transferring only the GRL byte to the 16-bit destination (example follows): move move GR, DP[0] DP[0], GRL ; move DP[0] to the GR register ; store the new DP[0] value, 00h used for high byte 1.3.4 Reading and Writing Register Bits The MOVE instruction can also be used to directly set or clear any one of the lowest 8 bits of a peripheral register in module 0h-5h or a system register in module 8h.
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MAXQ7665/MAXQ7666 User’s Guide • XOR src (Logical XOR active accumulator with source) • CPL (Bit-wise complement active accumulator) • NEG (Negate active accumulator) • SLA (Arithmetic shift left on active accumulator) • SLA2 (Arithmetic shift left active accumulator two bit positions) • SLA4 (Arithmetic shift left active accumulator four bit positions) • SRA (Arithmetic shift right on active accumulator) • SRA2 (Arithmetic shift right active accumulator two bit positions) • SRA4 (Arithmetic shift right ac
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MAXQ7665/MAXQ7666 User’s Guide For the modulo increment or decrement operation, the selected range of bits in AP are incremented or decremented. However, if these bits roll over or under, they simply wrap around without affecting the remaining bits in the accumulator pointer.
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MAXQ7665/MAXQ7666 User’s Guide 1.3.5.4 ALU Operations Using Only the Active Accumulator The following arithmetic and logical operations operate only on the active accumulator.
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MAXQ7665/MAXQ7666 User’s Guide 1.3.6.2 Zero Flag The Zero flag (PSF.7) is a dynamic flag that reflects the current state of the active accumulator Acc. If all bits in the active accumulator are zero, the Zero flag equals 1. Otherwise, it equals 0. Since the Zero flag is a dynamic reflection of (Acc = 0), any instruction that changes the value in the active accumulator can potentially change the value of the Zero flag.
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MAXQ7665/MAXQ7666 User’s Guide • MOVE Acc., C (Set selected active accumulator bit to Carry) • AND Acc. (Carry = Carry AND selected active accumulator bit) • OR Acc. (Carry = Carry OR selected active accumulator bit) • XOR Acc. (Carry = Carry XOR selected active accumulator bit) • JUMP C, src (Jump if Carry flag is set) • JUMP NC, src (Jump if Carry flag is cleared) 1.3.6.5 Overflow Flag The Overflow flag (PSF.
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MAXQ7665/MAXQ7666 User’s Guide 1.3.7.3 Conditional Jumps Conditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S). Except where noted for JUMP E and JUMP NE, the absolute and relative operands allowed are the same as for the unconditional JUMP command.
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MAXQ7665/MAXQ7666 User’s Guide If loop execution speed is critical and a relative jump cannot be used, one might consider preloading an internal 16-bit register with the src loop address for the ‘DJNZ LC[n], src’ loop. This ensures that the prefix register will not be needed to supply the loop address and always yields the fastest execution of the DJNZ instruction.
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MAXQ7665/MAXQ7666 User’s Guide INS is set automatically on entry to the interrupt handler and cleared automatically on exit (RETI). IntHandler: push PSF ; save C since used in identification process move C, IIR.X ; check highest priority flag in IIR jump C, ISR_X ; if IIR.X is set, interrupt from module X move C, IIR.Y ; check next highest priority int source jump C, ISR_Y ; if IIR.Y is set, interrupt from module Y ... ISR_X: ...
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MAXQ7665/MAXQ7666 User’s Guide The POP instruction removes a value from the stack and then decrements the stack pointer. The @SP-- stack access mnemonic is the associated source specifier that generates this behavior, thus the following two instructions are equivalent: pop PSF move PSF, @SP-The POPI instruction is equivalent to the POP instruction but additionally clears the INS bit to 0.
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MAXQ7665/MAXQ7666 User’s Guide Each data pointer (DP[n]) and Frame Pointer base (BP) register is actually implemented internally as a 17-bit register (e.g., 16:0). The Frame Pointer offset register (OFFS) is implemented internally as a 9-bit register (e.g., 8:0). The WBSn bit for the respective pointer controls whether the highest 16 bits (16:1) of the pointer are in use, as is the case for word mode (WBSn = 1) or whether the lowest 16 bits (15:0) are in use, as will be the case for byte mode (WBSn = 0).
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MAXQ7665/MAXQ7666 User’s Guide move move move move move move move move move move move move move @BP[--Offs], @BP[Offs++] @DP[0], @DP[0]++ @DP[1], @DP[1]++ @BP[Offs], @BP[Offs++] @DP[0], @DP[0]-@DP[1], @DP[1]-@BP[Offs], @BP[Offs--] DP[0], @DP[0]++ DP[0], @DP[0]-DP[1], @DP[1]++ DP[1], @DP[1]-Offs, @BP[Offs--] Offs, @BP[Offs++] 1.4 System Register Descriptions The MAXQ7665/MAXQ7666 system register map is shown in Table 1-8. The system register bit functions and reset value are shown in Table 1-9.
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Maxim Integrated A[n].11 A[n].10 A[n].9 A[n].8 0 0 0 0 LC[1].14 LC[1].15 0 LC[1] 0Dh[07h] LC[1].7 0 LC[0].7 0 IV.7 0 — 0 IP.7 0 LC[1].6 0 LC[0].6 0 IV.6 0 — 0 IP.6 0 — 0 DPC 0Eh[04h] 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 OFFS.6 0 LC[1].8 0 LC[0].8 0 IV.8 0 — 0 IP.8 0 0 0 LC[1].9 0 LC[0].9 0 IV.9 0 — 0 IP.9 0 OFFS.7 0 LC[1].10 0 LC[0].10 0 IV.10 0 — 0 IP.10 0 0 PFX[n].6 OFFS 0 LC[1].11 0 LC[0].11 0 IV.
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1-45 GR.14 GR.15 0 GR 0Eh[05h] GR.7 7 GR.6 6 0 0Eh[08h] GRS.7 0 BP.7 0 GRS.6 0 BP.6 0 DP[1].13 0 DP[0].13 0 FP.13 0 GRXL.13 0 DP[1].12 0 DP[0].12 0 FP.12 0 GRXL.12 0 DP[1].11 0 DP[0].11 0 FP.11 0 GRXL.11 0 DP[1].10 0 DP[0].10 0 FP.10 0 GRXL.10 0 DP[1].9 0 DP[0].9 0 FP.9 0 GRXL.9 0 DP[1].8 0 DP[0].8 0 FP.8 0 GRXL.8 0 DP[1].7 0 DP[0].7 0 FP.7 0 GRXL.7 0 DP[1].6 0 DP[0].6 0 FP.6 0 GRXL.6 0 DP[1].5 0 DP[0].5 0 FP.5 0 GRXL.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.1 Accumulator Pointer Register (AP) Register Description: Register Name: Register Address: Accumulator Pointer Register AP Module 08h, Index 00h Bit # 7 6 5 4 3 2 1 0 Name — — — — AP.3 AP.2 AP.1 AP.0 Reset 0 0 0 0 0 0 0 0 Access r r r r rw rw rw rw r = read, w = write Note: This register is cleared to 00h on all forms of reset. Bits 7 to 4: Reserved. Read 0, write ignored. Bits 3 to 0: Accumulator Select 3 to 0 (AP.3 to AP.0).
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MAXQ7665/MAXQ7666 User’s Guide Bits 2 to 0: Accumulator Pointer Auto-Increment/Decrement Modulus (MOD2 to MOD0). If these bits are set to a non-zero value, the accumulator pointer (AP3:AP0) will be automatically incremented or decremented following each arithmetic or logical operation. The mode for the auto-increment/decrement is determined as follows: MOD2:MOD0 AUTO-INCREMENT/DECREMENT MODE 000 No auto-increment/decrement (default). 001 Increment/decrement AP[0] modulo 2.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.4 Interrupt and Control Register (IC) Register Description: Register Name: Register Address: Interrupt and Control Register IC Module 08h, Index 05h Bit # 7 6 5 4 3 2 1 0 Name — — CGDS — — — INS IGE Reset 0 0 0 0 0 0 0 0 Access r r rw r r r rw rw r = read, w = write Note: This register is cleared to 00h on all forms of reset. Bits 7, 6, 4, 3, and 2: Reserved. Read 0, write ignored. Bit 5: System Clock Gating Disable (CGDS).
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MAXQ7665/MAXQ7666 User’s Guide 1.4.6 System Control Register (SC) Register Description: Register Name: Register Address: Bit # System Control Register SC Module 08h, Index 08h 7 6 5 4 3 2 1 0 Name TAP — CDA1 CDA0 UPA ROD PWL — Reset 1 0 0 0 0 0 1 0 Access rw r rw rw rw rw rw r r = read, w = write Note: This register is reset to 100000s0b on all forms of reset. Bit 1 (PWL) is set to 1 on a power-on reset only. Bit 7: Test Access (JTAG) Port Enable (TAP).
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MAXQ7665/MAXQ7666 User’s Guide 1.4.7 Interrupt Identification Register (IIR) The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module. The eighth bit, IIS, indicates a pending system interrupt, such as from the watchdog timer. The interrupt pending flags will be set only for enabled interrupt sources waiting for service.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.9 Watchdog Timer Control Register (WDCN) The 8-bit WDCN register is part of the system register group and used to provide system control. It controls the watchdog timeout period and interrupt or reset generation on watchdog timeout. The watchdog timer is clocked by the internal 7.6MHz RC oscillator. See Section 5 for a description of this register.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.11 Prefix Register (PFX[n]) Register Description: Register Name: Register Address: Bit # Prefix Register PFX[n] Module 0Bh, Index 0nh 15 14 13 12 11 10 9 8 Name PFX[n].15 PFX[n].14 PFX[n].13 PFX[n].12 PFX[n].11 PFX[n].10 PFX[n].9 PFX[n].8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name PFX[n].7 PFX[n].6 PFX[n].5 PFX[n].4 PFX[n].3 PFX[n].2 PFX[n].1 PFX[n].
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MAXQ7665/MAXQ7666 User’s Guide 1.4.12 Instruction Pointer Register (IP) Register Description: Register Name: Register Address: Bit # Instruction Pointer Register IP Module 0Ch, Index 00h 15 14 13 12 11 10 9 8 Name IP.15 IP.14 IP.13 IP.12 IP.11 IP.10 IP.9 IP.8 Reset 1 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.14 Interrupt Vector Register (IV) Register Description: Register Name: Register Address: Bit # Interrupt Vector Register IV Module 0Dh, Index 02h 15 14 13 12 11 10 9 8 Name IV.15 IV.14 IV.13 IV.12 IV.11 IV.10 IV.9 IV.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 IV.7 IV.6 IV.5 IV.4 IV.3 IV.2 IV.1 IV.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.16 Loop Counter 1 Register (LC[1]) Register Description: Register Name: Register Address: Bit # Loop Counter 1 Register LC[1] Module 0Dh, Index 07h 15 14 13 12 11 10 9 8 Name LC[1].15 LC[1].14 LC[1].13 LC[1].12 LC[1].11 LC[1].10 LC[1].9 LC[1].8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name LC[1].7 LC[1].6 LC[1].5 LC[1].4 LC[1].3 LC[1].2 LC[1].1 LC[1].
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MAXQ7665/MAXQ7666 User’s Guide 1.4.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.19 General Register (GR) Register Description: Register Name: Register Address: Bit # Name General Register GR Module 0Eh, Index 05h 15 14 13 12 11 10 9 8 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.21 Frame Pointer Base Register (BP) Register Description: Register Name: Register Address: Bit # Frame Pointer Base Register BP Module 0Eh, Index 07h 15 14 13 12 11 10 9 8 Name BP.15 BP.14 BP.13 BP.12 BP.11 BP.10 BP.9 BP.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name BP.7 BP.6 BP.5 BP.4 BP.3 BP.2 BP.1 BP.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.23 General Register High Byte (GRH) Register Description: Register Name: Register Address: Bit # General Register High Byte GRH Module 0Eh, Index 09h 7 6 5 4 3 2 1 0 Name GRH.7 GRH.6 GRH.5 GRH.4 GRH.3 GRH.2 GRH.1 GRH.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Note: This register is cleared to 00h on all forms of reset. Bits 7 to 0: General Register High Byte Bits 7 to 0 (GRH.7 to GRH.0).
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MAXQ7665/MAXQ7666 User’s Guide 1.4.25 Frame Pointer Register (FP) Register Description: Register Name: Register Address: Bit # Frame Pointer Register FP Module 0Eh, Index 0Bh 15 14 13 12 11 10 9 8 Name FP.15 FP.14 FP.13 FP.12 FP.11 FP.10 FP.9 FP.8 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name FP.7 FP.6 FP.5 FP.4 FP.3 FP.2 FP.1 FP.
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MAXQ7665/MAXQ7666 User’s Guide 1.4.27 Data Pointer 1 Register (DP[1]) Register Description: Register Name: Register Address: Bit # Data Pointer 1 Register DP[1] Module 0Fh, Index 07h 15 14 13 12 11 10 9 8 Name DP[1].15 DP[1].14 DP[1].13 DP[1].12 DP[1].11 DP[1].10 DP[1].9 DP[1].8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name DP[1].7 DP[1].6 DP[1].5 DP[1].4 DP[1].3 DP[1].2 DP[1].1 DP[1].
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MAXQ7665/MAXQ7666 User’s Guide Table 1-10.
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1-63 0 PR0.14 PR0.15 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 14 15 s = Dependent on the pin’s state. 00h[1Fh] PR0 00h[1Eh] SMD0 00h[1Dh] SCON0 00h[13h] EIES0 00h[10h] PD0 00h[0Bh] EIE0 00h[08h] PI0 00h[07h] SBUF0 00h[03h] EIF0 00h[00h] PO0 REGISTER 0 PR0.13 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 13 0 PR0.12 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 12 0 PR0.
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Maxim Integrated MB.13 0 MC2.13 0 0 MA.14 0 MB.14 0 MC2.14 0 MA.15 0 MB.15 0 MC2.15 0 — 0 — 0 0 0 — 0 — 0 — 0 SPIB.13 0 MC0.13 0 0 — 0 — 0 — 0 — 0 — 0 SPIB.12 0 MC0.12 0 MC1.12 0 MC2.12 0 MB.12 0 MA.12 0 — 12 0 — 0 — 0 — 0 — 0 — 0 SPIB.11 0 MC0.11 0 MC1.11 0 MC2.11 0 MB.11 0 MA.11 0 — 11 0 — 0 — 0 — 0 — 0 — 0 SPIB.10 0 MC0.10 0 MC1.10 0 MC2.10 0 MB.10 0 MA.
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1-65 02h[10h] T2CFG0 02h[0Fh] T2C1 02h[0Eh] T2R1 02h[0Dh] T2V1 02h[0Ch] T2CNB1 02h[0Bh] T2C0 02h[0Ah] T2R0 02h[09h] T2V0 02h[08h] T2CNB0 02h[07h] T2CH1 02h[06h] T2RH1 02h[05h] T2H1 02h[04h] T2CNA1 02h[03h] T2CH0 02h[02h] T2RH0 02h[01h] T2H0 02h[00h] T2CNA0 REGISTER 0 0 0 — 0 — 0 T2C1.14 0 T2C1.15 0 T2R1.14 0 T2R1.15 0 T2V1.14 0 T2V1.15 0 — 0 — 0 T2C0.14 0 T2C0.15 0 T2R0.14 0 T2R0.15 0 T2V0.14 0 T2V0.
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Maxim Integrated 0 0 — 13 12 0 — 11 0 — 0 — 10 db db db db db 0 0 0 ICDD.14 0 ICDD.15 0 ICDA.14 0 ICDA.15 0 — 0 — 0 — 0 — — — db db 0 ICDD.13 0 ICDA.13 0 — 0 — 0 — db 0 ICDD.12 0 ICDA.12 0 — 0 — 0 — db 0 ICDD.11 0 ICDA.11 0 — 0 — 0 — db 0 ICDD.10 0 ICDA.10 0 — 0 — 0 — db ICDT1.15 ICDT1.14 ICDT1.13 ICDT1.12 ICDT1.11 ICDT1.10 db ICDT0.15 ICDT0.14 ICDT0.13 ICDT0.12 ICDT0.11 ICDT0.
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1-67 03h[10h] T2CFG2 03h[0Bh] T2C2 03h[0Ah] T2R2 03h[09h] T2V2 03h[08h] T2CNB2 03h[03h] T2CH2 03h[02h] T2RH2 03h[01h] T2H2 03h[00h] T2CNA2 REGISTER 0 0 0 — 0 — 0 T2C2.14 0 T2C2.15 0 T2R2.14 0 T2R2.15 0 T2V2.14 0 T2V2.15 0 — 0 — 0 — 0 — — — 0 — — 0 0 — 0 14 — 15 0 — 0 T2C2.13 0 T2R2.13 0 T2V2.13 0 — 0 — 0 — 0 — 0 — 13 12 0 — 0 T2C2.12 0 T2R2.12 0 T2V2.12 0 — 0 — 0 — 0 — 0 — 0 — 0 T2C2.11 0 T2R2.11 0 T2V2.
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Maxim Integrated 04h[17h] C0M7C 04h[16h] C0M6C 04h[15h] C0M5C 04h[14h] C0M4C 04h[13h] C0M3C 04h[12h] C0M2C 04h[11h] C0M1C 04h[09h] C0TMA 04h[08h] C0RMS 04h[07h] C0DB 04h[06h] C0DP 04h[05h] COR 04h[04h] C0RE 04h[03h] C0TE 04h[02h] C0IR 04h[01h] C0S 04h[00h] C0C REGISTER 0 0 C0DB.12 0 C0DP.12 0 — 0 — 0 — 0 — 0 — 0 — 12 0 C0DB.11 0 C0DP.11 0 — 0 — 0 — 0 — 0 — 0 — 11 0 C0DB.10 0 C0DP.10 0 — 0 — 0 — 0 — 0 — 0 — 10 9 0 C0DB.
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1-69 04h[1Fh] C0M15C 04h[1Eh] C0M14C 04h[1Dh] C0M13C 04h[1Ch] C0M12C 04h[1Bh] C0M11C 04h[1Ah] C0M10C 04h[19h] C0M9C 04h[18h] C0M8C REGISTER 0 0 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — — — 14 15 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 13 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 12 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 11 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 10 9 0 — 0 — 0 — 0 — 0 — 0 — 0
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Maxim Integrated 0 — 0 — 13 0 VIBE 0 — 12 0 VDBE 0 — 11 0 0 0 — 0 — 0 DVLVL 0 VIOLVL 0 — 0 — 0 TSO.14 0 TSO.15 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 TSO.13 0 — 0 — 0 — 0 — 0 0 — 0 — 0 — 0 TSO.12 0 — 0 — 0 — 0 — 0 0 DACI.10 0 — 0 ADCDIF 1 VDPE 0 — 10 0 0 HFOC1 0 XHFRY 0 — 0 TSO.11 0 0 HFOC0 0 — 0 — 0 TSO.10 0 ADCD.11 ADCD.10 0 DACO.11 DACO.10 0 DACI.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 2: POWER-SUPPLY/SUPERVISORY MONITORING MODULE This section contains the following information: 2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 2.1.1 Power-Supply/Supervisory Module Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 2.2 Power-Supply/Supervisory Monitoring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 2-1. MAXQ7665/MAXQ7666 Power-Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .2-4 Figure 2-2. Supply Configuration 1 (Using Internal Linear Regulator) . . . . . . . . . . . . . . . . . . . . .2-11 Figure 2-3. Supply Configuration 2 (External DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 Figure 2-4. MAXQ7665/MAXQ7666 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 2: POWER-SUPPLY/SUPERVISORY MONITORING MODULE The MAXQ7665/MAXQ7666 power-supply/supervisory monitoring module supports dedicated supply pins to independently power analog, digital I/O, and digital core functions. The analog functions and digital I/O are powered from an external +5V supply, while the internal digital core is powered from a +3.3V supply, which can be supplied by an on-chip linear regulator.
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MAXQ7665/MAXQ7666 User’s Guide MAXQ7665/MAXQ7666 POWER-SUPPLY CONNECTION SCHEME AVDD ANALOG MODULE (MUX, ADC, PGA, DAC, TEMP SENSOR) AGND AGND DVDDIO DVDDIO +3.3V LINEAR REGULATOR VDDIO POWERSUPPLY MONITOR DIGITAL INPUT/ OUTPUT REGEN GNDIO DVDD DVDD RESET DVDD POWER-SUPPLY MONITOR POWERON RESET DIGITAL CORE (CPU, FLASH, RAM, OSCILLATOR, AND DIGITAL PERIPHERALS) DGND DGND DGND Figure 2-1.
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MAXQ7665/MAXQ7666 User’s Guide 2.1.1 Power-Supply/Supervisory Module Pins The power-supply module signals are shown in Table 2-1. Table 2-1. MAXQ7665/MAXQ7666 Power-Supply/Supervisory Module Pins POWER-SUPPLY SIGNAL PIN NUMBER FUNCTION 48 56 AVDD 44 50 Analog VDD Supply. AVDD is the power supply for all analog input/output functions including ADC, PGA, DAC, and temperature sensor. For the MAXQ7665/MAXQ7666, the analog supply voltage is +5.0V.
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MAXQ7665/MAXQ7666 User’s Guide 2.2 Power-Supply/Supervisory Monitoring Registers The MAXQ7665/MAXQ7666 power-supply/supervisory monitoring peripheral registers are described here. All these peripheral registers are directly accessible by the microcontroller through the module/index address. 2.2.1 Voltage Monitor Control Register (VMC) The VMC register contains the DVDD and DVDDIO voltage-monitor threshold select bits.
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MAXQ7665/MAXQ7666 User’s Guide Bits 3, 2: DVDD Brownout Interrupt Threshold Bits 1, 0 (VDBI1, VDBI0). These bits are used to select the brownout interrupt threshold level for the DVDD voltage supply. An interrupt flag (DVBI) is set if the DVDD brownout detection is enabled (VDBE = 1 in the APE register) and the DVDD voltage falls in the threshold range (see table below). To convert the interrupt flag to an interrupt, the DVDD brownout interrupt enable bit (DVBIE in the AIE register) must be set.
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MAXQ7665/MAXQ7666 User’s Guide 2.2.2 Analog Power Enable Register (APE) The APE register contains the power-enable bits to control and turn on/off the DVDDIO and DVDD power-supply voltage monitoring.
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MAXQ7665/MAXQ7666 User’s Guide 2.2.3 Analog Interrupt Enable Register (AIE) The AIE register is used to enable interrupts from a variety of analog sources including DVDDIO and DVDD brownout detection.
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MAXQ7665/MAXQ7666 User’s Guide 2.2.4 Analog Status Register (ASR) The ASR register reports the status of the DVDD and DVDDIO supply brownout detection.
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MAXQ7665/MAXQ7666 User’s Guide 2.3 Supply Configuration The MAXQ7665/MAXQ7666 use three supplies to power the internal analog, digital core, and digital I/O circuits. The supplies are configured as listed: • AVDD = +5V • DVDD = +3.3V (with internal linear regulator enabled or through an external supply) • DVDDIO = +5V Figure 2-2 and Figure 2-3 show the recommended supply configurations. Bypass capacitors should be mounted as close as possible to the body of the MAXQ7665/MAXQ7666 to reduce noise.
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MAXQ7665/MAXQ7666 User’s Guide 2.4 Linear Regulator The MAXQ7665/MAXQ7666 contain a +3.3V, low dropout (LDO) linear regulator. The regulator powers the MAXQ7665/MAXQ7666 digital core functions including the CPU, flash, SRAM, oscillator, and all the digital peripherals. The linear regulator is powered by the +5V DVDDIO supply. The REGEN signal must be connected to GNDIO to enable the internal regulator. When the internal linear regulator is disabled (REGEN connected to DVDDIO), an external +3.
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MAXQ7665/MAXQ7666 User’s Guide 2.5.1 Power-Up Counter An independent power-up counter functions as the startup counter to count 65,536 cycles of the internal 7.6MHz RC oscillator from initial power-on. This time period is verified by the counter after the DVDD level reaches the reset threshold (VRST). The counter is active only during initial power-up and is completely shut off during normal operation. 2.5.
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MAXQ7665/MAXQ7666 User’s Guide NOMINAL DVDD (+3.3V) +3.06V DVDD BROWNOUT RESET THRESHOLD RANGE VDBR[1:0] = 01 +2.77V BROWNOUT RESET INTERNAL RESET RESET PIN BOR STATE DGND Figure 2-5. MAXQ7665/MAXQ7666 Brownout Reset NOMINAL DVDD (+3.3V) +3.06V DVDD BROWNOUT RESET THRESHOLD RANGE VDBR[1:0] = 01 +2.77V +2.70V BROWNOUT RESET DEFAULT BOR THRESHOLD ~ +1.20V DGND INTERNAL RESET POWER-UP DELAY RESET PIN POR STATE BOR STATE Figure 2-6.
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MAXQ7665/MAXQ7666 User’s Guide 2.5.3 Reset Output The MAXQ7665/MAXQ7666 assert the RESET signal during power-up and also during reset conditions caused by an internal source (such as brownout, watchdog, or internal reset). On power-up, once DVDD exceeds 1.2V, RESET is asserted to be logic-low. As DVDD rises, RESET remains low.
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MAXQ7665/MAXQ7666 User’s Guide NOMINAL DVDD (+3.3V) DVDD BROWNOUT INTERRUPT THRESHOLD RANGE VDBI[1:0] = 01 +3.13V BROWNOUT INTERRUPT TRIGGER POINT BROWNOUT RESET TRIGGER POINT +3.06V +2.84V +2.77V DVDD BROWNOUT RESET THRESHOLD RANGE VDBR[1:0] = 01 BROWNOUT RESET BROWNOUT INTERRUPT INTERNAL RESET BOR STATE RESET OUTPUT DGND DVLVL FLAG (ASR[14]) VDBE BIT SET BY μC DVBI FLAG (ASR[4]) FLAG ARBITRARILY CLEARED BY μC Figure 2-7. DVDD Brownout Interrupt Threshold Detection 2.6.
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MAXQ7665/MAXQ7666 User’s Guide NOMINAL DVDDIO (+5.0V) +4.79V DVDDIO BROWNOUT INTERRUPT THRESHOLD RANGE VIOBI[1:0] = 01 +4.30V DVDDIO BROWNOUT INTERRUPT VIOLVL FLAG VIOBI FLAG VIOBI FLAG CLEARED IN INTERRUPT HANDLER GNDIO Figure 2-8. DVDDIO Brownout Interrupt Threshold Detection 2.
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MAXQ7665/MAXQ7666 User’s Guide SYSTEM CLOCK RESET RESET SAMPLING INTERNAL RESET FIRST INSTRUCTION FETCH Figure 2-9. MAXQ7665/MAXQ7666 External Reset 2.7.2 External Reset During normal operation, the MAXQ7665/MAXQ7666 devices are placed into an external reset mode by holding the RESET pin low for at least four clock cycles. If the MAXQ7665/MAXQ7666 devices are in the low-power stop mode (i.e.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 3: ANALOG I/O MODULE This section contains the following information: 3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5 3.1.1 Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 3.2 Analog I/O Module Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide 3.4 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34 3.4.1 Temperature Sensor Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3.4.2 Using the Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3.4.3 Internal Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 3-1. Analog I/O Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5 Figure 3-2. Differential Input ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 Figure 3-3. Multiplexer Input Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19 Figure 3-4A. Equivalent Input Circuit (Acquisition Mode with PGA Bypassed) . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF TABLES Table 3-1. Analog I/O Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 Table 3-2. ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 Table 3-3. PGA Gain and Channel Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20 Table 3-4. Unipolar Code Table (PGA Gain = 1) . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 3: ANALOG I/O MODULE The MAXQ7665/MAXQ7666 contain an ultra-low-power precision analog I/O module for measuring and controlling a host of sensors, motors, bridges, and other analog peripherals. The analog I/O module has all the components to make the MAXQ7665/MAXQ7666 stand-alone data-acquisition machines ideal for harsh environment applications. Except where explicitly noted, the MAXQ7665 and MAXQ7666 support identical features.
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MAXQ7665/MAXQ7666 User’s Guide 3.1.1 Analog I/O Pins The analog I/O module has 24 pins associated with the analog functions on the microcontroller. Table 3-1 shows the external interface signals used by the analog I/O module. Table 3-1. Analog I/O Module Signals SIGNAL FUNCTION AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 ADC Analog Input #. These are dedicated analog input pins connected through the internal analog multiplexer to the PGA and ADC.
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MAXQ7665/MAXQ7666 User’s Guide 3.2 Analog I/O Module Control and Status Registers The analog I/O module uses the following control and status registers. 3.2.
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MAXQ7665/MAXQ7666 User’s Guide 3.2.
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MAXQ7665/MAXQ7666 User’s Guide When ADCMX4 is cleared, the ADC input channel is configured for a differential voltage measurement. When ADCMX0 is set, the ADC’s positive and negative inputs are internally connected to the same analog input pin so the user can measure zero offset error, if any. When ADCMX4 is set, the ADC input channel is configured to measure remote or internal temperature, and the bits ADCMX3:ADCMX0 control the temperature measurement.
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MAXQ7665/MAXQ7666 User’s Guide Bits 2 to 0: ADC Source Select Bits 2 to 0 (ADCS2 to ADCS0). These bits select the ADC conversion start source used to trigger analog-to-digital conversion: ADCS2:ADCS0 CONVERSION START SOURCE 000 Timer 0. 001 Timer 1. 010 Timer 2. 011 Reserved, functions as 010 if set. 100 From ADC conversion start pin: P0.4/ADCCNV. 101 From ADC conversion start pin with inverted data. 110 Continuous conversion every 16 clocks. 111 From ADC start bit: ACNT.3.
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MAXQ7665/MAXQ7666 User’s Guide 3.2.
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MAXQ7665/MAXQ7666 User’s Guide 3.2.4 DAC Input Data Register (DACI) Register Description: Register Name: Register Address: DAC Input Data Register DACI Module 05h, Index 04h Bit # 15 14 13 12 11 10 9 8 Name — — — — DACI.11 DACI.10 DACI.9 DACI.8 Reset 0 0 0 0 0 0 0 0 Access r r r r rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name DACI.7 DACI.6 DACI.5 DACI.4 DACI.3 DACI.2 DACI.1 DACI.
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MAXQ7665/MAXQ7666 User’s Guide 3.2.6 ADC Data Register (ADCD) Register Description: Register Name: Register Address: ADC Data Register ADCD Module 05h, Index 08h Bit # 15 14 13 12 11 10 9 8 Name — — — — ADCD.11 ADCD.10 ADCD.9 ADCD.8 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name ADCD.7 ADCD.6 ADCD.5 ADCD.4 ADCD.3 ADCD.2 ADCD.1 ADCD.
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MAXQ7665/MAXQ7666 User’s Guide 3.2.
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MAXQ7665/MAXQ7666 User’s Guide 3.2.
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MAXQ7665/MAXQ7666 User’s Guide 3.2.
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MAXQ7665/MAXQ7666 User’s Guide 3.3 Analog-to-Digital Converter (ADC) Port The MAXQ7665/MAXQ7666 contain a low-power, high-precision, 12-bit, 500ksps successive approximation analog-to-digital converter (ADC) and 8 differential-input channel multiplexer. The ADC can be configured to run from a variety of conversion start sources both internal and external to the microcontroller. The ADC conversion rate is reduced to 142ksps when PGA gains greater than 1 are used to allow for adequate analog signal settling.
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MAXQ7665/MAXQ7666 User’s Guide 3.3.1 ADC Signals The MAXQ7665/MAXQ7666 ADC uses 18 external signals (other than analog supply and ground) as explained in Table 3-2. Table 3-2. ADC Signals SIGNAL PIN NUMBER FUNCTION 48-PIN 56-PIN AIN15 45 53 AIN14 46 54 AIN13 47 55 AIN12 48 56 AIN11 1 1 AIN10 2 2 AIN9 3 3 AIN8 4 4 AIN7 9 11 AIN6 10 12 AIN5 11 13 AIN4 12 14 AIN3 13 15 AIN2 14 16 AIN1 15 17 AIN0 16 18 P0.
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MAXQ7665/MAXQ7666 User’s Guide ADCMX 3 2 1 AIN14 AIN12 AIN10 AIN8 AIN6 AIN4 AIN2 2 PGG 1 0 TRK CMD AIN0 AIN15 PGA x1, x2, x4, x8, x16, x32 CIN+ 12-BIT ADC 500ksps AIN13 AIN11 CIN- AIN9 AIN7 AIN5 AIN3 AIN1 Figure 3-3.
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MAXQ7665/MAXQ7666 User’s Guide 3.3.3 True-Differential Analog Input T/H The equivalent input circuit of Figure 3-4 A and B shows the MAXQ7665/MAXQ7666’s analog input architecture when the PGA is bypassed (PGA disabled and PGA gain = 1). In track mode, a positive input capacitor is connected to AIN0, AIN2, AIN4…AIN14 and a negative input capacitor is connected to AIN1, AIN3, AIN5…AIN15 in differential mode.
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MAXQ7665/MAXQ7666 User’s Guide CAPACITIVE DAC AVDD CIN+ RIN+ AIN+ COMP CIN- CONTROL LOGIC RIN- AIN- AGND Figure 3-4A. Equivalent Input Circuit (Acquisition Mode with PGA Bypassed) CAPACITIVE DAC AVDD CIN+ RIN+ AIN+ COMP CIN- CONTROL LOGIC RIN- AIN- AGND Figure 3-4B. Equivalent Input Circuit (Hold/Conversion Mode with PGA Bypassed) 3.3.
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MAXQ7665/MAXQ7666 User’s Guide 3.3.5 Transfer Function The MAXQ7665/MAXQ7666 ADC output is straight binary in unipolar mode. Figure 3-5 shows the MAXQ7665/MAXQ7666 ADC unipolar transfer function for PGA gain of 1. Table 3-4 shows the unipolar relationship between the differential analog input voltage and the digital output code for PGA gain of 1. FFF FULL-SCALE TRANSITION FS = REFADC ZS = 0 1 LSB = REFADC / 4096 FFE FFD OUTPUT CODE (hex) FFC FFB 004 003 002 001 000 0 1 2 3 4 FS - 1.
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MAXQ7665/MAXQ7666 User’s Guide Table 3-5 shows the input range for various PGA settings (PGG2:PGG0) in unipolar mode. When the PGA is used (gain > 1), the differential input range at the analog multiplexer input is reduced by the gain factor. The maximum PGA output value is limited to 3.2V. For gain > 1, differential input range x PGA gain ≤ 3.2V and the ADC output code range is limited to 0–2621 (decimal). Table 3-5.
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MAXQ7665/MAXQ7666 User’s Guide Table 3-6. Bipolar Code Table (PGA Gain = 1) BINARY DIGITAL OUTPUT CODE ADCD11:ADCD0 HEXADECIMAL EQUIVALENT OF ADCD11:ADCD0 DECIMAL EQUIVALENT OF ADCD11:ADCD0 (CODE12) IDEAL DIFFERENTIAL INPUT VOLTAGE (V) (REFADC = 5.0V) 0111 1111 1111 0x7FF +2047 +2.49878 ± 0.5 LSB 0111 1111 1110 0x7FE +2046 +2.49756 ± 0.5 LSB 0000 0000 0001 0x001 +1 +0.00122 ± 0.5 LSB 0000 0000 0000 0x000 0 0.000 ± 0.5 LSB 1111 1111 1111 0xFFF -1 -0.00122 ± 0.
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MAXQ7665/MAXQ7666 User’s Guide 3.3.6 Programmable Gain Amplifier The MAXQ7665/MAXQ7666 programmable gain amplifier (PGA) receives its inputs from the input multiplexer and feeds its outputs to the 12-bit ADC. Figure 3-7 shows the MAXQ7665/MAXQ7666 PGA block diagram. The PGA has software-selectable gains of x1, x2, x4, x8, x16, and x32. The PGA uses a switched capacitor technique that reduces power and improves linearity and accuracy.
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MAXQ7665/MAXQ7666 User’s Guide 3.3.7 Analog Input Protection Internal ESD protection diodes limit all analog inputs to AVDD and AGND, allowing the inputs to swing from (AGND - 0.3V) to (AVDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs should not exceed AVDD by more than +50mV or be lower than AGND by -50mV. Input voltages beyond AGND - 0.3V and AVDD + 0.3V forward bias the internal protection diodes.
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MAXQ7665/MAXQ7666 User’s Guide AVDD + 0.3V ABS MAX+ REFADC MAX INPUT = AVDD AVDD REFADC AIN- DIFFERENTIAL ANALOG INPUT ABSOLUTE INPUT RANGE (EITHER AIN+ OR AIN- PIN) DIFFERENTIAL INPUT VOLTAGE RANGE AIN+ AGND AGND - 0.3V ADCIN = (AIN+ - AIN-) x PGA GAIN REFADC MIN INPUT = 1V ABS MAX- Figure 3-9. Analog Input Range Measuring a Negative Analog Input Value 3.3.
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MAXQ7665/MAXQ7666 User’s Guide 3.3.10 ADC Conversion Start Sources and Timing The MAXQ7665/MAXQ7666 ADC supports three different conversion start sources: timers, ADC convert pin, and software writes. The conversion start source provides the input trigger for the ADC to start acquisition and conversion. The ADC enable bit (ADCE) in the analog power control register (APE) must be set so the ADC block is enabled for operation.
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MAXQ7665/MAXQ7666 User’s Guide Table 3-9. ADC Dual- and Single-Edge Modes ADC DUALMODE (ADCDUL) 1 (Dual-Edge Mode) (Note: This mode is valid only with PGA gain > 1.) ADC CONVERSION SOURCE (ADCS2:ADCS0) ADC CONVERSION DESCRIPTION 000 (Timer 0) 001 (Timer 1) 010 (Timer 2) 100 (ADCCNV) Rising Edge of Conversion Source • Sets T/H into track mode. • Track duration is under user control.
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MAXQ7665/MAXQ7666 User’s Guide Table 3-9. ADC Dual- and Single-Edge Modes (continued) ADC DUALMODE (ADCDUL) ADC CONVERSION SOURCE (ADCS2:ADCS0) ADC CONVERSION TRIGGER 000 (Timer 0) 001 (Timer 1) 010 (Timer 2) 100 (ADCCNV) Rising Edge of Conversion Source • Sets T/H into track mode. • ADC control logic provides the required track duration composed of power-up delay (10 cycles), acquisition delay (3 cycles for PGA =1), and settling delay (40 cycles for PGA>1).
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MAXQ7665/MAXQ7666 User’s Guide Figure 3-10 shows single-edge-controlled ADC conversion timing when the ADC is in auto shutdown state and the PGA is bypassed. The power-up and acquisition is triggered by the rising edge of the ADC conversion start source signal ADC_CNVST. ADC_CNVST is an internal signal generated from a combination of all the three conversion start sources previously described.
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MAXQ7665/MAXQ7666 User’s Guide In dual-edged conversions, it is up to the user to provide the required power-up and acquisition delay as explained in Table 3-9. a) If ADC is in auto shutdown state, a minimum of 13 ADC clock cycles power-up and acquisition delay is required, in addition to 80 cycles PGA settling delay (PGA gain > 1) and 13 cycles ADC conversion delay for a total of at least 107 ADC clock cycles before the 12-bit result is available.
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MAXQ7665/MAXQ7666 User’s Guide 3.3.12 Using the ADC The flow chart in Figure 3-13 highlights all the steps required for initializing and using the ADC. SELECT ADC CLOCK DIVIDE RATIO IN THE OSCC REGISTER. ENABLE ADC: SET ADCE IN ANALOG POWER ENABLE REGISTER. ENABLE PGA, IF REQUIRED, AND SET PGG FOR GAIN > 1. IF PGA IS ENABLED, GIVE 5μs POWERUP/WARMUP TIME BEFORE CONVERSION. TO GET ADC DATA READY INTERRUPT AFTER A CONVERSION, SET ADCIE BIT IN ANALOG INTERRUPT ENABLE REGISTER.
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MAXQ7665/MAXQ7666 User’s Guide 3.4 Temperature Sensor The MAXQ7665/MAXQ7666 support an internal temperature sensor for local die temperature measurement and a remote temperature sensor drive to measure outside temperature. The internal temperature sensor performs local die temperature measurements with an internal diode-connected transistor.
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MAXQ7665/MAXQ7666 User’s Guide 3.4.1 Temperature Sensor Signals The MAXQ7665/MAXQ7666 temperature sensor uses four (one external diode can be connected between AIN0/AIN1, and a second diode between AIN2/AIN3) external signals in remote temperature sensor drive configuration as explained in Table 3-10. Table 3-10. Temperature Sensor Signals PIN NUMBER SIGNAL FUNCTION 48-PIN 56-PIN AIN3 13 15 AIN2 14 16 AIN1 15 17 AIN0 16 18 ADC Analog Input/Remote Temperature Sensor.
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MAXQ7665/MAXQ7666 User’s Guide Figure 3-15 shows the nominal transfer function for temperature conversions. Output coding is two’s complement with 1 LSB = +0.125°C. 7FF 7FE OUTPUT CODE (hex) 001 000 FFF FFE 801 800 -256 0 +255.875 TEMPERATURE (°C) Figure 3-15. Temperature Transfer Function 3.4.3 Internal Temperature Sensor The MAXQ7665/MAXQ7666 perform local die temperature measurements with an internal diode-connected transistor. The diode bias current is changed from 68µA to 4µA (4.
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MAXQ7665/MAXQ7666 User’s Guide 3.4.4.1 Differential Temperature Measurement For differential temperature measurements, connect the anode of a diode-connected transistor to the even input channel and the cathode to the odd input channel of an input pair AIN0/AIN1 or AIN2/AIN3. Run the two sensor connection lines parallel to each other with minimum spacing.
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MAXQ7665/MAXQ7666 User’s Guide Figure 3-16 shows a simplified functional block diagram of the MAXQ7665/MAXQ7666 DAC. REFDAC DACE DAC INPUT REGISTER PO.5/DACLOAD DAC OUTPUT REGISTER 12-BIT DAC DACOUT DAC LOAD CONTROL 0 1 2 DACLD Figure 3-16. DAC Block Diagram 3.5.1 DAC Signals The MAXQ7665/MAXQ7666 DAC external signals are explained in Table 3-12. Table 3-12. DAC Signals PIN NUMBER SIGNAL FUNCTION 48-PIN 56-PIN REFDAC 7 7 Dedicated DAC Reference Input Pin.
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MAXQ7665/MAXQ7666 User’s Guide Table 3-13 illustrates the relationship between the straight binary input and the analog output voltage. Table 3-13. DAC Input Code to Output Voltage (Gain = 1) BINARY DIGITAL INPUT CODE D11:D0 HEXADECIMAL EQUIVALENT OF D11:D0 DECIMAL EQUIVALENT OF D11:D0 (CODE12) NOMINAL OUTPUT ANALOG VOLTAGE (V) NOMINAL OUTPUT VOLTAGE (V) (REFDAC = 4.096V) 1111 1111 1111 0xFFF 4095 REFDAC x (4095/4096) +4.095 1111 1111 1110 0xFFE 4094 REFDAC x (4094/4096) +4.
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MAXQ7665/MAXQ7666 User’s Guide 3.5.4 DAC Power-Down The DAC is disabled and fully powered down if the DACE bit in the APE register is cleared. Full power-down reduces analog supply current (refer to the MAXQ7665/MAXQ7666 data sheet for exact current saving) and is ideal for infrequent data conversion. The DACE bit is the master control for DAC operation and, unless set, no DAC conversion is possible.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 4: CONTROLLER AREA NETWORK (CAN) MODULE This section contains the following information: 4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 4.2 CAN Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 4.2.1 Dual Port Memory Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide 4.3.1.1.8 Interframe Spacing (Intermission) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-48 4.3.1.2 Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-50 4.3.1.3 Error Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-51 4.3.1.4 Overload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 4-1. MAXQ7665/MAXQ7666 CAN 0 Controller Block Diagram . . . . . . . . . . . . . . . . . . . . .4-5 Figure 4-2. CAN Dual Port Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 Figure 4-3. CAN2.0A (Standard) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-47 Figure 4-4. CAN2.0B (Extended) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 4: CONTROLLER AREA NETWORK (CAN) MODULE The MAXQ7665/MAXQ7666 smart data-acquisition microcontrollers incorporate a single CAN controller (CAN 0), which provides operating modes that are fully compliant with the CAN2.0B specification. The CAN unit provides 15 message centers, each with capability to use 11-bit standard or 29-bit extended acceptance identifiers. Except where explicitly noted, the MAXQ7665 and MAXQ7666 features are identical.
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MAXQ7665/MAXQ7666 User’s Guide The priority order associated with the CAN module transmitting or receiving a message is determined by the inverse of the number of the message center, and is independent of the arbitration bits assigned to the message center. Thus, message center 2 has a higher priority than message center 14.
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MAXQ7665/MAXQ7666 User’s Guide 4.2 CAN Controller Registers 4.2.1 Dual Port Memory Space Registers This section summarizes CAN 0 control/status/mask information and CAN 0 message center registers that are located in the dual-port memory space. The CAN 0 control/status/mask information is organized in sixteen 8-bit registers. For the 15 CAN 0 message centers, each message center contains sixteen 8-bit registers.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.1.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.1.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.2 Control/Status/Mask Register Descriptions The CAN control/status/mask registers are located at either the higher order (H) or the lower order (L) byte of the dual port address location from 00h to 07h. Write access to these registers in dual port memory space is allowed only during a software initialization (SWINT = 1). A write by the microcontroller to any of these registers when SWINT = 0 will not alter any of the data in these registers.
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Media Arbitration Register 0 (C0MA0) Bit # Name 7 6 5 4 3 2 1 0 M0AA7 M0AA6 M0AA5 M0AA4 M0AA3 M0AA2 M0AA1 M0AA0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 00h(H) CAN 0 Media Arbitration Register 1 (C0MA1) Bit # 7 6 5 4 3 2 1 0 Name M1AA7 M1AA6 M1AA5 M1AA4 M1AA3 M1AA2 M1AA1 M1AA0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 01h(H) r = read, w =
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Bus Timing Register 0 (C0BT0) Bit # 7 6 5 4 3 2 1 0 Name SJW1 SJW0 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 02h(L) r = read, w = write (allowed only when SWINT = 1 via C0DP/C0DB) Bits 7 and 6: CAN Synchronization Jump Width Select (SJW1 and SJW0).
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Bus Timing Register 1 (C0BT1) Bit # 7 6 5 4 3 2 1 0 Name SMP TSEG26 TSEG25 TSEG24 TSEG13 TSEG12 TSEG11 TSEG10 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 02h(H) r = read, w = write (allowed only when SWINT = 1 via C0DP/C0DB) Bit 7: CAN Sampling Rate (SMP). The SMP bit determines the number of samples to be taken during each receive bit time. Programming SMP = 0 takes only one sample during each bit time.
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Standard Global Mask Register 0 (C0SGM0) Bit # 7 6 5 4 3 2 1 0 Name MASK28 MASK27 MASK26 MASK25 MASK24 MASK23 MASK22 MASK21 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 03h(L) CAN 0 Standard Global Mask Register 1 (C0SGM1) Bit # 7 6 5 4 3 2 1 0 Name MASK20 MASK19 MASK18 — — — — — Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 03h(H) r = read, w =
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Extended Global Mask Register 1 (C0EGM1) Bit # 7 6 5 4 3 2 1 0 Name MASK20 MASK19 MASK18 MASK17 MASK16 MASK15 MASK14 MASK13 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 04h(H) CAN 0 Extended Global Mask Register 2 (C0EGM2) Bit # 7 6 5 4 3 2 1 0 Name MASK12 MASK11 MASK10 MASK9 MASK8 MASK7 MASK6 MASK5 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 0
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Message Center 15 Mask Register 0 (C0M15M0) Bit # 7 6 5 4 3 2 1 0 Name MASK28 MASK27 MASK26 MASK25 MASK24 MASK23 MASK22 MASK21 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 06h(L) CAN 0 Message Center 15 Mask Register 1 (C0M15M1) Bit # 7 6 5 4 3 2 1 0 Name MASK20 MASK19 MASK18 MASK17 MASK16 MASK15 MASK14 MASK13 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Message Center 15 Mask Register 3 (C0M15M3) Bit # 7 6 5 4 3 2 1 0 Name MASK4 MASK3 MASK2 MASK1 MASK0 — — — Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Dual Port Address 07h(H) r = read, w = write (allowed only when SWINT = 1 via C0DP/C0DB) CAN Message Center 15 Mask Registers 0 to 3 (C0M15M0 to C0M15M3).
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MAXQ7665/MAXQ7666 User’s Guide 4.2.3 CAN Message Center Register Descriptions The CAN message center registers are located at either the higher order (H) or the lower order (L) byte of the dual port address locations from 08h to 7Fh. The microcontroller has read/write access to these locations at any time independent of the state of SWINT. All message centers (y = 1–15) are identical, with the exception of 15, which has some minor differences noted in the register descriptions.
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Message Center y Arbitration Register 3 (C0MyAR3) Bit # 7 6 5 4 3 2 1 0 Name ID4 ID3 ID2 ID1 ID0 — — WTOE Reset X X X X X X X X Access rw rw rw rw rw rw rw rw Dual Port Address (8y+2)h(L) X = Don’t care r = read, w = write (via C0DP/C0DB) CAN 0 Message Center y Arbitration Registers 0 to 3 (C0MyAR0 to C0MyAR3). These bits form the arbitration value/identification number for the message center y.
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MAXQ7665/MAXQ7666 User’s Guide Special Notes for Message Center 15: The ROW bit in message center 15 is associated with an overwrite of the shadow buffer for message center 15. The EXTRQ and DTUP bits are also shadow buffered to allow the buffered message and the message center 15 value to take on different relationships. The EXTRQ and DTUP values read by software are the current message center 15 values, rather than those of the shadow buffer, as is the case with the ROW bit.
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Message Center y Data Byte 0 (C0MyD0) Bit # 7 6 5 4 3 2 1 0 Reset X X X X X X X X Access rw rw rw rw rw rw rw rw Name Dual Port Address (8y+3)h(H) CAN 0 Message Center y Data Byte 1 (C0MyD1) Bit # 7 6 5 4 3 2 1 0 Reset X X X X X X X X Access rw rw rw rw rw rw rw rw Name Dual Port Address (8y+4)h(L) CAN 0 Message Center y Data Byte 2 (C0MyD2) Bit # 7 6 5 4 3 2 1 0 Reset X X X X X X X X Access
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MAXQ7665/MAXQ7666 User’s Guide CAN 0 Message Center y Data Byte 4 (C0MyD4) Bit # 7 6 5 4 3 2 1 0 Name Reset X X X X X X X X Access rw rw rw rw rw rw rw rw Dual Port Address (8y+5)h(H) CAN 0 Message Center y Data Byte 5 (C0MyD5) Bit # 7 6 5 4 3 2 1 0 Reset X X X X X X X X Access rw rw rw rw rw rw rw rw Name Dual Port Address (8y+6)h(L) CAN 0 Message Center y Data Byte 6 (C0MyD6) Bit # 7 6 5 4 3 2 1 0 Reset X X X X X X X X Access r
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4 CAN Global Control and Status Register Descriptions All the global CAN controls and status, as well as the individual message center control/status registers, are located in the peripheral register map. These registers are located in Module 4, indexes 0h–9h, 11h–1Fh. Note: All the registers located in the peripheral register map are directly accessible by the microcontroller using the module/index address. 4.2.4.
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MAXQ7665/MAXQ7666 User’s Guide Bit 4: Low-Power Siesta Mode (SIESTA). Setting the SIESTA bit to 1 places the CAN 0 controller into a low-power static state after completion of the last reception, transmission, or after the arbitration was lost or an error condition occurred. Note that the term "after arbitration lost" denotes the fact the arbitration was lost and the reception following this lost arbitration is completed.
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MAXQ7665/MAXQ7666 User’s Guide processor has removed itself from the BUSOFF condition, it also clears BSS = 0, sets SWINT = 1, and clears both the transmit- and receive-error counters to 00h. The following two situations are examples of how the autobaud function works on the CAN processor.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4.
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MAXQ7665/MAXQ7666 User’s Guide C0C.1 = 1, EC96/128 = EC128. In this mode, when EC96/128 = 1 the interrupt flag indicates that either the CAN 0 transmit-error counter or the CAN 0 receive-error counter has reached an error count of 128, which represents an exceptionally high number of errors. EC96/128 = 0 indicates that the current transmit-error counter and receive error-counter both have an error count of less than 128.
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MAXQ7665/MAXQ7666 User’s Guide Bits 2, 1, 0: CAN 0 Bus Error Status 2, 1, 0 (ER2, ER1, ER0). The ER2:ER0 bits indicate the first type of error that is encountered within a CAN 0 bus frame. The following states outline the specific error type. The eighth state (111 binary) is automatically programmed into ER2:ER0, following a read of the CAN 0 status register to establish if there has been a change in an error condition when doing a future read of the CAN 0 status register.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4.3 CAN 0 Interrupt Register (C0IR) Register Description: Register Name: Register Address: CAN 0 Interrupt Register C0IR Module 04h, Index 02h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r r = read Bits 15 to 8: Reserved.
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MAXQ7665/MAXQ7666 User’s Guide The INTIN vector value does not change when a new interrupt source becomes active and the previous one has not yet been acknowledged and removed (i.e., microcontroller read of CAN 0 status register or microcontroller clear of the appropriate INTRQ bit in the respective CAN 0 message control register), regardless of the fact that the new interrupt has a higher priority or not.
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MAXQ7665/MAXQ7666 User’s Guide To properly reflect the value of each interrupt source in the C0IR register, each source must be enabled via the respective interrupt enable. These include ERIE and/or STIE enable in the case of status-change-related interrupt (01) sources, and either the ETI or ERI enable for each message center interrupt (02h–10h) source. The status values of the interrupt sources in C0IR do not, however, require setting either the EA or C0IE bits in the IE and EIE peripheral registers.
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MAXQ7665/MAXQ7666 User’s Guide 2. ERI = 1 and/or ETI = 1 Only (STIE = 0: Hardwired Method) with No Prior Interrupt Active CASE ERIE RECEPTION SUCCESSFUL? INTIN VECTOR INTRQ CAN 0 INT A 0 No Value A or 0 0 Inactive B 0 Yes Value A or 0 0 Inactive C 1 No Value A or 0 0 Inactive D 1 Yes Value A or (MCV > INTIN) 1 Active 4.2.4.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4.5 CAN 0 Receive-Error Register (C0RE) Register Description: Register Name: Register Address: CAN 0 Receive-Error Register C0RE Module 04h, Index 04h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name C0RE.7 C0RE.6 C0RE.5 C0RE.4 C0RE.3 C0RE.2 C0RE.1 C0RE.
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MAXQ7665/MAXQ7666 User’s Guide Bit 6: Increment/Decrement Select (INCDEC). This bit determines the C0DP’s auto-increment/decrement function when AID bit is set to logic 1. When INCDEC is set to logic 0, the contents of C0DP are decremented by 1 after a read/write access to the C0DB register. When INCDEC is 1, the contents of the C0DP are incremented by 1 after a read/write access to the C0DB register. Bit 5: Automatic Increment/Decrement Enable (AID).
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4.8 CAN 0 Data Buffer Register (C0DB) Register Description: Register Name: Register Address: Bit # CAN 0 Data Buffer Register C0DB Module 04h, Index 07h 15 14 13 12 11 10 9 8 Name C0DB.15 C0DB.14 C0DB.35 C0DB.12 C0DB.11 C0DB.10 C0DB.9 C0DB.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name C0DB.7 C0DB.6 C0DB.5 C0DB.4 C0DB.3 C0DB.2 C0DB.1 C0DB.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4.9 CAN 0 Receive Message Stored Register (C0RMS) Register Description: Register Name: Register Address: CAN 0 Receive Message Stored Register C0RMS Module 04h, Index 08h Bit # 15 14 13 12 11 10 9 8 Name — C0RMS.15 C0RMS.14 C0RMS.13 C0RMS.12 C0RMS.11 C0RMS.10 C0RMS.9 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name C0RMS.8 C0RMS.7 C0RMS.6 C0RMS.5 C0RMS.4 C0RMS.3 C0RMS.2 C0RMS.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4.10 CAN 0 Transmit Message Acknowledgement Register (C0TMA) Register Description: Register Name: Register Address: CAN 0 Transmit Message Acknowledgement Register C0TMA Module 04h, Index 09h Bit # 15 14 13 12 11 10 9 8 Name — C0TMA.15 C0TMA.14 C0TMA.13 C0TMA.12 C0TMA.11 C0TMA.10 C0TMA.9 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name C0TMA.8 C0TMA.7 C0TMA.6 C0TMA.5 C0TMA.4 C0TMA.3 C0TMA.
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MAXQ7665/MAXQ7666 User’s Guide 4.2.4.
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MAXQ7665/MAXQ7666 User’s Guide Bit 3: External Transmit Request (EXTRQ). (Read/clear only.) When EXTRQ is cleared to 0, there are no pending requests by external CAN nodes for this message. When EXTRQ is set to 1, a request has been made for this message by an external CAN node, but the service request has not been completed by the CAN 0 controller at the time of the read of EXTRQ.
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MAXQ7665/MAXQ7666 User’s Guide Bit 0: Data Updated (DTUP). (Unrestricted read.) When T/R = 0, DTUP can only be cleared to 0 when written by the microcontroller. A write of 1 to DTUP with T/R = 0 leaves the DTUP bit unchanged. A write of 1 to DTUP with T/R = 1 leaves the MTRQ bit unchanged. DTUP is unrestricted read/write when T/R = 1. The DTUP bit has a dual function depending on whether a message is configured for transmit or receive via the T/R bit in the CAN 0 message format register.
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MAXQ7665/MAXQ7666 User’s Guide Note: The CAN 0 message center 2 to 15 control register bits are identical to those found in the CAN 0 message center 1 control register. Refer to these descriptions for the following registers.
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MAXQ7665/MAXQ7666 User’s Guide Register Description: Register Name: Register Address: CAN 0 Message Center 4 Control Register C0M4C Module 04h, Index 14h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rc r* r* r* r = read, w = write, c = clear only, * = see description Registe
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MAXQ7665/MAXQ7666 User’s Guide Register Description: Register Name: Register Address: CAN 0 Message Center 6 Control Register C0M6C Module 04h, Index 16h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rc r* r* r* r = read, w = write, c = clear only, * = see description Registe
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MAXQ7665/MAXQ7666 User’s Guide Register Description: Register Name: Register Address: CAN 0 Message Center 8 Control Register C0M8C Module 04h, Index 18h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP Name Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rc r* r* r* r = read, w = write, c = clear only, * = see description Register
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MAXQ7665/MAXQ7666 User’s Guide Register Description: Register Name: Register Address: CAN 0 Message Center 10 Control Register C0M10C Module 04h, Index 1Ah Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rc r* r* r* r = read, w = write, c = clear only, * = see description Regis
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MAXQ7665/MAXQ7666 User’s Guide Register Description: Register Name: Register Address: CAN 0 Message Center 12 Control Register C0M12C Module 04h, Index 1Ch Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rc r* r* r* r = read, w = write, c = clear only, * = see description Regis
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MAXQ7665/MAXQ7666 User’s Guide Register Description: Register Name: Register Address: CAN 0 Message Center 14 Control Register C0M14C Module 04h, Index 1Eh Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rc r* r* r* r = read, w = write, c = clear only, * = see description Regis
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MAXQ7665/MAXQ7666 User’s Guide 4.3 CAN Operations The CAN2.0B protocol specifies two different message formats: the standard 11-bit (CAN2.0A) and the extended 29-bit (CAN2.0B), and four different frame types for CAN bus communications. The standard format, as shown in Figure 4-3, makes use of an 11-bit identifier. The extended format, as shown in Figure 4-4, makes use of a 29-bit identifier.
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MAXQ7665/MAXQ7666 User’s Guide 4.3.1.1.3 Control Field (Standard and extended format.) The control field is composed of six bits in two fields. The first field is made up of two reserved bits that are transmitted as dominant bits (Figure 4-5). The second field contains four bits that comprise the data length code (DLC).
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MAXQ7665/MAXQ7666 User’s Guide DATA FIELD OR CONTROL FIELD CRC FIELD ACK FIELD CRC DELIMITER CRC SEQUENCE Figure 4-6. CRC Field CRC FIELD END OF FRAME ACK FIELD ACK SLOT ACK DELIMITER Figure 4-7. Acknowledge Field FRAME INTERFRAME SPACE INTERMISSON FRAME BUS IDLE Figure 4-8.
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MAXQ7665/MAXQ7666 User’s Guide 4.3.1.2 Remote Frame (Standard and extended format.) The remote frame is transmitted by a CAN controller to request the transmission of the data frame with the same identifier (Figure 4-9). The remote frame is composed of seven fields, which include start of frame, arbitration field, control field, data field, CRC field, acknowledge field, and end of frame. The remote frame is used when a CAN processor wishes to request data from another node.
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MAXQ7665/MAXQ7666 User’s Guide 4.3.1.3 Error Frame The error frame is transmitted by a CAN controller when the CAN processor detects a bus error. The error frame is composed of two different fields: the superposition of the error flags from different nodes and the error delimiter. The error frame is composed of six dominant bits that violate the CAN specification bit stuffing rule. If either of the CAN processors detects an error condition, that CAN processor transmits an error frame.
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MAXQ7665/MAXQ7666 User’s Guide 4.4 General CAN Protocol-Related Issues 4.4.1 Bit Stuffing The CAN processor performs a function termed bit stuffing in accordance with the CAN2.0 protocol. The bit stuffing is a mechanism that is done on both the transmitting and receiving end of the transmission.
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MAXQ7665/MAXQ7666 User’s Guide 4.6 Initializing the CAN Controller Software initialization of the CAN controller begins with the setting of the software initialization bit (SWINT) in the CAN 0 control peripheral register. When SWINT = 1, the CAN module is disabled and the CAN transmit output (CANTXD) is placed in a recessive state.
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ER0 MAXQ7665/MAXQ7666 User’s Guide ER1 C0IE CAN INTERRUPT TXS IGE WKS RXS 1 D Q CR CAN 0 CONTROL REGISTER ERIE CAN 0 STATUS REGISTER READ STIE BSS EC96 CAN 0/1 STATUS REGISTER ER2 IM4 CAN 0 MESSAGE 1 CONTROL REGISTER ETI ERI INTRQ UPDATE CAN 0 INTERRUPT REGISTER SUCCESSFUL RECEIVE MESSAGE CENTER 1 SUCCESSFUL TRANSMIT MESSAGE CENTER 1 MESSAGE CENTER 1 MESSAGE CENTER 15 Figure 4-12.
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MAXQ7665/MAXQ7666 User’s Guide 4.8 Arbitration/Masking Considerations The CAN processor is designed to evaluate and determine if an incoming message is loaded into one of the 15 message centers. Acceptance of a message is determined by comparing the message’s ID and/or data field against the corresponding arbitration information defined for each message center. Messages that contain bit errors or which fail arbitration are discarded.
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MAXQ7665/MAXQ7666 User’s Guide 4.9 Transmitting and Receiving Messages All CAN data is sent and received through message centers. All CAN message centers are identical with the exception of message center 15. Message center 15 has been designed as a receive-only center and is shadow buffered to help prevent the loss of incoming messages when software is unable to read one message before the next one should be loaded.
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MAXQ7665/MAXQ7666 User’s Guide 4.9.4 Receiving/Responding to Remote Frame Requests The remote frame request is handled like a data frame with data length zero and the EXTRQ and RXS bits are set. Each incoming remote frame request (RFR) message is compared sequentially with each enabled (MSRDY = 1) message center starting with the lowest numbered message center (highest priority) and proceeding to the highest numbered message center.
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MAXQ7665/MAXQ7666 User’s Guide Case 2: Software-Initiated Reply (Using TIH as gating control.) CAN module wants to receive an RFR and wait for software to determine when and what is transmitted in reference to RFR. 1) Software sets T/R = 1, MSRDY = 0, DTUP = 0, and TIH = 1. 2) Software loads data into respective message center. 3) Software sets MSRDY = 1, DTUP = 1, and TIH = 1 in same instruction. Note: Software does not change MTRQ = 0 from previously completed transmission.
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MAXQ7665/MAXQ7666 User’s Guide Case 4: Software-Initiated Reply (Reply through different message center, using TIH as gating control.) CAN controller wants to receive an RFR in a message center (denoted MC1) configured to receive data (T/R = 0) and to wait for software to select another message center (denoted MC2) to send data back to remote request node. 1) Software sets T/R = 0, MSRDY = 1, and DTUP = 0 in MC1 and awaits either data frame or RFR.
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MAXQ7665/MAXQ7666 User’s Guide Important Information Concerning ID Changes When Awaiting Data from a Previous Remote Frame Request The use of acceptance filtering (MEME = 1) in conjunction with remote frame requests can result in a modification of the message center arbitration registers. Suppose, for example, that a message center is configured to transmit a remote frame request (MTRQ = 1, EXTRQ = 0, T/R = 0, and MSRDY = 1).
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MAXQ7665/MAXQ7666 User’s Guide Case 2: WTOE = 0 (Overwrites Disabled) 1) Software configures message centers 1 and 2 with the same arbitration value (abbreviated AV). 2) Software configures message centers 1 and 2 to receive (T/R = 0) and to disable message overwrite (WTOE = 0). 3) The first message received that matches AV is stored in message center 1, DTUP = 1. 4) The second message received that matches AV is stored in message center 2, DTUP = 1.
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MAXQ7665/MAXQ7666 User’s Guide The autobaud feature for the CAN module is enabled by setting the autobaud bit (C0C.2). Setting this bit activates a special loopback circuit within the CAN module that logically ANDs incoming network data received on the Rx pin with the Tx pin of the CAN module.
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MAXQ7665/MAXQ7666 User’s Guide 4.14 BUSON/BUSOFF Recovery and Error Counter Operation The CAN module contains two peripheral registers that allow software to monitor and modify (under controlled conditions) the error counts associated with the transmit- and receive-error counters in the CAN module. These registers can be read at any time. Writing the CAN transmit-error counter registers updates both the transmit-error counter registers and the receive-error counter registers with the same value.
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MAXQ7665/MAXQ7666 User’s Guide 4.15 Bit Timing Bit timing in the CAN2.0B specification is based on a unit called the nominal bit time. The nominal bit time is further subdivided into four specific time periods. 1) The SYNC_SEG time segment is where an edge is expected when synchronizing to the CAN bus. 2) The PROP_SEG time segment is provided to compensate for the physical times associated with the CAN bus network. 3) The PHASE_SEG1 and PHASE_SEG2 time segments compensate for edge phase errors.
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MAXQ7665/MAXQ7666 User’s Guide The CAN 0 bus timing register 0 (C0BT0) contains the control bits for the PHASE_SEG1 and PHASE_SEG2 time segments as well as the baud-rate prescaler (BPR5:BPR0) bits. CAN 0 bus timing register 1 (C0BT1) controls the sampling rate, the time segment two bits that control the number of clock cycles assigned to the phase segment 2 portion, and the time segment one bits that determine the number of clock cycles assigned to the phase segment 1 portion.
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MAXQ7665/MAXQ7666 User’s Guide The following restrictions apply to the above equations: t TSEG1 ≥ t TSEG2 t TSEG2 ≥ t SJW t SJW < t TSEG1 2 ≤ TS1_ LEN ≤ 16 2 ≤ TS2 _ LEN ≤ 8 (TS1_ LEN + TS2 _ LEN + 1) ≤ 25 The nominal bit time applies when a synchronization edge falls within the tSYNC_SEG period. The maximum bit time occurs when the synchronization edge falls outside of the tSYNC_SEG period, and the synchronization jump width time is added to perform the resynchronization.
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MAXQ7665/MAXQ7666 User’s Guide 4.16 CAN Bus Activity The CAN bus activity (CAN0BA) status is active when a CAN bus activity is detected on the CAN input pin (Figure 4-15). This signal is used as one of the switchback sources for PMM mode or a wake-up source for stop mode if its interrupt function is also enabled. The status bit CAN0BA in the COR register can be used by software to determine the switchback or wake-up source.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 5: OSCILLATOR/CLOCK GENERATION MODULE This section contains the following information: 5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 5.1.1 Oscillator/Clock Generation Module Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 5.2 Oscillator/Clock Generation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 5-1. Oscillator/Clock Generation Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 Figure 5-2. Oscillator Startup Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13 Figure 5-3. High-Frequency Crystal Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 Figure 5-4. Selecting External Crystal/Resonator as System Clock . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 5: OSCILLATOR/CLOCK GENERATION MODULE The MAXQ7665/MAXQ7666 oscillator/clock generation module supplies the system clock for the microcontroller core and all the peripheral modules. The MAXQ7665/MAXQ7666 are designed to operate up to 8MHz. Except where explicitly stated, the MAXQ7665 and MAXQ7666 have identical features. The MAXQ7665/MAXQ7666 oscillator/clock generation module features include: • Internal 7.
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MAXQ7665/MAXQ7666 User’s Guide DVDD WDT RESET WDIF WATCHDOG INTERRUPT FLAG WATCHDOG TIMER RESET WTRF WATCHDOG TIMER RESET FLAG POWER-ON RESET EWDI STOP WD1 WD0 EWT RWT POWERUP TIMER (/216) STOP HFIC(1:0) HFOC(1:0) XT EXTHF HFE RCE STOP XIN/ HF-CLK HIGHFREQ CLOCK/ XTAL XOUT ENABLE RC OSC XHFRY CLOCK DIVIDE MUX RGMD SWB XT EXTHF PMME SYSCLK CD1 CD0 ADC CLOCK PRESCALE ADCCLK ADCD2 ADCD1 ADCD0 CAN CLOCK PRESCALE CAN CLOCK BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Figure 5-1.
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MAXQ7665/MAXQ7666 User’s Guide 5.2 Oscillator/Clock Generation Registers The MAXQ7665/MAXQ7666 oscillator/clock generation module registers are described here. All these registers are directly accessible by the microcontroller through the module/index address. 5.2.1 Analog Status Register (ASR) The ASR register contains the high-frequency oscillator ready and failure flags. This register is cleared to its default state when it is read.
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MAXQ7665/MAXQ7666 User’s Guide 5.2.2 Oscillator Control Register (OSCC) The OSCC register contains the oscillator enable and configuration bits.
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MAXQ7665/MAXQ7666 User’s Guide Bits 9 and 8: High-Frequency Crystal Input Capacitance Select 1 and 0 (HFIC1 and HFIC0). These bits select the input capacitance of the on-chip high-frequency oscillator. The capacitor value is switched on to the XIN pin of the MAXQ7665. The possible selections are given below. Note: For the default 00 setting, only a 1.3pF capacitor is switched on. The 7pF capacitor value is essentially due to stray capacitance.
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MAXQ7665/MAXQ7666 User’s Guide 5.2.3 System Clock Control Register (CKCN) The 8-bit CKCN register is part of the system register group and used to support system clock generation. It controls the system clock speed and power management mode selection.
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MAXQ7665/MAXQ7666 User’s Guide • The SPI module’s SS (slave select input) signal is asserted in slave mode. • A CAN bus activity on its data input (CANRXD) while its interrupt is enabled. • Active debug mode is entered either by break point match or issuance of the debug command from background mode. When any of these conditions cause switchback to clear PMME to 0, the system clock rate will then revert back to the divide-by-1 mode (CD1:CD0 = 00).
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MAXQ7665/MAXQ7666 User’s Guide 5.2.4 Watchdog Timer Control Register (WDCN) The 8-bit WDCN register is part of the system register group and used to provide system control. It controls the watchdog timeout period and interrupt or reset generation on watchdog timeout. The watchdog timer is clocked by the internal 7.6MHz RC oscillator. Enabling the watchdog does not force the internal 7.6MHz RC oscillator enable (RCE) bit to logic 1.
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MAXQ7665/MAXQ7666 User’s Guide Bit 2: Watchdog Reset Flag (WTRF). This flag is set to 1 when the watchdog resets the processor. Software can check this bit following a reset to determine if the watchdog was the source of the reset. Setting this bit to 1 in software will not cause a watchdog reset. This bit is cleared by power-on reset only and is unaffected by other forms of reset.
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MAXQ7665/MAXQ7666 User’s Guide 5.3 System Clock Generation All functional modules in the MAXQ7665/MAXQ7666 are synchronized to a single system clock. This system clock can be generated from one of three possible sources: • Internal 7.6MHz RC oscillator • Internal high-frequency oscillator using external crystal or resonator circuit • External high-frequency clock signal Table 5-2 shows the registers and bits used to control clock generation and selection.
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MAXQ7665/MAXQ7666 User’s Guide INTERNAL 7.6MHz RC OSCILLATOR STARTUP FLOW POWER-ON RESET NO DVDD > ˜1.2V YES START UP 7.6MHz INTERNAL RC OSCILLATOR RESET 16-BIT POWER-UP COUNTER 8.6ms POWER-UP COUNTER DELAY NO A) POWER-UP COUNTER = 65,535? B) DVDD > DEFAULT POR THRESHOLD LEVEL (2.7V–2.99V) YES INTERNAL RC-BASED CODE EXECUTION Figure 5-2. Oscillator Startup Flow In all other cases, setting XT = 0 switches the system clock source to the internal RC immediately. The RGMD (CKCN.
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MAXQ7665/MAXQ7666 User’s Guide The crystal oscillator/resonator is disabled upon power-up, as the default mode for the MAXQ7665/MAXQ7666 is to run from the internal 7.6MHz RC oscillator. To use the external crystal/resonator, select the input (HFIC1:HFIC0) and output capacitance (HFOC1:HFOC0) of the internal high-frequency oscillator (to match the external crystal/resonator load capacitance requirement) in the OSCC register. Figure 5-3 shows the possible options. The HFE bit (OSCC.
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MAXQ7665/MAXQ7666 User’s Guide SELECTING EXTERNAL CRYSTAL/RESONATOR AS SYSTEM CLOCK SELECT XIN/XOUT CAPACITOR VALUES AND DRIVE STRENGTH: HFIC[1:0] AND HFOC[1:0] ENABLE HF OSCILLATOR HFE = 1 SELECT EXTERNAL CRYSTAL/RESONATOR AS CLOCK SOURCE XT = 1 SELECT CLOCK DIVIDE VALUE: PMME, CD1 AND CD0 BITS NO ~600μs (4096 CRYSTAL/RESONATOR CLOCK CYCLES) WARMUP DELAY WAIT FOR HIGH-FREQ OSCILLATOR FLAG TO BE SET: XHFRY = 1? CRYSTAL/RESONATOR-BASED CODE EXECUTION Figure 5-4.
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MAXQ7665/MAXQ7666 User’s Guide 5.3.3 External Clock (Direct Input) The MAXQ7665/MAXQ7666 can also obtain the system clock signal directly from an external source. In this configuration, the clock generation circuitry is driven directly by an external clock. To operate from an external clock, connect the clock source to the XIN pin and leave the XOUT pin floating. Figure 5-6 shows the external clock source configuration.
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MAXQ7665/MAXQ7666 User’s Guide 5.3.5 External Crystal-Fail Detection and Automatic Switchover The MAXQ7665/MAXQ7666 have a high-frequency oscillator-fail detection circuit. An automatic clock switchover from crystal to 7.6MHz RC oscillator is forced if: • XT = 1 (external crystal is selected as the system clock source). • XHFRY = 1 (high-frequency oscillator warmup is complete). • A clock failure (high-frequency source drops below 30kHz) is detected.
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MAXQ7665/MAXQ7666 User’s Guide 5.4 Watchdog Timer The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an event timer, or a system supervisor. As shown in Figure 5-8, the watchdog timer is driven by the internal 7.6MHz RC clock and is supplied to a series of dividers. If the watchdog interrupt and the watchdog reset are disabled (EWDI = 0 and EWT = 0), the watchdog timer is disabled and its input clock is gated off.
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MAXQ7665/MAXQ7666 User’s Guide Table 5-4. Interrupt and Reset Functions for Watchdog RCE EWT EWDI WDIF 0 x x x Watchdog disabled. OPERATION 1 0 0 x Watchdog disable, clock is gated off. 1 0 1 0 Watchdog interrupt is enabled and has not occurred. Watchdog reset function disabled. 1 0 1 1 Watchdog interrupt is enabled and has occurred. Watchdog reset function disabled. 1 1 0 0 Watchdog reset function is enabled. Watchdog interrupt is disabled.
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MAXQ7665/MAXQ7666 User’s Guide 5.5 Power Management Mode There are two major sources of power dissipation in CMOS circuitry. The first is static dissipation caused by leakage current. The second is dynamic dissipation caused by transient switching current required to charge and discharge load capacitors, as well as shortcircuit current dissipated by momentary connections between VDD and ground during gate switching.
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MAXQ7665/MAXQ7666 User’s Guide 5.5.2 Switchback Mode When power management mode is active, the MAXQ7665/MAXQ7666 operate at a reduced clock rate. Although execution continues as normal, peripherals that base their timing on the system clock such as the UART module and the SPI module may be unable to operate normally or at a high enough speed for proper application response. Additionally, interrupt latency is greatly increased.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 6: SERIAL I/O MODULE This section contains the following information: 6.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.1.1 UART Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5 6.2 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 6-1. UART Synchronous Mode (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Figure 6-2. UART Asynchronous Mode (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Figure 6-3. UART Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Figure 6-4. UART Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 6: SERIAL I/O MODULE The MAXQ7665/MAXQ7666 serial I/O module provides access to a universal asynchronous receiver/transmitter (UART) for serial communication with framing error detection. The UART is a full-duplex communication channel capable of supporting asynchronous and synchronous data transfers. The UART allows the MAXQ7665/MAXQ7666 to conveniently communicate with other RS-232 interfaceenabled devices and can support LIN-bus implementation.
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MAXQ7665/MAXQ7666 User’s Guide SBUF0 LOAD CLOCK OUTPUT SHIFT REGISTER DIVIDE BY 12 URX PIN LATCH S0 D7 D6 D5 D4 D3 D2 D1 D0 SYSTEM CLOCK DIVIDE BY 4 0 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL LOAD SERIAL BUFFER SERIAL I/O CONTROL INTS BAUD CLOCK RECEIVE DATA BUFFER WR RECEIVE BUFFER DATA CLOCK D7 D6 D5 D4 D3 D2 D1 D0 TI FLAG = SCON0.1 SBUF0 RD CLOCK RI FLAG = SCON0.0 SI RECEIVE SHIFT REGISTER SERIAL INTERRUPT UTX PIN Figure 6-1.
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MAXQ7665/MAXQ7666 User’s Guide 6.1.1 UART Pins The MAXQ7665/MAXQ7666 UART supports dedicated transmit and receive pins as described in Table 6-2. Table 6-2. MAXQ7665/MAXQ7666 UART Pins UART EXTERNAL SIGNAL PIN NUMBER 48-PIN 56-PIN UTX 22 25 UART Transmitter Output. This signal is the transmit output from the UART. In synchronous mode, the shift clock is output on this pin. URX 23 26 UART Receiver Input: This signal is the receive input for the UART.
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MAXQ7665/MAXQ7666 User’s Guide Serial Mode Definition UART MODE SM2 SM1 SM0 FUNCTION LENGTH (BITS) PERIOD 0 0 0 0 Synchronous 8 12 System Clock 0 1 0 0 Synchronous 8 4 System Clock 1 X 1 0 Asynchronous 10 64/16 Baud Clock (SMOD = 0/1) 2 0 0 1 Asynchronous 11 64/32 System Clock (SMOD = 0/1) 2 1 0 1 Asynchronous (MP) 11 64/32 System Clock (SMOD = 0/1) 3 0 1 1 Asynchronous 11 64/16 Baud Clock (SMOD = 0/1) 3 1 1 1 Asynchronous (MP) 11 64/16 Baud Clock (SMO
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MAXQ7665/MAXQ7666 User’s Guide 6.2.2 Serial Port 0 Mode Register (SMD0) Register Description: Register Name: Register Address: Serial Port 0 Mode Register SMD0 Module 00h, Index 1Eh Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name — — — — — ESI SMOD FEDE Reset 0 0 0 0 0 0 0 0 Access r r r r r rw rw rw r = read, w = write Bits 15 to 3: Reserved.
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MAXQ7665/MAXQ7666 User’s Guide 6.2.3 Phase Register 0 Register (PR0) Register Description: Register Name: Register Address: Phase Register 0 PR0 Module 00h, Index 1Fh Bit # 15 14 13 12 11 10 9 8 Name PR0.15 PR0.14 PR0.13 PR0.12 PR0.11 PR0.10 PR0.9 PR0.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name PR0.7 PR0.6 PR0.5 PR0.4 PR0.3 PR0.2 PR0.1 PR0.
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MAXQ7665/MAXQ7666 User’s Guide 6.3 Modes of Operation A detailed description of the MAXQ7665/MAXQ7666 UART modes is given in this section. 6.3.1 UART Mode 0 This mode is used to communicate in synchronous, half-duplex format with devices that accept the MAXQ7665/MAXQ7666 microcontroller as a master. Figure 6-3 shows a functional block diagram and basic timing of this mode. As can be seen, there is one bidirectional data line (URX) and one shift clock line (UTX) used for communication.
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MAXQ7665/MAXQ7666 User’s Guide SBUF0 SYSTEM CLOCK DIVIDE BY 12 0 URX PIN LATCH S0 D7 D6 D5 D4 D3 D2 D1 D0 LOAD CLOCK OUTPUT SHIFT REGISTER DIVIDE BY 4 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL LOAD SERIAL BUFFER TI FLAG = SCON0.1 SERIAL I/O CONTROL RD RECEIVE DATA BUFFER WR RECEIVE BUFFER DATA CLOCK D7 D6 D5 D4 D3 D2 D1 D0 INTS BAUD CLOCK SBUF0 CLOCK RI FLAG = SCON0.
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MAXQ7665/MAXQ7666 User’s Guide SBUF0 1 START D7 D6 D5 D4 D3 D2 D1 D0 SYSTEM CLOCK STOP LOAD CLOCK TRANSMIT SHIFT REGISTER UTX PIN LATCH S0 0 DIVIDE BY 4 0 1 DATA BUS SMOD LDSBUF RDSBUF BAUD CLOCK GENERATOR DIVIDE BY 16 SHIFT LOAD SERIAL BUFFER BAUD CLOCK SBUF0 READ SERIAL BUFFER SERIAL I/O CONTROL RD RECEIVE DATA BUFFER WR LOAD RESET START SI D7 D6 D5 D4 D3 D2 D1 D0 RI FLAG = SCON0.0 START TI FLAG = SCON0.1 CLOCK INTS RB8 = SCON0.
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MAXQ7665/MAXQ7666 User’s Guide 6.3.3 UART Mode 2 This mode uses a total of 11 bits in asynchronous, full-duplex communication as illustrated in Figure 6-5. The 11 bits consist of one start bit (logic 0), 8 data bits, a programmable 9th bit, and one stop bit (logic 1). Like mode 1, the transmissions occur on the UTX signal pin and receptions on URX. For transmission purposes, the 9th bit can be stuffed as logic 0 or 1. A common use is to put the parity bit in this location.
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MAXQ7665/MAXQ7666 User’s Guide SBUF0 LATCH S0 START D7 D6 D5 D4 D3 D2 D1 D0 1 DIVIDE BY 2 0 D8 SYSTEM CLOCK/2 STOP LOAD CLOCK TRANSMIT SHIFT REGISTER UTX PIN 0 TB8 = SCON0.3 1 DATA BUS SMOD LDSBUF RDSBUF DIVIDE BY 16 SHIFT LOAD SERIAL BUFFER SHIFT CLOCK SERIAL I/O CONTROL SBUF0 READ SERIAL BUFFER RD RECEIVE DATA BUFFER WR LOAD RESET D7 D6 D5 D4 D3 D2 D1 D0 START SI D8 RI FLAG = SCON0.0 STOP TI FLAG = SCON0.1 CLOCK INTS RB8 = SCON0.
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MAXQ7665/MAXQ7666 User’s Guide SBUF0 1 DIVIDE BY 4 0 START D8 D7 D6 D5 D4 D3 D2 D1 D0 SYSTEM CLOCK STOP LOAD CLOCK TRANSMIT SHIFT REGISTER LATCH S0 UTX PIN 0 TB8 = SCON0.3 1 DATA BUS SMOD LDSBUF RDSBUF BAUD CLOCK GENERATOR SHIFT LOAD SERIAL BUFFER DIVIDE BY 16 BAUD CLOCK SERIAL I/O CONTROL SBUF0 READ SERIAL BUFFER RD RECEIVE DATA BUFFER WR LOAD RESET D7 D6 D5 D4 D3 D2 D1 D0 START SI D8 RI FLAG = SCON0.0 STOP TI FLAG = SCON0.1 CLOCK INTS RB8 = SCON0.
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MAXQ7665/MAXQ7666 User’s Guide 6.4 Baud-Rate Generation Each mode of operation has a baud-rate generation technique associated with it. The baud-rate generation is affected by certain user options such as the power management mode enable (PMME) bit, serial mode 2 (SM2) bit, and baud-rate doubler (SMOD) bit. Table 6-3 summarizes the effects of the various user options on the UART baud clock. Table 6-3.
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MAXQ7665/MAXQ7666 User’s Guide 6.4.4 Baud-Clock Generator The baud-clock generator is basically a phase accumulator that produces a baud clock as the result of phase overflow from the most significant bit of the phase shift circuitry. As illustrated in Figure 6-7, a user-programmable 16-bit phase register (PR0) is used to select a suitable phase value for its baud clock. The phase value dictates the phase period of the accumulation process.
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MAXQ7665/MAXQ7666 User’s Guide 6.5 Framing Error Detection A framing error occurs when a valid stop bit is not detected. This results in the possible improper reception of the serial word. The UART can detect a framing error and notify the software. Typical causes of framing errors are noise and contention. The framing error condition is reported in the SCON0 register for the UART. The framing error bit, FE, is located in SCON0.7.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 7: TYPE 2 TIMER/COUNTER MODULE This section contains the following information: 7.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.1.1 Type 2 Timer/Counter I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6 7.2 Type 2 Timer/Counter Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide 7.4 Type 2 Timer/Counter Capture Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22 7.4.1 Measure Low-Pulse Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22 7.4.2 Measure High-Pulse Duration Repeatedly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23 7.4.3 Measure Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 7: TYPE 2 TIMER/COUNTER MODULE The MAXQ7665/MAXQ7666 microcontrollers have three Type 2 timer/counter modules. The Type 2 timer/counter is an auto-reload 16bit timer/counter with the following functions: • 8-bit/16-bit timer/counter • Up/down auto-reload • Counter function of external pulse • Capture • Compare The three Type 2 timer/counter modules supported in MAXQ7665/MAXQ7666 are referred to as timer 0, timer 1, and timer 2 in this document.
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MAXQ7665/MAXQ7666 User’s Guide CAPTURE T2Cx REGISTER 16-BIT CAPTURE/COMPARE EQUAL INPUT CONDITIONING SCALING GATING CLOCK T2Vx REGISTER 16-BIT UP COUNTER OVERFLOW OUTPUT CONDITIONING POLARITY SELECTION RELOAD T2Rx REGISTER 16-BIT RELOAD Figure 7-1.
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MAXQ7665/MAXQ7666 User’s Guide T2CLx REGISTER (LOWER BYTE OF T2Cx) 8-BIT CAPTURE/COMPARE LOW CAPTURE EQUAL CLOCK T2Lx REGISTER (LOWER BYTE OF T2Vx) 8-BIT UP COUNTER LOW OUTPUT CONDITIONING POLARITY SELECTION OVERFLOW RELOAD T2RLx REGISTER (LOWER BYTE OF T2Rx) 8-BIT RELOAD LOW INPUT CONDITIONING SCALING GATING T2CHx REGISTER 8-BIT CAPTURE/COMPARE HIGH EQUAL CLOCK T2Hx REGISTER 8-BIT UP COUNTER HIGH OVERFLOW OUTPUT CONDITIONING POLARITY SELECTION RELOAD CAPTURE T2RHx REGISTER 8-BIT RELOAD HIGH
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MAXQ7665/MAXQ7666 User’s Guide 7.1.1 Type 2 Timer/Counter I/O Pins Each Type 2 timer/counter module normally supports one primary input/output pin that is referred to as Tx. Table 7-1 describes the pin assignments for the three MAXQ7665/MAXQ7666 timer/counter modules. Table 7-1. Type 2 Timer/Counter Input and Output Pins TIMER/COUNTER EXTERNAL SIGNAL PIN 48 56 MULTIPLEXED WITH PORT PIN T0—Timer 0 Input/Output 24 27 P0.6 Timer 0 Input/Output. T0 is shared with GPIO port P0 bit 6.
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MAXQ7665/MAXQ7666 User’s Guide 7.2.1 Type 2 Status/Control Registers The MAXQ7665/MAXQ7666 timer/counter module registers T2CFGx (configuration), T2CNAx (control A), and T2CNBx (control B), where x = 0, 1, and 2, are described here. 7.2.1.
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MAXQ7665/MAXQ7666 User’s Guide Bits 2 and 1: Capture/Compare Function Select Bits (CCF1 and CCF0). These bits, in conjunction with the C/T2 bit, select the basic operating mode of the Type 2 timer. In the dual 8-bit mode of operation (T2MD = 1), the T2Lx timer only operates in compare mode.
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MAXQ7665/MAXQ7666 User’s Guide Bit 6: Type 2 Timer Output Enable 0 (T2OE0). This register bit enables the timer output function for the external Tx pin. The following table shows the timer output possibilities for the external pin. Note: When the timer output function on the Tx pin is enabled, the polarity bit (T2POL0) selects the starting logic level for the pin output.
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MAXQ7665/MAXQ7666 User’s Guide Bit 0: Gating Enable (G2EN). This bit enables the external Tx pin to gate the input clock to the 16-bit (T2MD = 0) or highest 8-bit (T2MD = 1) timer. Gating uses Tx as an input, so it can only be used when T2OE0 = 0 and C/T2 = 0. Gating is not possible on the low 8-bit timer (T2Lx) when the Type 2 timer is operated in dual 8-bit mode. Gating is not supported for counter mode operation (C/T2 = 1).
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MAXQ7665/MAXQ7666 User’s Guide 7.2.2 Type 2 Timer Value Registers The MAXQ7665/MAXQ7666 timer/counter registers T2Vx (timer value) and T2Hx (timer value high), where x = 0, 1, and 2, are described here. 7.2.2.1 Type 2 Timer/Counter Value Register (T2Vx) Register Description: Register Name: Register Address: Type 2 Timer/Counter Value Register T2Vx (x = 0, 1, 2) T2V0: Module 02h, Index 09h T2V1: Module 02h, Index 0Dh T2V2: Module 03h, Index 09h Bit # 15 14 13 12 11 10 9 8 Name T2Vx.15 T2Vx.
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MAXQ7665/MAXQ7666 User’s Guide 7.2.2.2 Type 2 Timer/Counter Value High Register (T2Hx) Register Description: Register Name: Register Address: Type 2 Timer/Counter Value High Register T2Hx (x = 0, 1, 2) T2H0: Module 02h, Index 01h T2H1: Module 02h, Index 05h T2H2: Module 03h, Index 01h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name T2Hx.7 T2Hx.6 T2Hx.5 T2Hx.4 T2Hx.3 T2Hx.2 T2Hx.
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MAXQ7665/MAXQ7666 User’s Guide 7.2.3 Type 2 Reload Registers The MAXQ7665/MAXQ7666 timer/counter module registers T2Rx (timer reload) and T2RHx (timer reload high), where x = 0, 1, and 2, are described here. 7.2.3.1 Type 2 Timer/Counter Reload Register (T2Rx) Register Description: Register Name: Register Address: Type 2 Timer/Counter Reload Register T2Rx (x = 0, 1, 2) T2R0: Module 02h, Index 0Ah T2R1: Module 02h, Index 0Eh T2R2: Module 03h, Index 0Ah Bit # 15 14 13 12 11 10 9 8 Name T2Rx.
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MAXQ7665/MAXQ7666 User’s Guide 7.2.3.2 Type 2 Timer/Counter Reload High Register (T2RHx) Register Description: Register Name: Register Address: Type 2 Timer/Counter Reload High Register T2RHx (x = 0, 1, 2) T2RH0: Module 02h, Index 02h T2RH1: Module 02h, Index 06h T2RH2: Module 03h, Index 02h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name T2RHx.7 T2RHx.6 T2RHx.5 T2RHx.4 T2RHx.
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MAXQ7665/MAXQ7666 User’s Guide 7.2.4 Type 2 Capture/Compare Registers The MAXQ7665/MAXQ7666 timer/counter module registers T2Cx (timer capture/compare) and T2CHx (timer capture/compare high), where x = 0, 1, and 2, are described here. 7.2.4.
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MAXQ7665/MAXQ7666 User’s Guide 7.2.4.2 Type 2 Timer/Counter Capture/Compare High Register (T2CHx) Register Description: Register Name: Register Address: Type 2 Timer/Counter Capture/Compare High Register T2CHx (x = 0, 1, 2) T2CH0: Module 02h, Index 03h T2CH1: Module 02h, Index 07h T2CH2: Module 03h, Index 03h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name T2CHx.7 T2CHx.6 T2CHx.
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MAXQ7665/MAXQ7666 User’s Guide 7.3 Type 2 Timer/Counter Operation Modes The MAXQ7665/MAXQ7666 Type 2 timer/counter supports six operation modes. Table 7-3 summarizes the modes supported by the Type 2 timer and the peripheral register bits associated with those modes. The Type 2 timer operating mode selection is illustrated in Figure 7-3. Figure 7-4 shows the PWM timer output possibilities. Table 7-3.
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MAXQ7665/MAXQ7666 User’s Guide T2Lx COMPARE MATCH T2CHx T2CLx T2Vx COMPARE MATCH OR T2Hx COMPARE MATCH TR2L T2MD T2Lx OVERFLOW T2Lx T2Vx OVERFLOW OR T2Hx OVERFLOW T2Hx T2CLK C/T2 T2RLx EDGE DETECTION AND GATING T2RHx Tx PIN INPUT CCF[1:0] G2EN TR2 SS2 T2POL[0] Figure 7-3. Type 2 Timer Mode Selection POx.x DATA (IF PDx.x = 1) T2Vx 16-BIT TIMER OR T2Hx 8-TIMER Tx PIN T2POL[0] T2OE[0] POSSIBLE INPUT USE: TIMER GATE EDGE CAPTURE/RELOAD EDGE COUNTER Figure 7-4.
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MAXQ7665/MAXQ7666 User’s Guide 7.3.1 16-Bit Timer: Auto-Reload/Compare The 16-bit auto-reload/compare mode for the Type 2 timer is in effect when the timer-mode select bit (T2MD) is cleared and the capture/compare function definition bits are both cleared (CCF1:CCF0 = 00b). The timer value is contained in the T2Vx register. The timer run control bit (TR2) starts and stops the 16-bit timer.
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MAXQ7665/MAXQ7666 User’s Guide 7.3.2 16-Bit Timer: Capture Mode The 16-bit capture mode requires that some event trigger the capture. Normally, this event will be an external edge. The CCF1:CCF0 bits define which edge(s) causes a capture to occur. If CCF1:CCF0 = 01b, a rising edge causes a capture. If CCF1:CCF0 = 10b, a falling edge causes a capture. If CCF1:CCF0 = 11b, rising and falling edges both cause a capture to occur. The CPRL2 bit enables both capture and reload to occur on the specified edge(s).
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MAXQ7665/MAXQ7666 User’s Guide 7.3.4 Dual 8-Bit Timers The dual 8-bit timer mode of operation is initiated by setting the T2MD bit to logic 1. When T2MD = 1, each 16-bit register associated with the Type 2 timer is split into separate upper and lower 8-bit registers to support dual 8-bit timers. Thus, the primary 8-bit timer is composed of T2Hx (value), T2RHx (reload), T2CHx (capture/compare), and the secondary 8-bit timer is composed of T2Lx (value), T2RLx (reload), and T2CLx (capture/compare).
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MAXQ7665/MAXQ7666 User’s Guide 7.4 Type 2 Timer/Counter Capture Application Examples The following examples are used to demonstrate some of the Type 2 timer capture functions. All examples assume that pulse and/or period measurements do not exceed 216 (i.e., 65,536) input clocks and that capture register holds the desired result. 7.4.
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MAXQ7665/MAXQ7666 User’s Guide 7.4.2 Measure High-Pulse Duration Repeatedly To measure the duration of high pulses seen on the T0 input pin repeatedly, the Type 2 timer is configured for a single-shot delayed run, gating enabled for logic-low, and capture on the falling edge. The CPRL2 bit can be set to generate a reload on each falling edge.
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MAXQ7665/MAXQ7666 User’s Guide 7.4.3 Measure Period To measure the period of the signal seen on the T0 input pin, the Type 2 timer is configured for a single-shot capture, no gating, either edge (selected by the CCF1:CCF0 bits). The CPRL2 bit can be set to generate a reload on each capture edge.
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MAXQ7665/MAXQ7666 User’s Guide 7.4.4 Measure Duty Cycle Repeatedly To measure the duty cycle of the signal seen on the T0 input pin, the Type 2 timer is configured for a single-shot delayed run with both edges defined for capture. The CPRL2 bits should be configured to 1 to request reloads on each edge. To prevent reloads on one of the edges, gating should be enabled. The T2POL0 bit specifies which edge starts/ends the capture cycle and which edge does not have a reload associated with it.
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MAXQ7665/MAXQ7666 User’s Guide 7.4.5 Overflow/Interrupt on Cumulative Time To cause an overflow only when the T0 pin has been low for some cumulative duration, the Type 2 timer can be configured to the gated compare mode of operation with an initial starting value appropriate for the cumulative duration to be detected.
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MAXQ7665/MAXQ7666 User’s Guide 7.5 Type 2 Timer/Counter Compare Application Example The following example is used to demonstrate the Type 2 timer compare function. 7.5.1 A Simple Waveform Output To output a simple waveform on the T0 pin whose frequency and duty cycle can be configured with an appropriate initial starting value for T2R0 and T2C0 registers.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 8: GENERAL-PURPOSE I/O MODULE This section contains the following information: 8.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.1 Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 8: GENERAL-PURPOSE I/O MODULE The MAXQ7665/MAXQ7666 smart data-acquisition microcontrollers provide 8 port pins for general-purpose I/O, which are grouped into the logical port P0.
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MAXQ7665/MAXQ7666 User’s Guide 8.1.1 Port Pins The MAXQ7665/MAXQ7666 port P0 pins are summarized in Table 8-1. Table 8-1. MAXQ7665/MAXQ7666 Port P0 Pins PIN NUMBER PORT P0 SIGNALS 48-PIN 56-PIN P0.0/TDO 32 37 Port 0 Data 0/JTAG Serial Test Data Output. P0.0 is a general-purpose digital I/O with interrupt/wakeup capability. TDO is the JTAG serial test data output. After power-up or a reset this pin defaults to JTAG TDO pin. P0.1/TMS 33 38 Port 0 Data 1/JTAG Test Mode Select. P0.
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MAXQ7665/MAXQ7666 User’s Guide 8.2.
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MAXQ7665/MAXQ7666 User’s Guide Bit 2: Bit 2 Edge Detect (IE2). This bit is set when a negative edge (IT2 = 1) or a positive edge (IT2 = 0) is detected on the interrupt 2 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set.
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MAXQ7665/MAXQ7666 User’s Guide 8.2.
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MAXQ7665/MAXQ7666 User’s Guide 8.2.5 Port 0 Direction Register (PD0) Register Description: Register Name: Register Address: Port 0 Direction Register PD0 Module 00h, Index 10h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name PD0.7 PD0.6 PD0.5 PD0.4 PD0.3 PD0.2 PD0.1 PD0.
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MAXQ7665/MAXQ7666 User’s Guide 8.2.
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MAXQ7665/MAXQ7666 User’s Guide 8.3 GPIO Operation From a software perspective, the MAXQ7665/MAXQ7666 port P0 appears as a group of peripheral registers with unique addresses and is addressed as a byte or 8 individual bit locations. The port is designed to provide programming flexibility for the user application. • All individual I/O bits are independently configured. • Any combination of input, output, or alternate function in a port is permitted.
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MAXQ7665/MAXQ7666 User’s Guide Table 8-3.
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MAXQ7665/MAXQ7666 User’s Guide 8.3.4 Port Pin Examples 8.3.4.1 Port Pin Example 1: Driving Outputs on Port 0 move PO0, #000h move PD0, #0FFh ; Set all outputs low ; Set all P0 pins to output mode 8.3.4.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 9: SERIAL PERIPHERAL INTERFACE (SPI) MODULE This section contains the following information: 9.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 9.1.1 SPI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 9.2 SPI Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 9-1. SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 Figure 9-2. SPI Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9 Figure 9-3. SPI Transfer Formats (CKPOL, CKPHA Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11 LIST OF TABLES Table 9-1. MAXQ7665/MAXQ7666 SPI Pins . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 9: SERIAL PERIPHERAL INTERFACE (SPI) MODULE The MAXQ7665/MAXQ7666 serial peripheral interface (SPI) module provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a 4-wire full-duplex serial bus that can be operated in either master mode or slave mode.
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MAXQ7665/MAXQ7666 User’s Guide 9.1.1 SPI Pins The SPI signals are shown in Table 9-1. Table 9-1. MAXQ7665/MAXQ7666 SPI Pins PIN NUMBER SPI EXTERNAL SIGNAL MASTER MODE USE 48 SLAVE MODE USE 56 MISO—Master In, Slave Out 35 Input to serial shift register. Output from serial shift register when selected. Data sent most significant bit first. MOSI—Master Out, Slave In 34 Output from serial shift register. Data sent most significant bit first. Input to serial shift register when selected.
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MAXQ7665/MAXQ7666 User’s Guide 9.2.2 SPI Control Register (SPICN) Register Description: Register Name: Register Address: SPI Control Register SPICN Module 01h, Index 07h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name STBY SPIC ROVR WCOL MODF MODFE MSTM SPIEN Reset 0 0 0 0 0 0 0 0 Access r rw rw rw rw rw rw rw r = read, w = write Bits 15 to 8: Reserved.
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MAXQ7665/MAXQ7666 User’s Guide Bit 3: Mode-Fault Flag (MODF). This bit is the mode-fault flag for SPI master mode operation. When mode fault detection is enabled (MODFE = 1) in master mode, detection of high-to-low transition on the SS pin signifies a mode fault causes MODF to be set to 1. This bit must be cleared to 0 by software once set. Setting this bit to logic 1 causes an interrupt if enabled. This flag has no meaning in slave mode. 0 = No mode fault has been detected.
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MAXQ7665/MAXQ7666 User’s Guide 9.2.3 SPI Configuration Register (SPICF) Register Description: Register Name: Register Address: SPI Configuration Register SPICF Module 01h, Index 08h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name ESPII — — — — CHR CKPHA CKPOL Reset 0 0 0 0 0 0 0 0 Access rw r r r r rw rw rw r = read, w = write Bits 15 to 8, 6 to 3: Reserved.
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MAXQ7665/MAXQ7666 User’s Guide 9.2.4 SPI Clock Register (SPICK) Register Description: Register Name: Register Address: SPI Clock Register SPICK Module 01h, Index 09h Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name CKR.7 CKR.6 CKR.5 CKR.4 CKR.3 CKR.2 CKR.1 CKR.0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Bits 15 to 8: Reserved.
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MAXQ7665/MAXQ7666 User’s Guide 9.3 SPI Operation The MAXQ7665/MAXQ7666 SPI can be viewed as a synchronous serial I/O port that shifts a data stream of 8 or 16 bits between peripheral devices. Data is shifted in and out of the SPI through the programmable shift registers that are formed by serially connecting the master’s shift register and a slave shift register. The SPI bus is typically implemented with one master device and multiple slave devices.
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MAXQ7665/MAXQ7666 User’s Guide 9.3.2 SPI Slave Operation The MAXQ7665/MAXQ7666 SPI module operates in slave mode when the MSTM bit is cleared to logic 0. In slave mode, the SPI module is dependent on the SCLK signal sourced from the master to control the data transfer. The SCLK input frequency should be no greater than the system clock of the MAXQ7665/MAXQ7666 slave device divided by 8. The slave select (SS) input must be externally asserted by a master before data exchange can take place.
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MAXQ7665/MAXQ7666 User’s Guide 9.3.3 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received over two serial data lines with respect to a single serial shift clock. The polarity and phase of the serial shift clock are the primary components in defining the SPI data transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and therefore also defines which clock edge is the active edge.
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MAXQ7665/MAXQ7666 User’s Guide 9.3.4 SPI Character Lengths To flexibly accommodate different SPI transfer data lengths, the character length for any transfer is user configurable through the character length bit (CHR) in the SPI configuration register. The CHR bit allows selection of either 8-bit or 16-bit transfers. When loading 8-bit characters into the SPIB data buffer, the byte for transmission should be right justified or placed in the least significant byte of the word.
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MAXQ7665/MAXQ7666 User’s Guide 9.5.2 Receive Overrun Since the receive direction of the MAXQ7665/MAXQ7666 SPI is double buffered, there is no overrun condition as long as the received character in the read buffer is read before the next character in the shift register is ready to be transferred to the read buffer.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 10: TEST ACCESS PORT (TAP) This section contains the following information: 10.1 TAP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2.1 TAP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 10-1. MAXQ7665/MAXQ7666 TAP and TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 Figure 10-2. TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 Figure 10-3. TAP Controller Debug Mode—IR-Scan Example . . . . . . . . . . . . . . . . . . . . . . . . . .10-9 Figure 10-4. TAP Controller Debug Mode—DR-Scan Example . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 10: TEST ACCESS PORT (TAP) 10.1 TAP Overview The MAXQ7665/MAXQ7666 incorporate a test access port (TAP) and TAP controller for communication with a host device across a 4-wire synchronous serial interface. The MAXQ7665/MAXQ7666 use the TAP to support in-system flash programming, in-circuit debug, and device test functions. The MAXQ7665/MAXQ7666 TAP features include the following: • 4-wire synchronous communication • TAP signals compatible with JTAG IEEE Standard 1149.
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MAXQ7665/MAXQ7666 User’s Guide 10.2.1 TAP Pins The TAP is formed by four interface signals as described in Table 10-1. The TAP signals are multiplexed with port pins P0.0, P0.1, P0.2, and P0.3. These pins default to their JTAG TAP function on reset, which means that the MAXQ7665/MAXQ7666 will always be ready for in-circuit debugging or in-circuit programming following any reset. Once an application has been loaded and starts running, the JTAG TAP port can still be used for in-circuit debugging operations.
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MAXQ7665/MAXQ7666 User’s Guide 10.3 TAP Interface Control Once an application has been loaded and starts running, the MAXQ7665/MAXQ7666 JTAG TAP interface can be controlled by the TAP bit in the system control register as described in Section 10.3.1. 10.3.
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MAXQ7665/MAXQ7666 User’s Guide 10.4 TAP Controller Operation The MAXQ7665/MAXQ7666 TAP controller is formed by a finite state machine that provides 16 operational states for access control. The TAP state control is achieved through host manipulation of the TMS and TCK signals. The TMS signal is sampled at the rising edge of TCK and decoded by the TAP controller to control movement between the TAP states. The TDI input and TDO output are meaningful once the TAP is in a serial shift state.
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MAXQ7665/MAXQ7666 User’s Guide 10.4.2 Run-Test-Idle As illustrated in Figure 10-2, the run-test-idle state is an intermediate state for getting to one of the two state sequences in which the TAP controller performs meaningful operations: • Controller state sequence (IR-scan) • Data register state sequence (DR-scan) 10.4.3 IR-Scan Sequence The MAXQ7665/MAXQ7666 support a 3-bit TAP instruction register to allow certain device specific instructions (e.g., "Debug" or "System Programming") to be supported.
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MAXQ7665/MAXQ7666 User’s Guide Table 10-3.
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MAXQ7665/MAXQ7666 User’s Guide 10.4.5.1 TAP Communication Examples IR-Scans and DR-Scans Figures 10-3 and 10-4 illustrate examples of communication between the host JTAG controller and the TAP of the MAXQ7665/ MAXQ7666. The host controls the TCK and TMS signals to move through the desired TAP states while accessing the selected shift register through the TDI input and TDO output pair.
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MAXQ7665/MAXQ7666 User’s Guide TCK TMS TEST-LOGIC-RESET SELECT-IR-SCAN SELECT-DR-SCAN RUN-TEST/IDLE UPDATE-DR EXIT1-DR SHIFT-DR EXIT2-DR PAUSE-DR EXIT1-DR SHIFT-DR CAPTURE-DR SELECT-DR-SCAN RUN-TEST/IDLE CONTROL STATE TDI SHIFT REGISTER PARALLEL OUTPUT DON'T CARE OR UNDEFINED DON'T CARE OR UNDEFINED NEW DATA OLD DATA INSTRUCTION REGISTER DATA REGISTER DON'T CARE OR UNDEFINED TDO ENABLE TDO Figure 10-4.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 11: IN-CIRCUIT DEBUG MODE This section contains the following information: 11.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 11.2 In-Circuit Debug Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 11.2.1 In-Circuit Debug Temporary 0 Register (ICDT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 11.2.
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MAXQ7665/MAXQ7666 User’s Guide LIST OF FIGURES Figure 11-1. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 LIST OF TABLES Table 11-1. Background Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11 Table 11-2. Background Mode Debug Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 Table 11-3. Output from DebugReadMap Command . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 11: IN-CIRCUIT DEBUG MODE The MAXQ7665/MAXQ7666 are equipped with embedded debug hardware and embedded ROM firmware developed for the purpose of providing in-circuit debugging capability to the user application. The in-circuit debug mode uses the JTAG-compatible TAP as its means of communication between the host and MAXQ7665/MAXQ7666 microcontrollers.
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MAXQ7665/MAXQ7666 User’s Guide The debug engine is supported by five functional registers: • ICDB: The ICDB register is an 8-bit data register that supports exchanging command/data between the host system and the incircuit debugger. The register functions as an 8-bit parallel buffer for the debug shift register in the TAP. The ICDB register is mapped to the peripheral register space and is read/write accessible by the CPU and the debug engine.
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MAXQ7665/MAXQ7666 User’s Guide 11.2.2 In-Circuit Debug Temporary 1 Register (ICDT1) The ICDT1 register is read/write accessible by the CPU only in background mode or debug mode. This register is intended for use by the utility ROM routines as temporary storage to save registers that might otherwise have to be placed in the stack. This register is cleared after a power-on reset or by a test-logic-reset TAP state.
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MAXQ7665/MAXQ7666 User’s Guide Bit 5: Break-On Register Enable (REGE). The REGE bit is used to enable the break-on register function. When the REGE bit is set to 1, BP4 and BP5 are used as register breakpoints. A break occurs when the content of BP4 is matched with the destination address of the current instruction. For BP5, a break occurs only on a selected data pattern for a selected destination register addressed by BP5. The data pattern is determined by the contents in the ICDA and ICDD register.
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MAXQ7665/MAXQ7666 User’s Guide 11.2.4 In-Circuit Debug Flag Register (ICDF) Register Description: Register Name: Register Address: In-Circuit Debug Flag Register ICDF Module 02h, Index 1Bh Bit # 7 6 5 4 3 2 1 0 Name — — — — PSS1 PSS0 SPE TXC Reset 0 0 0 0 0 0 0 0 Access r r r r rw rw rw rw r = read, w = write Bits 7 to 4: Reserved. Read 0, write ignored. Bits 3 and 2: Programming Source Select Bits 1 and 0 (PSS1 and PSS0). See Section 12 for information on these bits.
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MAXQ7665/MAXQ7666 User’s Guide 11.2.6 In-Circuit Debug Address Register (ICDA) The debug engine uses the ICDA register to store addresses so that ROM code may view that information. This register is also used by the debug engine as a mask register to mask out don’t care bits in the ICDD register when BP5 is used as a register breakpoint.
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MAXQ7665/MAXQ7666 User’s Guide 11.2.8 System Control Register (SC) Register Description: Register Name: Register Address: Bit # System Control Register SC Module 08h, Index 08h 7 6 5 4 3 2 1 0 Name TAP — CDA1 CDA0 UPA ROD PWL — Reset 1 0 0 0 0 0 1* 0 Access rw r rw rw rw rw rw r r = read, w = write *This register defaults to 80h on all forms of reset except after power-on reset. After power-on reset, the PWL bit is also set and this register defaults to 82h.
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MAXQ7665/MAXQ7666 User’s Guide 11.3 Debug Engine Operation To enable a communication link between the host and the MAXQ7665/MAXQ7666 debug engine, the debug instruction (010b) must be loaded into the TAP instruction register using the IR-scan sequence. Once the instruction is latched in the instruction parallel buffer (IR2:IR0) and is recognized by the TAP controller in the update-IR state, the 10-bit data shift register is activated as the communication channel for DR-scan sequences.
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MAXQ7665/MAXQ7666 User’s Guide Table 11-1 shows the background mode commands supported by the MAXQ7665/MAXQ7666. Encodings not listed in this table are not supported in background mode and are treated as no operations. A command can consist of multiple-byte transactions between the external host and the debug engine via the TAP. However, a command code is always 8 bits and is always transmitted first, followed by address and/or data when needed. Table 11-1.
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MAXQ7665/MAXQ7666 User’s Guide 11.3.2 Breakpoint Registers The MAXQ7665/MAXQ7666 incorporate six host-configurable breakpoint registers (BP0–BP5) for establishing different types of breakpoint mechanisms. The first four breakpoint registers (BP0–BP3) are 16-bit registers that are configurable as program memory address breakpoints. When enabled, the debug engine forces a break when a match between the breakpoint register and the program memory execution address occurs.
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MAXQ7665/MAXQ7666 User’s Guide 11.3.2.2 Breakpoint Register 4 (BP4) Register Description: Register Name: Breakpoint Register 4 BP4 This register is accessible only via background mode read/write commands. When (REGE = 0): This register serves as one of the two data memory address breakpoints. When DME is set in background mode, the debug engine monitors the data memory address bus activity while the CPU is executing the user program.
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MAXQ7665/MAXQ7666 User’s Guide 11.3.2.3 Breakpoint Register 5 (BP5) This register is accessible only through background mode read/write commands. When (REGE = 0): This register serves as one of the two data memory address breakpoints. When DME is set in background mode, the debug engine monitors the data memory address bus activity while the CPU is executing the user program. If an address match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
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MAXQ7665/MAXQ7666 User’s Guide 11.3.4 Debug Mode There are two ways to enter debug mode from background mode: 1) issuance of the debug command directly by the host through the TAP communication port, or 2) the breakpoint matching mechanism. The host can issue the debug background command to the debug engine. This direct debug mode entry is unstable. The response time varies dependent on system conditions when the command is issued.
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MAXQ7665/MAXQ7666 User’s Guide Internally, the ROM can ascertain when new data is available or when it can output the next data byte via the TXC flag. The TXC flag is an important indicator between the debug engine and the utility ROM debug routines. The utility ROM firmware sets the TXC flag to 1 to indicate that valid data has been loaded to the ICDB register.
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MAXQ7665/MAXQ7666 User’s Guide 11.3.6 Read-Register Map Command Host-ROM Instruction A read-register map command reads out data contents for all implemented system and peripheral registers. The host does not specify a target register but instead should expect register data output in successive order, starting with the lowest order register in register module 0. Data is loaded by the ROM to the 8-bit ICDB register and is output one byte per transfer cycle.
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MAXQ7665/MAXQ7666 User’s Guide 11.3.9 Debug Mode Special Considerations The following are special considerations when using debug mode. The debug engine cannot be operated reliably when the CPU is configured in the power management mode (divide-by-256 system clock mode). To allow for proper execution of debug mode commands when invoked during PMM, the switchback enable (SWB) bit should be configured to logic 1.
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MAXQ7665/MAXQ7666 User’s Guide 11.3.10.3 Data Memory Write Command When invoking this command, ICDA should be set to the word address of the location to write to, and ICDD should be set to the data word to write. The input address must be based on the utility ROM memory map, as shown in Section 1. 11.3.10.4 Program Stack Read Command When invoking this command, ICDA should be set to the address of the starting stack location (value of SP) to read from, and ICDD should be set to the number of words.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 12: IN-SYSTEM PROGRAMMING This section contains the following information: 12.1 Bootstrap-Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2 12.2 In-System Programming Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3 12.2.1 In-Circuit Debug Flag Register (ICDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3 12.2.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 12: IN-SYSTEM PROGRAMMING The MAXQ7665/MAXQ7666 are equipped with a bootstrap loader as part of the utility ROM firmware. The main function of the bootstrap loader is to provide in-system programming capability to the user application.
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MAXQ7665/MAXQ7666 User’s Guide 12.2 In-System Programming Peripheral Registers The MAXQ7665/MAXQ7666 in-system programming peripheral registers are described here. All the in-system programming peripheral registers are directly accessible by the microcontroller through the module/index address. 12.2.
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MAXQ7665/MAXQ7666 User’s Guide 12.2.2 System Control Register (SC) Register Description: Register Name: Register Address: System Control Register SC Module 08h, Index 08h Bit # 7 6 5 4 3 2 1 0 Name TAP — CDA1 CDA0 UPA ROD PWL — Reset 1 0 0 0 0 0 1* 0 Access rw r rw rw rw rw rw r r = read, w = write *This register defaults to 80h on all forms of reset except after power-on reset. After power-on resert, the PWL bit is also set and this register defaults to 82h.
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MAXQ7665/MAXQ7666 User’s Guide 12.3 JTAG Bootloader Operation The MAXQ7665/MAXQ7666 JTAG bootloader uses the same status bit handshaking hardware as is used for in-circuit debugging. When the SPE bit of the system programming buffer (SPB) is set to 1 and JTAG is selected as the programming source (PSS1:PSS0 = 00b), the background and active-debug-mode state machines are disabled.
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MAXQ7665/MAXQ7666 User’s Guide 12.4.1 Entering a Password A password can be entered via the TAP interface directly by issuing the unlock-password debug-mode command. The unlock-password command requires 32 follow-on transfer cycles, each containing a byte value to be compared with the program memory password. 12.5 JTAG Bootloader Protocol When communicating with the bootloader using the JTAG interface, the clock rate (TCK) must be kept below 1/8 the system clock rate.
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MAXQ7665/MAXQ7666 User’s Guide All commands in Family 0 can be executed without first matching the password. All other commands (in Families 1x through Fx) are password protected; the password must first be matched before these commands can be executed. A special case exists when the program memory has not been initialized (following master erase).
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MAXQ7665/MAXQ7666 User’s Guide Table 12-4. Bootloader Status Flags FLAG BIT FUNCTION 0 Password Lock 0 = The password is unlocked or had a default value; password-protected commands can be used. 1 = The password is locked. Password-protected commands cannot be used. 1 Word/Byte Mode 0 = The bootloader is currently in byte mode for memory reads/writes. 1 = The bootloader is currently in word mode for memory reads/writes. 2 Word/Byte Mode Supported 0 = The bootloader supports byte mode only.
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MAXQ7665/MAXQ7666 User’s Guide Command 09h—Get Utility ROM Version I/O Byte 1 Input 09h Output VersionL Byte 2 VersionH Command 0Ah—Set Word/Byte Mode Access The Mode byte should be 0 to set byte access mode or 1 to set word access mode. The current access mode is returned in the status flag byte by command 04h, as well as a flag to indicate whether word access mode is supported by this particular bootloader.
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MAXQ7665/MAXQ7666 User’s Guide 12.5.3 Family 2 Commands: Dump Variable Length (Password Protected) Command 20h—Dump Code Variable Length This command has a slightly different format depending on the length of the dump requested. It returns the contents of the application flash/ROM—(LengthL) or (LengthH:LengthL) bytes/words starting at (AddressH:AddressL).
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MAXQ7665/MAXQ7666 User’s Guide 12.5.5 Family 4 Commands: Verify Variable Length (Password Protected) Command 40h—Verify Code Variable Length This command operates in the same manner as the “Load Code Variable Length” command, except that instead of programming the input data into code flash, it verifies that the input data matches the data already in code space. If the data does not match, the status code is set to reflect this failure.
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MAXQ7665/MAXQ7666 User’s Guide 12.5.8 Family 9 Commands: Load Fixed Length (Password Protected) Command 90h—Load Code Fixed Length This command loads a block of 128 bytes into the program memory (SRAM) starting at the specified address. The address is rounded down to the nearest block boundary (multiple of 64) before the data is loaded.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 13: HARDWARE MULTIPLIER MODULE This section contains the following information: 13.1 Hardware Multiplier Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2 13.2 Hardware Multiplier Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.2.1 Hardware Multiplier Control Register (MCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.2.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 13: HARDWARE MULTIPLIER MODULE The MAXQ7665/MAXQ7666 microcontrollers include a hardware multiplier module to support high-speed multiplications. The hardware multiplier module is equipped with two 16-bit operand registers, a 32-bit read-only result register, and an accumulator of 48-bit width. The multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle.
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MAXQ7665/MAXQ7666 User’s Guide 13.2 Hardware Multiplier Peripheral Registers 13.2.
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MAXQ7665/MAXQ7666 User’s Guide Bit 3: Operand Count Select (OPCS). This bit defines how many operands must be loaded to trigger a multiply or multiply-accumulate/subtract operation (except when SQU = 1 since this implicitly specifies a single operand). When this bit is cleared to logic 0, both operands (MA and MB) must be written to trigger the operation. When this bit is set to 1, the specified operation is triggered once either operand is written.
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MAXQ7665/MAXQ7666 User’s Guide 13.2.3 Multiplier Operand B Register (MB) Register Description: Register Name: Register Address: Bit # Multiplier Operand B Register MB Module 001, Index 02h 15 14 13 12 11 10 9 8 Name MB.15 MB.14 MB.13 MB.12 MB.11 MB.10 MB.9 MB.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name MB.7 MB.6 MB.5 MB.4 MB.3 MB.2 MB.1 MB.
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MAXQ7665/MAXQ7666 User’s Guide 13.2.5 Multiplier Accumulator 1 Register (MC1) Register Description: Register Name: Register Address: Bit # Multiplier Accumulator 1 Register MC1 Module 001, Index 04h 15 14 13 12 11 10 9 8 Name MC1.15 MC1.14 MC1.13 MC1.12 MC1.11 MC1.10 MC1.9 MC1.8 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw Bit # 7 6 5 4 3 2 1 0 Name MC1.7 MC1.6 MC1.5 MC1.4 MC1.3 MC1.2 MC1.1 MC1.
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MAXQ7665/MAXQ7666 User’s Guide 13.2.7 Multiplier Read Register 1 (MC1R) Register Description: Register Name: Register Address: Bit # Multiplier Read Register 1 MC1R Module 001, Index 0Ch 15 14 13 12 11 10 9 8 Name MC1R.15 MC1R.14 MC1R.13 MC1R.12 MC1R.11 MC1R.10 MC1R.9 MC1R.8 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name MC1R.7 MC1R.6 MC1R.5 MC1R.4 MC1R.3 MC1R.2 MC1R.1 MC1R.
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MAXQ7665/MAXQ7666 User’s Guide 13.3 Hardware Multiplier Controls The selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register: SUS, MSUB, MMAC, and SQU. The number of operands that must be loaded to trigger the specified operation is dictated by the OPCS bit setting, except when the square function is enabled (SQU = 1).
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MAXQ7665/MAXQ7666 User’s Guide 13.8 Accessing the Multiplier There are no restrictions on how quickly data is entered into the operand registers or on the order of data entry. The only requirement to do a calculation is to perform the loading of MA and/or MB registers having specified data type and operation in the MCNT register. The multiplier keeps track of the writes to the MA and MB registers, and starts calculation immediately after the prescribed number of operands is loaded.
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MAXQ7665/MAXQ7666 User’s Guide 13.9 MAXQ7665/MAXQ7666 Hardware Multiplier Examples The following are code examples of multiplier operations.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 14: MAXQ7665/MAXQ7666 INSTRUCTION SET SUMMARY This section contains the following information: ADD/ADDC src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-5 AND src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-6 AND Acc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-23 RET C/RET NC, RETI Z/RETI NZ, RETI S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-23 RL/RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-25 RR/RRC . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 14: MAXQ7665/MAXQ7666 INSTRUCTION SET SUMMARY Table 14-1. MAXQ7665/MAXQ7666 Instruction Set Summary MATH BIT OPERATIONS LOGICAL OPERATIONS MNEMONIC 14-3 AND src OR src XOR src CPL NEG SLA SLA2 SLA4 RL RLC SRA SRA2 SRA4 SR RR RRC MOVE C, Acc. MOVE C, #0 MOVE C, #1 CPL C MOVE Acc., C AND Acc. OR Acc. XOR Acc. MOVE dst., #1 MOVE dst., #0 MOVE C, src.
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MAXQ7665/MAXQ7666 User’s Guide Table 14-1.
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MAXQ7665/MAXQ7666 User’s Guide ADD/ADDC src Add/Add with Carry Description: The ADD instruction sums the active accumulator (Acc or A[AP]) and the specified src data and stores the result back to the active accumulator. The ADDC instruction additionally includes the Carry (C) Status Flag in the summation. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7665/MAXQ7666 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ7665/MAXQ7666 User’s Guide AND src Logical AND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7665/MAXQ7666 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ7665/MAXQ7666 User’s Guide {L/S}CALL src {Long/Short} Call to Subroutine Description: Performs a call to the subroutine destination specified by src. The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words). The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute long CALL.
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MAXQ7665/MAXQ7666 User’s Guide CMP src Compare Accumulator Description: Compare for equality between the active accumulator and the least significant byte of the specified src. The MAXQ7665/MAXQ7666 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ7665/MAXQ7666 User’s Guide CPL C Complement Carry Flag Description: Logically complements the Carry (C) Flag. Status Flags: C Operation: C ← ~C Encoding: 15 1101 0 1010 0010 1010 ;C=0 Example(s): ;C←1 CPL C {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Description: The DJNZ LC[n], src instruction performs a conditional branch based upon the associated Loop Counter (LC[n]) register.
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MAXQ7665/MAXQ7666 User’s Guide {L/S}JUMP src Unconditional {Long/Short} Jump Description: Performs an unconditional jump as determined by the src specifier. The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words). The JUMP instruction uses a 16-bit immediate src to perform an absolute JUMP to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute JUMP. Using the optional 'L' prefix (i.e.
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MAXQ7665/MAXQ7666 User’s Guide {L/S}JUMP C/{L/S}JUMP NC, src L/S}JUMP Z/{L/S}JUMP NZ, src {{L/S}JUMP E/{L/S}JUMP NE, src {L/S}JUMP S, src Conditional {Long/Short} Jump on Status Flag Description: Performs conditional branching based upon the state of a specific processor status flag. JUMP C results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear. JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear.
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MAXQ7665/MAXQ7666 User’s Guide JUMP NZ Z=0: IP ← IP + src (relative) -or- src (absolute) Operation: Z=1: IP ← IP + 1 Encoding: 15 f101 0 1100 ssss ssss Example(s): JUMP NZ, label1 JUMP E E=1: IP ← IP + src (relative) -or- src (absolute) Operation: E=0: IP ← IP + 1 Encoding: 15 0011 ; Z=1, branch taken 0 1100 ssss ssss Example(s): JUMP E, label1 ; E=1, branch taken Special Notes: The src specifier must be immediate data.
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MAXQ7665/MAXQ7666 User’s Guide MOVE dst, src Move Data Description: Moves data from a specified source (src) to a specified destination (dst). A list of defined source, destination specifiers is given in the table below. Also, since src can be either 8-bit (byte) or 16-bit (word) data, the rules governing data transfer are also explained below in the encoding section.
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MAXQ7665/MAXQ7666 User’s Guide MOVE dst, src Move Data Table 14-3. Destination Specifier Codes dst dst BIT ENCODING (ddd dddd) WIDTH (16 OR 8) NUL 111 0110 8/16 Null (Virtual) Destination. Intended as a bit bucket to assist software with pointer increments/decrements. MN[n] nnn 0NNN 8/16 nnnn Selects One of First 8 Registers in Module NNN; where NNN= 0 to 5. Access to Next 24 Using PFX[n].
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MAXQ7665/MAXQ7666 User’s Guide Example(s): MOVE A[0], A[3] ; A[0] ← A[3] MOVE DP[0], #110h ; DP[0] ← #0110h (PFX[0] register used) ; MOVE PFX[0], #01h (smart-prefixing) ; MOVE DP[0], #10h MOVE DP[0], #80h Special Notes: ; DP[0] ← #0080h (PFX[0] register not needed) Proper loading of the PFX[n] registers, when for the purpose of supplying 16-bit immediate data or accessing 2-cycle destinations, is handled automatically by the assembler and is therefore an optional step for the user when writing assem
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MAXQ7665/MAXQ7666 User’s Guide MOVE C, Acc. Move Accumulator Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified active accumulator bit. Status Flags: C Operation: C ← Acc. Encoding: 15 1110 0 1010 bbbb 1010 ; Acc = 01C0h, C=0 Example(s): MOVE C, Acc.8 ; C =1 MOVE C, src. Move Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified source bit src.. Status Flags: C Operation: C ← src.
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MAXQ7665/MAXQ7666 User’s Guide MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag. Status Flag: C←1 Operation: C←1 Encoding: 15 1101 0 1010 0001 1010 ;C=0 Example(s): ;C←1 MOVE C, #1 MOVE dst., #0 Clear Bit Description: Clears the bit specified by dst.. Status Flags: C, E (if dst is PSF), S, Z Operation: dst. ← 0 Encoding: 15 1ddd 0 dddd 0bbb ; M0[0] = FEh Example(s): Special Notes: 0111 MOVE M0[0].1, #0 ; M0[0] = FCh MOVE M0[0].
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MAXQ7665/MAXQ7666 User’s Guide NEG Negate Accumulator Description: Performs a negation (2's complement) of the active accumulator and returns the result back to the active accumulator. Status Flags: S, Z Operation: Acc ← ~Acc + 1 Encoding: 15 1000 0 1010 1001 1010 ; Acc = FEEDh, S=1, Z=0 Example(s): NEG ; Acc = 0113h, S=0, Z=0 OR src Logical OR Description: Performs a logical-OR between the active accumulator (Acc or A[AP]) and the specified src data.
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MAXQ7665/MAXQ7666 User’s Guide OR Acc. Logical OR Carry Flag with Accumulator Bit Description: Performs a logical-OR between the Carry (C) status flag and a specified bit of the active accumulator (Acc.) and returns the result to the Carry. Status Flags: C Operation: C ← C OR Acc. Encoding: 15 1010 0 1010 bbbb 1010 ; Acc = 2345h, C=0 at start Example(s): OR Acc.1 ; Acc.1=0 → C=0 OR Acc.2 ; Acc.
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MAXQ7665/MAXQ7666 User’s Guide POPI dst Pop Word from the Stack Enable Interrupts Description: Pops a single word from the stack (@SP) to the specified dst and decrements the stack pointer (SP). Additionally, POPI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
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MAXQ7665/MAXQ7666 User’s Guide RET Return from Subroutine Description: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). The decremented SP is saved as the new stack pointer (SP).
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MAXQ7665/MAXQ7666 User’s Guide RET NC Operation: C=0: IP ← @SP-C=1: IP ← IP +1 Encoding: 15 1110 Example(s): 0 1100 0000 RET NC 1101 ; C=1, return (RET) does not occur RET Z Operation: Z=1: IP ← @SP-Z=0: IP ← IP + 1 Encoding: 15 1001 Example(s): 0 1100 0000 RET Z 1101 ; Z=0, return (RET) does not occur RET NZ Operation: Z=0: IP ← @SP-Z=1: IP ← IP +1 Encoding: 15 1101 Example(s): 0 1100 0000 RET NZ 1101 ; Z=0, return (RET) is performed RET S Operation: S=1: IP ← @SP-- Encodin
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MAXQ7665/MAXQ7666 User’s Guide RETI Return from Interrupt Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). Additionally, RETI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
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MAXQ7665/MAXQ7666 User’s Guide RETI Z Operation: Z=1: IP ← @SP-INS ← 0 Z=0: IP ← IP + 1 Encoding: 15 1001 Example(s): 0 1100 1000 RETI Z 1101 ; Z=0, return from interrupt (RETI) does not occur RETI NZ Operation: Z=0: IP ← @SP-INS ← 0 Z=1: IP ← IP +1 Encoding: 15 1101 Example(s): 0 1100 1000 RETI NZ 1101 ; Z=0, return from interrupt (RETI) is performed RETI S Operation: S=1: IP ← @SP-INS ← 0 S=0: IP ← IP + 1 Encoding: 15 1100 Example(s): Maxim Integrated RETI S 0 1100 1000 1101
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MAXQ7665/MAXQ7666 User’s Guide RL/RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msb of the accumulator (bit 15) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 15 Active Accumulator (Acc) 0 Acc.[15:1]← Acc.[14:0]; Acc.0 ← Acc.
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MAXQ7665/MAXQ7666 User’s Guide RR/RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsb of the accumulator (bit 0) back to the msb (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: 15 Active Accumulator (Acc) 0 Acc.[14:0]← Acc.[15:1]; Acc.15 ← Acc.
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MAXQ7665/MAXQ7666 User’s Guide SLA/SLA2/SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iteration, a 0 is shifted into the lsb, and the msb is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
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MAXQ7665/MAXQ7666 User’s Guide SR/SRA/SRA2/SRA4 Shift Accumulator Right/ Shift Accumulator Right Arithmetically One, Two, or Four Times Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times, respectively, for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msb while the SRA, SRA2, and SRA4 instructions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation.
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MAXQ7665/MAXQ7666 User’s Guide 15 SRA2 Operation: Active Accumulator (Acc) 0 Carry Flag 0 Carry Flag Acc.[13:0] ← Acc.[15:2] Acc.[15:14] ← Acc.15 C ← Acc.1 Encoding: 15 1000 0 1010 1110 1010 ; Acc = 0003h, C=0, Z=0 Example(s): SRA2 ; Acc = 0000h, C=1, Z=1 15 SRA4 Operation: Active Accumulator (Acc) Acc.[11:0] ← Acc.[15:4] Acc.[15:12] ← Acc.15 C ← Acc.
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MAXQ7665/MAXQ7666 User’s Guide SUB/SUBB src Subtract /Subtract with Borrow Description: Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumulator. The SUBB additionally subtracts the borrow (Carry Flag), which may have resulted from previous subtraction. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7665/MAXQ7666 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ7665/MAXQ7666 User’s Guide XCH Description: Exchange Accumulator Bytes Exchanges the upper and lower bytes of the active accumulator. Status Flags: S Operation: Acc.[15:8] ← Acc.[7:0] Acc.[7:0] ← Acc.[15:8] Encoding: 15 1000 0 1010 1000 1010 ; Acc = 2345h Example(s): XCHN ; Acc = 4523h XCHN Exchange Accumulator Nibbles Description: Exchanges the upper and lower nibbles in the active accumulator byte(s). Status Flags: S Operation: Acc.[7:4] ← Acc.[3:0] Acc.[3:0] ← Acc.[7:4] Acc.
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MAXQ7665/MAXQ7666 User’s Guide XOR src Logical XOR Description: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7665/MAXQ7666 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 15: UTILITY ROM (SPECIFIC TO MAXQ7665A–MAXQ7665D WITH TYPE A FLASH) This section contains the following information: 15.1 In-Application Programming Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-3 15.2 Data Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-3 15.3 Temperature Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 15: UTILITY ROM (SPECIFIC TO MAXQ7665A–MAXQ7665D WITH TYPE A FLASH) The MAXQ7665 utility ROM includes routines that provide the following functions to application software: • In-application programming routines for Type A flash memory (program, erase, mass erase) • Single word/byte copy and buffer copy routines for use with lookup tables • Temperature conversion routine to perform internal/remote diode-connected transistor based temperature measurement The MAXQ7665 fl
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MAXQ7665/MAXQ7666 User’s Guide 15.1 In-Application Programming Functions Function: Summary: Inputs: Outputs: Destroys: flashEraseSector Erases (programs to FFFFh) a sector of flash memory. A[0]: Word address located in the sector to be erased. Carry: Set on error and cleared on success. If set, then A[0] contains one of the following error codes: 1: Failure due to software timeout. 2: Failure reported by hardware (FERR). 3: Failure due to trying to erase current page.
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MAXQ7665/MAXQ7666 User’s Guide Function: Summary: Inputs: Outputs: Destroys: moveDP0inc Reads the byte/word value pointed to by DP[0], then increments DP[0]. DP[0]: Address to read from. GR: Data byte/word read. DP[0] is incremented. Selects DP[0] in DPC. Notes: 1) Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as explained in Section 1.
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MAXQ7665/MAXQ7666 User’s Guide Function: Summary: Inputs: Outputs: Destroys: moveDP1dec Reads the byte/word value pointed to by DP[1], then decrements DP[1]. DP[1]: Address to read from. GR: Data byte/word read. DP[1] is decremented. Selects DP[1] in DPC. Notes: 1) Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as explained in Section 1.
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MAXQ7665/MAXQ7666 User’s Guide Function: Summary: Inputs: Outputs: Destroys: copyBuffer Copies LC[0] bytes/words from DP[0] to BP[OFFS]. DP[0]: Address to copy from. BP[OFFS]: Address to copy to. LC[0]: Number of bytes or words to copy. OFFS is incremented by LC[0]. DP[0] is incremented by LC[0]. LC[0] Notes: 1) Before calling this function, DPC should be set appropriately to configure DP[0] and BP[OFFS] for byte or word mode.
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MAXQ7665/MAXQ7666 User’s Guide 15.4 ROM Example 1: Calling A MAXQ7665 Utility ROM Function Directly This example shows the direct addressing method for calling MAXQ7665 utility functions, using the function moveDP1inc to read a static string from code space. Note the equate UROM_MOVEDP1INC. UROM_MOVEDP1INC EQU 08877h Text: DB “Hello World!”,0 ; Define a string in code space.
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MAXQ7665/MAXQ7666 User’s Guide 15.5 ROM Example 2: Calling A MAXQ7665 Utility ROM Function Indirectly The second example shows the indirect addressing method (lookup table) for calling MAXQ7665 utility functions. We use the same function (UROM_MoveDP1Inc) to read our static string, but this time we must figure out the address we want dynamically. Note the inserted code where we before had a direct call to the function. Also note that the function index of moveDP1inc is 7.
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MAXQ7665/MAXQ7666 User’s Guide SECTION 16: UTILITY ROM (SPECIFIC TO MAXQ7666 WITH TYPE F FLASH) This section contains the following information: 16.1 In-Application Programming Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3 16.2 Data Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-6 16.3 Temperature Conversion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXQ7665/MAXQ7666 User’s Guide SECTION 16: UTILITY ROM (SPECIFIC TO MAXQ7666 WITH TYPE F FLASH) The MAXQ7666 utility ROM includes routines that provide the following functions to application software: • In-application programming routines for Type F flash memory (program, erase, mass erase) • Single word/byte copy and buffer copy routines for use with lookup tables • Temperature conversion routine to perform internal/remote diode-connected transistor based temperature measurement The MAXQ7666 flash type is
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MAXQ7665/MAXQ7666 User’s Guide Table 16-1. Utility ROM User Functions (for Utility ROM Version 1.01) (continued) FUNCTION NUMBER FUNCTION NAME ENTRY POINT SUMMARY 16 dataFlashWrite 08906h Writes a word to the data flash memory. 17 dataFlashWriteEven 08920h Writes a word to the data flash memory even address. 18 dataFlashErasePage 08929h 19 — — 20 dataFlashEraseAll 08937h Erases the entire data flash. 21 dataFlashReadEven 0893Eh Reads a word from the data flash memory even address.
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MAXQ7665/MAXQ7666 User’s Guide Function: Summary: Inputs: Outputs: Destroys: programFlashEraseAll Erases (programs to FFFFh) all locations in program flash memory. None. Carry: Set on error and cleared on success. PSF, GR, LC[0], LC[1], APC, AP, A[0] (AP, APC set to 0) Notes: 1) If the watchdog reset is enabled, user code should disable it before calling this function. Also, disable interrupts globally (IGE = 0). 2) This function can only be called by code running from the RAM.
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MAXQ7665/MAXQ7666 User’s Guide Function: Summary: Inputs: Outputs: Destroys: dataFlashErasePage Erases (programs to FFFFh) two pages (1 page = 1 word) of the data flash memory. A[0]: Word address located in the page to be erased. The specified even page and the next sequential odd page will be erased. Carry: Set on error and cleared on success. If set, then A[0] contains one of the following error codes: 1. Failure due to software timeout. 2. Failure reported by hardware (FERR). 3.
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MAXQ7665/MAXQ7666 User’s Guide 16.2 Data Transfer Functions Function: Summary: Inputs: Outputs: Destroys: moveDP0 Reads the byte/word value pointed to by DP[0]. DP[0]: Address to read from. GR: Data byte/word read. Selects DP[0] in DPC. Notes: 1) Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as explained in Section 1.
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MAXQ7665/MAXQ7666 User’s Guide Function: Summary: Inputs: Outputs: Destroys: moveDP1inc Reads the byte/word value pointed to by DP[1], then increments DP[1]. DP[1]: Address to read from. GR: Data byte/word read. DP[1] is incremented. Selects DP[1] in DPC. Notes: 1) Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as explained in Section 1.
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MAXQ7665/MAXQ7666 User’s Guide Function: Summary: Inputs: Outputs: Destroys: moveFPdec Reads the byte/word value pointed to by BP[OFFS] then decrements OFFS. BP[OFFS]: Address to read from. GR: Data byte/word read. OFFS is decremented. Selects BP in DPC. Notes: 1) Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as explained in Section 1.
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MAXQ7665/MAXQ7666 User’s Guide REVISION HISTORY REVISION NUMBER REVISION DATE 0 12/07 DESCRIPTION Initial release. PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed.