Rev 0; 4/09 MAXQ7667 USER’S GUIDE BURST ENABLE BURST BURST OUTPUT, DUTY CYCLE, AND PULSE COUNTER 0.47µF 0.47µF REFBG REFSAR 0.47µF REFECHO AIN0 AIN1 AVDD AIN2 AIN3 THERMISTOR AIN4 AIN5 VOLTAGE REFERENCE SIGMA-DELTA ADC -1 2mV 0mV AVDD/2 MUX 120kΩ BATTERY+ 0.01µF 3kΩ ECHON DIGITAL BANDPASS FILTER SIGMA-DELTA ADC 470pF AVDD/2 0.01µF LNA DIGITAL LOWPASS FILTER FULL WAVE DETECTOR 3kΩ ECHOP 16-BIT 16-MIPS MICROCONTROLLER 470pF 120kΩ FIFO THRESHOLD ADJUST GATE5 BSP129 +5.
MAXQ7667 User’s Guide TABLE OF CONTENTS SECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 SECTION 2: Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 SECTION 3: Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 SECTION 4: Register Descriptions . . . . . .
MAXQ7667 User’s Guide SECTION 1: OVERVIEW The MAXQ7667 is a smart data-acquisition system based on the MAXQ® microcontroller (µC) with integrated peripheral functions for ultrasonic, time-of-flight, distance measurement. The MAXQ processor is a high-performance reduced instruction set computing (RISC) core µC designed for efficient peripheral multitasking applications.
MAXQ7667 User’s Guide • One Schedule Timer • Three General-Purpose Timers • LIN-Compatible UART • SPI Port • JTAG Port • Watchdog Timer • Voltage Monitors MAXQ7667 Module Functions CORE MODULES PERIPHERAL MODULES MEMORY MODULE APPLICATION-SPECIFIC PERIPHERALS UTILITY ROM MAXQ7667 16-BIT HARVARD MAXQ RISC CPU DATA RAM 4KB (2KWORD) • 16 ALU REGISTERS • MMU • HW MULTPLY/ACCUM FLASH ROM 32KB (16KWORD) • INTERRUPT CONTROL • VARIABLE GAIN LNA • 16-BIT SIGMA-DELTA ADC • DIGITAL BANDPASS FILTER • DIGITAL L
MAXQ7667 User’s Guide Typical Application Circuit BURST ENABLE BURST BURST OUTPUT, DUTY CYCLE, AND PULSE COUNTER 0.47µF 0.47µF REFBG REFSAR 0.47µF REFECHO AIN0 AIN1 AVDD AIN2 AIN3 THERMISTOR AIN4 AIN5 VOLTAGE REFERENCE SIGMA-DELTA ADC -1 2mV 0mV AVDD/2 MUX 120kΩ BATTERY+ 0.01µF 3kΩ ECHON DIGITAL BANDPASS FILTER SIGMA-DELTA ADC 470pF AVDD/2 0.
MAXQ7667 User’s Guide SECTION 2: ARCHITECTURE This section contains the following information: 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 2.1.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 2.1.2 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide LIST OF FIGURES Figure 2-1. MAXQ7667 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Figure 2-2. MAXQ7667 Transport-Triggered Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 Figure 2-3. Instruction Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 Figure 2-4. Pseudo-Von Neumann Memory Map (MAXQ7667 Default) . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 2: ARCHITECTURE 2.1 Overview The MAXQ7667 is a low-power, high-performance, 16-bit RISC microcontroller based on the MAXQ architecture. It includes support for integrated, in-system-programmable flash memory and a wide range of peripherals supporting ultrasonic measurement, schedule timer, general-purpose timer/counters, GPIO, SPI, JTAG port, LIN-capable UART, 12-bit SAR ADC with five input channels, and a voltage reference.
MAXQ7667 User’s Guide CORE MODULES PERIPHERAL MODULES MEMORY MODULE APPLICATION-SPECIFIC PERIPHERALS UTILITY ROM MAXQ7667 16-BIT HARVARD MAXQ RISC CPU DATA RAM 4KB (2KWORD) • 16 ALU REGISTERS • MMU • HW MULTPLY/ACCUM FLASH ROM 32KB (16KWORD) • INTERRUPT CONTROL • VARIABLE GAIN LNA • 16-BIT SIGMA-DELTA ADC • DIGITAL BANDPASS FILTER • DIGITAL LOWPASS FILTER • LP FILTER FIFO • PLL FREQUENCY GENERATOR • BURST GENERATOR • 16-WORD HW STACK • HARVARD ARCHITECTURE GENERAL-PURPOSE PERIPHERALS • 3 16-BIT TIM
MAXQ7667 User’s Guide 2.1.3 Harvard Memory Architecture As part of the MAXQ family, the MAXQ7667 core architecture is based on the MAXQ20 design, which implements a 16-bit internal databus and ALU. Program memory, data memory, and register space on the MAXQ7667 follow the Harvard architecture model. Each type of memory is kept separate and is accessed by a separate bus, allowing different word lengths for different types of memory. Registers may be either 8 or 16 bits in width.
MAXQ7667 User’s Guide 2.2 Architecture The MAXQ7667 architecture is designed to be modular and expandable. Top-level instruction decoding is extremely simple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the system register and peripheral register groups. Figure 2-2 illustrates the modular architecture.
MAXQ7667 User’s Guide Memory access from the MAXQ7667 is based on a Harvard architecture with separate address spaces for program and data memory. The simple instruction set and transport-triggered architecture allow the MAXQ7667 to run in a nonpipelined execution mode where each instruction can be fetched from memory, decoded, and executed in a single clock cycle. Data memory is accessed through one of three data pointer registers.
MAXQ7667 User’s Guide 2.2.2 Register Space The MAXQ7667 architecture provides a total of 16 register modules. Each of these modules contains 32 registers. Of these possible 16 register modules, only 13 are used on the MAXQ7667—seven for system registers and six for peripheral registers.
MAXQ7667 User’s Guide The MAXQ7667 peripheral register space (modules 0 to 5) contains registers that access the following peripherals: • Two general-purpose, 8-bit, I/O ports (P0, P1) • External interrupts (up to 16) • Three programmable Type 2 timer/counters • LIN-compatible UART interface • SPI • Analog module (SAR ADC and ultrasonic measurement) • Hardware multiplier • JTAG debug engine • Schedule timer The lower 8 bits of all registers in modules 0 to 5 (as well as the AP module M8) are bit addressabl
MAXQ7667 User’s Guide Table 2-2.
MAXQ7667 User’s Guide ing address of the utility ROM. The default IP setting of 8000h is assigned to allow initial in-system programming to be accomplished with utility ROM code assistance. The utility ROM code interrogates a specific register bit in order to decide whether to execute in-system programming or jump immediately to user code starting at 0000h. The user code reset vector should always be stored in the lowest bytes of the program memory. 2.2.3.
MAXQ7667 User’s Guide tion. Using Data Pointer indirectly with "++" will automatically increase the content of the active Data Pointer by 1 immediately following the execution of read data transfer (@DP[n]++) or immediately preceding the execution of a write operation (@++DP[n]).
MAXQ7667 User’s Guide 2.2.3.5 Pseudo-Von Neumann Memory Mapping The MAXQ7667 supports a pseudo-Von Neumann memory structure that can merge program and data into a linear memory map. This is accomplished by mapping the data memory into the program space or mapping program memory segment into the data space. In all MAXQ processors the program memory ranges from x0000h to x7FFFh is the normal user code segment, followed by the utility ROM segment.
MAXQ7667 User’s Guide 2.2.3.6 Pseudo-Von Neumann Memory Access The pseudo-Von Neumann memory mapping is straightforward if there is no memory overlapping among the program, utility ROM, and data memory segments. When accessing the program memory as data, the CDA bit can be used to select the program pages as needed. Full data memory access to the physical program memory pages is based on the assumption that the maximum physical data memory is in the range of 16K x 16.
MAXQ7667 User’s Guide 2.2.3.8 Memory Management Unit Memory allocation and accessing control for program and data memory can be managed by the memory management unit (MMU). A single memory management unit option is discussed in this user’s guide, however the memory management unit implementation for any given product depends upon the type and amount of memory addressable by the device. Users should consult the individual product data sheet(s) and/or user’s guide supplement(s) for detailed information.
MAXQ7667 User’s Guide EXECUTING FROM PROGRAM SPACE (UPA = 0, ONLY P0 PRESENT) 15 PROGRAM MEMORY 0 15 DATA MEMORY 0 0xFFFF 0xFFFF LOGICAL SPACE 0xA800 LOGICAL DATA MEMORY 0xA000 LOGICAL SPACE 0x9000 0x9000 UTILITY ROM UTILITY ROM 0x8000 0x8000 0x4000 PHYSICAL PROGRAM (P0) 0x800 PHYSICAL DATA 0x0000 x0000 EXECUTING FROM UTILITY ROM (UPA = 0, ONLY P0 PRESENT) 15 PROGRAM MEMORY 15 0 DATA MEMORY 0 xFFFF LOGICAL SPACE 0xA800 xC000 LOGICAL DATA MEMORY xA000 LOGICAL SPACE x9000 UTILITY ROM
MAXQ7667 User’s Guide EXECUTING FROM PROGRAM SPACE (UPA = 0, ONLY P0 PRESENT) 15 PROGRAM MEMORY 7 0 DATA MEMORY 0 0xFFFF 0xFFFF LOGICAL SPACE 0xA800 LOGICAL DATA MEMORY 0xA000 0xA000 LOGICAL SPACE 0x9000 UTILITY ROM 0x8000 0x8000 0x4000 0x1000 PHYSICAL PROGRAM (P0) PHYSICAL DATA 0x0000 0x0000 EXECUTING FROM UTILITY ROM (UPA = 0, ONLY P0 PRESENT) 15 PROGRAM MEMORY 0 7 DATA MEMORY 0 xFFFF xFFFF LOGICAL SPACE 0xA800 LOGICAL DATA MEMORY xA000 LOGICAL SPACE x9000 UTILITY ROM x8000 x8
MAXQ7667 User’s Guide 2.2.4 Interrupts The MAXQ7667 provides a single, programmable interrupt vector (IV) that can be used to handle internal and external interrupts. Interrupts can be generated from system level sources (e.g., watchdog timer) or by sources associated with the peripheral modules included in the specific MAXQ7667 microcontroller. Only one interrupt can be handled at a time, and all interrupts naturally have the same priority.
MAXQ7667 User’s Guide 2.2.4.3 Synchronous vs. Asynchronous Interrupt Sources Interrupt sources can be classified as either asynchronous or synchronous. All internal interrupts are synchronous interrupts. An internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle. All external interrupts are asynchronous interrupts by nature.
MAXQ7667 User’s Guide SYSTEM MODULES WDIF (WATCHDOG) EWDI (LOCAL ENABLE) IMS (SYSTEM ENABLE) MODULE 0 EIF0.0 EIF0.1 EIF0.5 EIE0.0–EIE0.5 (LOCAL ENABLES) EIF1.0 EIF1.1 EIF1.7 EIE1.0–EIE1.
MAXQ7667 User’s Guide Table 2-3. MAXQ7667 Interrupt Sources and Control Bits INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG External Interrupt Port 0 0 EX0 (EIE0.0) IE0 (EIF0.0) External Interrupt Port 0 1 EX1 (EIE0.1) IE1 (EIF0.1) External Interrupt Port 0 2 EX2 (EIE0.2) IE2 (EIF0.2) External Interrupt Port 0 3 EX3 (EIE0.3) IE3 (EIF0.3) External Interrupt Port 0 4 EX4 (EIE0.4) IE4 (EIF0.4) External Interrupt Port 0 5 EX5 (EIE0.5) IE5 (EIF0.5) EX0 (EIE1.0) IE0 (EIF1.
MAXQ7667 User’s Guide Table 2-3. MAXQ7667 Interrupt Sources and Control Bits (continued) INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAG SAR ADC Data Ready SARIE (AIE.0) SARRDY (ASR.0) Echo Envelope Lowpass Filter Output LPFIE (AIE.1) LPFRDY (ASR.1) Echo Envelope Lowpass Filter FIFO Full Interrupt LFLIE (AIE.2) LPFFL (ASR.2) CMPIE (AIE.3) CMPI (ASR.3) AVDD Brownout Interrupt VABIE (AIE.4) VABI (ASR.4) DVDD Brownout Interrupt VDBIE (AIE.5) VDBI (ASR.
MAXQ7667 User’s Guide SECTION 3: PROGRAMMING This section contains the following information: 3.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.2 Prefixing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.3 Reading and Writing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 3.
MAXQ7667 User’s Guide 3.7.3 Conditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 3.7.4 Calling Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 3.7.5 Looping Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 3.7.6 Conditional Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 3: PROGRAMMING This section provides a programming overview of the MAXQ7667. For full details on the instruction set, as well as System Register and Peripheral Register detailed bit descriptions, see the appropriate sections in this user’s guide. 3.1 Addressing Modes The instruction set for the MAXQ7667 provides three different addressing modes: direct, indirect, and immediate.
MAXQ7667 User’s Guide Generally, prefixing operations can be inserted automatically by the assembler as needed, so that (for example) move DP[0], #1234h actually assembles as move PFX[0], #12h move DP[0], #34h However, the operation move DP[0], #0055h does not require a prefixing operation even though the register DP[0] is 16-bit. This is because the prefix value defaults to zero, so the line move is not required. PFX[0], #00h 3.
MAXQ7667 User’s Guide 3.3.4 Moving Values Between Registers of Different Sizes Before covering some transfer scenarios that might arise, a special register must be introduced that will be used in many of these cases. The 16-bit General Register (GR) is expressly provided for performing byte singulation of 16-bit words. The high and low bytes of GR are individually accessible in the GRH and GRL registers respectively.
MAXQ7667 User’s Guide 3.3.4.5 High (16-Bit Destination) ← 8-Bit Source To modify only the high byte of a given 16-bit destination, the 16-bit register should be moved into the GR register such that the low byte can be singulated and the high byte can be written exclusively. Additional cycles are required if the destination index is greater than 0Fh or if the source index is greater than 0Fh.
MAXQ7667 User’s Guide 3.5.2 Enabling Autoincrement and Autodecrement The accumulator pointer AP can be set to automatically increment or decrement after each arithmetic or logical operation. This is useful for operations involving a number of accumulator registers, such as adding or subtracting two multibyte integers.
MAXQ7667 User’s Guide The Accumulator Pointer Control Register (APC) controls the automatic-increment/decrement mode as well as selects the range of bits (modulo) in the AP register that will be incremented or decremented. There are nine different unique settings for the APC register, as listed in Table 3-1. Table 3-1. Accumulator Pointer Control Register Settings APC.2 (MOD2) APC.1 (MOD1) APC.0 (MOD0) APC.
MAXQ7667 User’s Guide 3.5.3 ALU Operations Using the Active Accumulator and a Source The following arithmetic and logical operations can use any register or immediate value as a source. The active accumulator Acc is always used as the second operand and the implicit destination. Also, Acc may not be used as the source for any of these operations.
MAXQ7667 User’s Guide 3.5.6 Example: Adding Two 4-Byte Numbers Using Autoincrement move A[0], #5678h ; First number – 12345678h move A[1], #1234h move A[2], #0AAAAh ; Second number – 0AAAAAAAh move A[3], #0AAAh move APC, #81h ; Active Acc = A[0], increment low bit = mod 2 add A[2] ; A[0] = 5678h + AAAAh = 0122h + Carry addc A[3] ; A[1] = 1234h + AAAh + 1 = 1CDFh ; 12345678h + 0AAAAAAAh = 1CDF0122h 3.
MAXQ7667 User’s Guide • SLA, SLA2, SLA4 (Arithmetic shift left active accumulator) • SRA, SRA2, SRA4 (Arithmetic shift right active accumulator) • SR (Shift active accumulator right) • RLC/RRC (Rotate active accumulator left/right through Carry) • MOVE C, Acc. (Set Carry to selected active accumulator bit) • MOVE C, #i (Explicitly set, i = 1, or clear, i = 0, the Carry flag) • CPL C (Complement Carry) • AND Acc. • OR Acc. • XOR Acc. • MOVE C, src.
MAXQ7667 User’s Guide 3.7.2 Unconditional Jumps An unconditional jump can be relative (IP +127/-128 words) or absolute (to anywhere in program space). Relative jumps must use an 8-bit immediate operand, such as Label1: ... jump Label1 ; must be within +127/-128 words of the JUMP Absolute jumps can use a 16-bit immediate operand, a 16-bit register, or an 8-bit register.
MAXQ7667 User’s Guide When the supplied loop address is outside the relative jump range, the prefix register (PFX[0]) is used to supply the high byte of the loop address as required. move LoopTop: call ...
MAXQ7667 User’s Guide Once the interrupt handler receives the interrupt, the Interrupt in Service (INS) bit will be set by hardware to block further interrupts, and execution control is transferred to the interrupt service routine. Within the interrupt service routine, the source of the interrupt must be determined. Since all interrupts go to the same interrupt service routine, the Interrupt Identification Register (IIR) must be examined to determine which module initiated the interrupt.
MAXQ7667 User’s Guide 3.9 Accessing the Stack The hardware stack is used automatically by the CALL, RET and RETI instructions, but it can also be used explicitly to store and retrieve data. All values stored on the stack are 16 bits wide. The PUSH instruction increments the stack pointer SP and then stores a value on the stack. When pushing a 16-bit value onto the stack, the entire value is stored.
MAXQ7667 User’s Guide 3.10 Accessing Data Memory Data memory is accessed through the data pointer registers DP[0] and DP[1] or the Frame Pointer BP[OFFS]. Once one of these registers is set to a location in data memory, that location can be read or written as follows, using the mnemonic @DP[0], @DP[1] or @BP[OFFS] as a source or destination.
MAXQ7667 User’s Guide Once the pointer selection has been made, it will remain in effect until: • the source data pointer select bits are changed via the explicit or implicit methods described above (i.e., another data pointer is selected for use) • the memory to which the active source data pointer is addressing is enabled for code fetching using the Instruction Pointer, or • a memory write operation is performed using a data pointer other than the current active source pointer.
MAXQ7667 User’s Guide SECTION 4: REGISTER DESCRIPTIONS This section contains the following information: 4.1 System Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 4.1.1 Accumulator Pointer Register (AP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 4.1.2 Accumulator Pointer Control Register (APC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 4.1.
MAXQ7667 User’s Guide LIST OF TABLES Table 4-1. MAXQ7667 System Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Table 4-2. MAXQ7667 System Register Bit Functions and Reset Value . . . . . . . . . . . . . . . . . . . .4-4 Table 4-3. MAXQ7667 Peripheral Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22 Table 4-4. MAXQ7667 Module 0 Register Bit Functions and Reset Values . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 4: REGISTER DESCRIPTIONS 4.1 System Register Descriptions The MAXQ7667 system register map is shown in Table 4-1. The system register bit functions and reset value are shown in Table 4-2. Those registers defined in the MAXQ7667 system register map are described in the following sections. The address for each register are given in the format module[index], where module is the module specifier from 8h to Fh and index is the register subindex from 0h to Fh. Table 4-1.
A[n]11 A[n]10 A[n]9 A[n]8 0 LC[1] 0Dh[07h] 0 0 0 0 0 0 0 0 LC[1]7 0 LC[0]7 0 IV7 0 — 0 IP7 0 LC[1]6 0 LC[0]6 0 IV6 0 — 0 IP6 0 PFX[n]6 ___________________________________________________________________________________________________________ 0 DPC 0Eh[04h] 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 OFFS5 0 LC[1]5 0 LC[0]5 0 IV5 0 — 0 IP5 0 PFX[n]5 0 A[n]5 0 WD1 0 RCMD 0 II5 0 CDA1 0 IM5 0 CGDS 0 — 0 — 0 — 5 s = Bit
4-5 GR14 GR15 0 GR 0Eh[05h] GR7 7 GR6 6 0 0Eh[08h] GRS7 0 BP7 0 GRS6 0 BP6 0 DP[1]13 0 DP[0]13 0 FP13 0 GRXL13 0 DP[1]12 0 DP[0]12 0 FP12 0 GRXL12 0 DP[1]11 0 DP[0]11 0 FP11 0 GRXL11 0 DP[1]10 0 DP[0]10 0 FP10 0 GRXL10 0 DP[1]9 0 DP[0]9 0 FP9 0 GRXL9 0 DP[1]8 0 DP[0]8 0 FP8 0 GRXL8 0 DP[1]7 0 DP[0]7 0 FP7 0 GRXL7 0 DP[1]6 0 DP[0]6 0 FP6 0 GRXL6 0 DP[1]5 0 DP[0]5 0 FP5 0 GRXL5 0 GRH5 0 GRS5 0 BP5 0 GRL5 0 GR5
MAXQ7667 User’s Guide 4.1.1 Accumulator Pointer Register (AP) Register Description: Register Name: Register Address: Accumulator Pointer Register AP Module 08h, Index 00h Bit # 7 6 5 4 3 2 1 0 Name — — — — AP3 AP2 AP1 AP0 Reset 0 0 0 0 0 0 0 0 Access r r r r rw rw rw rw r = read, w = write Note: This register is cleared to 00h on all forms of reset. Bits 7 to 4: Reserved. Read 0, write ignored. Bits 3 to 0: Accumulator Select 3:0 (AP[3:0]).
MAXQ7667 User’s Guide Bits 2 to 0: Accumulator Pointer Autoincrement/Decrement Modulus (MOD[2:0]). If these bits are set to a nonzero value, the accumulator pointer (AP[3:0]) will be automatically incremented or decremented following each arithmetic or logical operation. The mode for the autoincrement/decrement is determined as follows: MOD[2:0] AUTOINCREMENT/DECREMENT MODE 000 No autoincrement/decrement (default). 001 Increment/decrement AP[0] modulo 2. 010 Increment/decrement AP[1:0] modulo 4.
MAXQ7667 User’s Guide 4.1.4 Interrupt and Control Register (IC) Register Description: Register Name: Register Address: Interrupt and Control Register IC Module 08h, Index 05h Bit # 7 6 5 4 3 2 1 0 Name — — CGDS — — — INS IGE Reset 0 0 0 0 0 0 0 0 Access r r rw r r r rw rw r = read, w = write Note: This register is cleared to 00h on all forms of reset. Bits 7, 6, 4, 3, and 2: Reserved. Read 0, write ignored. Bit 5: System Clock Gating Disable (CGDS).
MAXQ7667 User’s Guide 4.1.6 System Control Register (SC) Register Description: Register Name: Register Address: Bit # System Control Register SC Module 08h, Index 08h 7 6 5 4 3 2 1 0 Name TAP — CDA1 CDA0 UPA ROD PWL — Reset 1 0 0 0 0 0 1 0 Access rw r rw rw rw rw rw r r = read, w = write Note: Bit 1 (PWL) is set to 1 on a power-on reset only. Bit 7: Test Access (JTAG) Port Enable (TAP). This bit controls whether the Test Access Port special-function pins are enabled.
MAXQ7667 User’s Guide 4.1.7 Interrupt Identification Register (IIR) The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module. The eighth bit, IIS, indicates a pending system interrupt, such as from the watchdog timer. The interrupt pending flags will be set only for enabled interrupt sources waiting for service.
MAXQ7667 User’s Guide 4.1.9 Watchdog Timer Control Register (WDCN) The 8-bit WDCN register is part of the system register group and used to provide system control. It controls the watchdog timeout period and interrupt or reset generation on watchdog timeout. The watchdog timer is clocked by the internal RC oscillator. See Section 15 for a description of this register.
MAXQ7667 User’s Guide 4.1.
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MAXQ7667 User’s Guide 4.1.23 General Register High Byte (GRH) Register Description: Register Name: Register Address: Bit # Name General Register High Byte GRH Module 0Eh, Index 09h 7 6 5 4 3 2 1 0 GRH7 GRH6 GRH5 GRH4 GRH3 GRH2 GRH1 GRH0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Note: This register is cleared to 00h on all forms of reset. Bits 7 to 0: General Register High Byte Bits 7:0 (GRH[7:0]).
MAXQ7667 User’s Guide 4.1.
MAXQ7667 User’s Guide 4.1.
MAXQ7667 User’s Guide 4.2 Peripheral Register Modules The MAXQ7667 microcontroller uses peripheral registers to control and monitor peripheral modules. These registers reside in Modules 0h to 5h, with subindex values 0h to 1Fh. The MAXQ7667 peripheral register map is shown in Table 4-3. The peripheral register module bit function and reset values are shown in Table 4-4. Each peripheral modules and its associated registers/bits are covered separately in their respective sections. Table 4-3.
4-23 __________________________________________________________________________________________________________ 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 14 15 st = Dependent on the pin’s state.
0 — 0 STIM14 0 SALM14 0 0 — 0 STIM15 0 SALM15 0 0 MC0R14 0 MC0R15 0 MC1R14 0 MC1R15 0 — 0 — — — 0 — — 0 0 SPIB14 SPIB15 0 0 MC014 MC015 0 0 0 0 MC114 0 MC115 0 MC214 0 MB14 MC215 MB15 0 MA14 MA15 0 0 — — 0 14 15 0 SALM13 0 STIM13 0 — 0 MC0R13 0 MC1R13 0 — 0 — 0 — 0 SPIB13 0 MC013 0 MC113 0 MC213 0 MB13 0 MA13 0 — 13 0 SALM12 0 STIM12 0 — 0 MC0R12 0 MC1R12 0 — 0 — 0 — 0 SPIB12 0 MC012 0 MC112 0
4-25 0 ID014 P ID114 P 0 ID015 P ID115 P P ID113 P ID013 0 — 0 0 — 0 — — — — 13 14 15 P ID112 P ID012 0 — 0 — 12 P ID111 P ID011 0 — 0 — 11 P ID110 P ID010 0 — 0 — 10 9 P ID19 P ID09 0 — 0 — P ID18 P ID08 P RCTRM8 0 — 8 P ID17 P ID07 P RCTRM7 0 — 7 REGISTER BIT 6 P ID16 P ID06 P RCTRM6 0 — 5 P ID15 P ID05 P RCTRM5 0 — P = Cleared to 00h on power-on reset and then, if required, initialized to a value stored wi
0 T2C114 T2C115 0 0 T2R114 T2R115 0 0 T2V114 T2V115 0 0 — — 0 0 T2C014 T2C015 0 0 T2R014 T2R015 0 0 T2V014 T2V015 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — 0 — 0 — — 0 0 — — 0 14 15 0 T2C113 0 T2R113 0 T2V113 0 — 0 T2C013 0 T2R013 0 T2V013 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 13 0 T2C112 0 T2R112 0 T2V112 0 — 0 T2C012 0 T2R012 0 T2V012 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0
4-27 0 0 0 ICDD14 0 ICDA14 db ICDD15 ICDA15 db db ICDT114 db ICDT115 0 ICDT014 0 ICDT015 0 — 0 — — — 14 15 0 ICDD13 0 ICDA13 db ICDT113 db ICDT013 0 — 0 — 13 0 ICDD12 0 ICDA12 db ICDT112 db ICDT012 0 — 0 — 12 0 ICDD11 0 ICDA11 db ICDT111 db ICDT011 0 — 0 — 11 0 — 0 — 10 0 ICDD10 0 ICDA10 db ICDT110 db ICDT010 db = Special: read/write access only in background or debug mode. dw = Special: read/write by debug engine.
03h[11h] STA0 03h[10h] T2CFG2 03h[0Fh] ISVEC 03h[0Eh] CHKSUM 03h[0Dh] ERRR 03h[0Ch] FSTAT 03h[0Bh] T2C2 03h[0Ah] T2R2 03h[09h] T2V2 03h[08h] T2CNB2 03h[07h] SBUF 03h[06h] SCON 03h[05h] CNT1 03h[03h] T2CH2 03h[02h] T2RH2 03h[01h] T2H2 03h[00h] T2CNA2 REGISTER 0 T2C213 0 T2R213 0 T2V213 0 — 0 — 0 — 0 — 0 — 13 0 T2C212 0 T2R212 0 T2V212 0 — 0 — 0 — 0 — 0 — 12 0 T2C211 0 T2R211 0 T2V211 0 — 0 — 0 — 0 — 0 — 11 0 T2C210 0 T2R
4-29 03h[1Ah] TMR 03h[19h] BT 03h[18h] SADEN 03h[17h] SADDR 03h[16h] IDFB 03h[15h] CNT2 03h[14h] CNT0 03h[13h] FCON 03h[12h] SMD REGISTER 0 0 0 TMR14 0 BT14 0 — 14 TMR15 BT15 0 — 15 0 TMR13 0 BT13 1 IDFBH5 13 0 TMR12 0 BT12 1 IDFBH4 12 0 TMR11 0 BT11 1 IDFBH3 11 0 TMR10 0 BT10 1 IDFBH2 10 0 TMR9 0 BT9 1 IDFBH1 9 0 TMR8 0 BT8 1 IDFBH0 8 0 0 TMR7 0 BT7 0 0 TMR6 0 BT6 0 0 SADEN6 0 SADEN7 0 SADDR6 0 — SADDR7 — 0 0 —
__________________________________________________________________________________________________________ 0 RBUFE — 0 0 LPFF14 LPFF15 0 0 LPFD14 LPFD15 0 0 BPFO14 BPFO15 0 0 BPFI14 BPFI15 0 0 — — 0 0 FFIL2 FFIL3 0 0 — — 0 0 DVLVL VIOLVL 0 0 CMPT14 CMPT15 0 0 CMPH14 CMPP 0 0 — — 0 0 — — 0 0 — — 0 0 — 0 — 0 BDIV2 BDIV3 1 0 BDS BSTT 0 14 15 s = Bits clear on power-on reset.
4-31 05h[1Eh] A3D 05h[1Ch] A3B 05h[1Bh] A3A 05h[19h] A2D 05h[17h] A2B 05h[16h] A2A 05h[15h] B3COEF 05h[14h] B2COEF 05h[13h] B1COEF 05h[12h] FGAIN REGISTER FGAIN14 FGAIN15 FGAIN13 13 FGAIN12 12 FGAIN11 11 FGAIN10 10 FGAIN9 9 7 FGAIN7 0x7B5C FGAIN8 8 REGISTER BIT FGAIN6 6 FGAIN5 5 FGAIN4 4 FGAIN3 3 FGAIN2 2 FGAIN1 1 FGAIN0 0 A3D15 A3B15 A3A15 A2D15 A2B15 A2A15 B3COEF15 A3D14 A3B14 A3A14 A2D14 A2B14 A2A14 B3COEF14 A3D13 A3B13 A3A13 A2D13 A2B13 A2A13
MAXQ7667 User’s Guide SECTION 5: GENERAL-PURPOSE I/O MODULE This section contains the following information: 5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 5.1.1 Enhanced Type D I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 5.1.2 GPIO Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide LIST OF FIGURES Figure 5-1. Enhanced Type D Port Pin Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 LIST OF TABLES Table 5-1. Port P0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 Table 5-2. Port P1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4 Table 5-3.
MAXQ7667 User’s Guide SECTION 5: GENERAL-PURPOSE I/O MODULE The MAXQ7667 smart data-acquisition microcontroller provides 2 ports (P0 and P1) for general-purpose I/O, each with 8 port pins.
MAXQ7667 User’s Guide 5.1.2 GPIO Port Pins The MAXQ7667 port P0 and P1 pins are summarized in Table 5-1 and Table 5-2. Table 5-1. Port P0 Pins PORT P0 SIGNALS PIN P0.0/URX 9 Digital GPIO and UART Receive Data Input. As URX this pin is the receive data input of the UART, which can (optionally) be connected to RXD of a LIN transceiver. P0.1/UTX 10 Digital GPIO and UART Transmit Data Output.
MAXQ7667 User’s Guide 5.2 Port Registers The following peripheral registers control the general-purpose I/O and external interrupt features specific to the MAXQ7667. 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide 5.2.
MAXQ7667 User’s Guide In addition to the standard enhanced Type D GPIO port features, the MAXQ7667 offers programmable drive strength and programmable direction of resistive pullup or pulldown. 5.2.
MAXQ7667 User’s Guide 5.2.16 Pad Resistive Pull Direction Register (Port 1) (PR1) Pad Resistive Pull Direction Register (Port 1) PR1 Module 00h, Index 1Ch Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name PR17 PR16 PR15 PR14 PR13 PR12 PR11 PR10 Reset 1 1 1 1 1 1 1 1 Access rw rw rw rw rw rw rw rw r = read, w = write Note: This register is cleared to FFh on all forms of reset. Bits 7 to 0: Port 1 Resistive Select Bits 7:0 (PR1[7:0]).
MAXQ7667 User’s Guide The ports (P0 and P1) can be used to support applications that require open-drain/open-source functionality. This can be achieved by using the PO and PD register of the port. • Three-state the port pin needed to be open drain by setting the corresponding PDn.x bit to 0. • Clear the corresponding POn.x bit to 0. • Use the corresponding PDn.x bit to drive the port pin function, instead of the POn.x register.
MAXQ7667 User’s Guide Table 5-4. Port P0 Pin Special and Alternate Functions (continued) PORT P0 PIN FUNCTION TYPE FUNCTION Special TXEN—As TXEN this pin can be used to control the transmit enable of an external driver (active low). This pin defaults to TXEN any time the UART is used. TXEN is low when the UART is transmitting, and is resistively pulled high/low when it is not. SBUF loaded with data Alternate External Interrupt 2, Input (EIE0.2) EX2 = 1 Special T0—Timer 0 (Type 2) Output (T2CNA0.
MAXQ7667 User’s Guide Table 5-4. Port P0 Pin Special and Alternate Functions (continued) PORT P0 PIN FUNCTION TYPE FUNCTION ENABLED WHEN Special T2—Timer 2 (Type 2) Output (T2CNA2.6) T2OE0 = 1 Special T2—Timer 2 (Type 2) Counter Input (T2CFG2.0) C/T2 = 1 (T2CFG2[2:1]) CCF[1:0] =! 00b (T2CNA2.6) T2OE0 must be 0 Special T2—Timer 2 (Type 2) Gate Input (T2CNA2.0) G2EN = 1 or (T2CFG2[2:1]) CCF[1:0] = 11b and (T2CNA2.2) CPRL2 = 1 (T2CNA2.6) T2OE0 must be 0 (T2CFG2.
MAXQ7667 User’s Guide Table 5-5. Port P1 Pin Special and Alternate Functions (continued) PORT P1 PIN P1.6/SCLK FUNCTION TYPE FUNCTION ENABLED WHEN Special SCLK—Serial Clock, Master Mode, Output — Special SCLK—Serial Clock, Slave Mode, Input — Alternate External Interrupt 6, Input (EIE1.6) EX6 = 1 Special SYNC—Resets the Synchronous Timer (SCNT.8) SSYNC_EN = 1 Special SS—Slave Select for the SPI, Input, Slave Mode (SPICN.0) SPIEN = 1 (SPICN.1) MSTM = 0 (SPICN.
MAXQ7667 User’s Guide SECTION 6: TYPE 2 TIMER/COUNTER MODULE This section contains the following information: 6.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.1.1 Modes of Operation for Type 2 Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 6.1.2 Type 2 Timer/Counter I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6 6.
MAXQ7667 User’s Guide 6.7.9 Type 2 Timer Capture Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27 6.7.9.1 Measure Low-Pulse Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27 6.7.9.2 Measure High-Pulse Duration Repeatedly . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 6.7.9.3 Measure Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29 6.7.9.
MAXQ7667 User’s Guide SECTION 6: TYPE 2 TIMER/COUNTER MODULE The MAXQ7667 microcontroller has three Type 2 timer/counters. The Type 2 timer/counter is an autoreload 16-bit timer/counter with the following functions: • 8-bit/16-bit timer/counter • Up/down autoreload • Counter function of external pulse • Capture • Compare • Input/output enhancements The three Type 2 timer/counter modules supported in the MAXQ7667 are referred to as timer 0, timer 1, and timer 2.
MAXQ7667 User’s Guide CAPTURE T2Cx REGISTER 16-BIT CAPTURE/COMPARE EQUAL INPUT CONDITIONING SCALING GATING CLOCK T2Vx REGISTER 16-BIT UP COUNTER OVERFLOW OUTPUT CONDITIONING POLARITY SELECTION RELOAD T2Rx REGISTER 16-BIT RELOAD Figure 6-1.
MAXQ7667 User’s Guide T2CLx REGISTER (LOWER BYTE OF T2Cx) 8-BIT CAPTURE/COMPARE LOW CAPTURE EQUAL CLOCK T2Lx REGISTER (LOWER BYTE OF T2Vx) 8-BIT UP COUNTER LOW OUTPUT CONDITIONING POLARITY SELECTION OVERFLOW RELOAD T2RLx REGISTER (LOWER BYTE OF T2Rx) 8-BIT RELOAD LOW INPUT CONDITIONING SCALING GATING T2CHx REGISTER 8-BIT CAPTURE/COMPARE HIGH EQUAL CLOCK T2Hx REGISTER 8-BIT UP COUNTER HIGH OVERFLOW OUTPUT CONDITIONING POLARITY SELECTION RELOAD CAPTURE T2RHx REGISTER 8-BIT RELOAD HIGH Figure
MAXQ7667 User’s Guide 6.1.2 Type 2 Timer/Counter I/O Pins Each of the three timer/counters, typically, has a pair of pins associated with it to support the enhanced input/output functionality. The pair of pins are referred to as the primary and secondary pins and are designated the symbols T2P0 and T2PB0, respectively. Because there are three Type 2 timers, the pairs are referred to as follows: T2P0, T2PB0; T2P1; T2P2, T2PB2 (secondary pin is not available for timer 1).
MAXQ7667 User’s Guide 6.2 Type 2 Timer/Counter Peripheral Registers Table 6-2. Type 2 Timer/Counter Register Map REGISTER MODULE NUMBER INDEX T2CFG0 02h 10h Timer/Counter 0 (Type 2) Configuration Register. Controls counter/timer select, capture/compare function select, 8-/16-bit mode select, and clock divide modes. T2CNA0 02h 00h Timer/Counter 0 (Type 2) Control Register A. I/O settings, run enables, polarity modes. T2CNB0 02h 08h Timer/Counter 0 (Type 2) Control Register B.
MAXQ7667 User’s Guide 6.3 Type 2 Status/Control Registers 6.3.
MAXQ7667 User’s Guide Bits 2 and 1: Capture/Compare Function Select Bits (CCF1 and CCF0). These bits, in conjunction with the C/T2 bit, select the basic operating mode of the Type 2 timer. In the dual 8-bit mode of operation (T2MD = 1), the T2Lx timer only operates in compare mode.
MAXQ7667 User’s Guide Bit 6: Type 2 Timer Output Enable 0 (T2OE0). This register bit enables the timer output function for the external T2P pin. The following table shows the timer output possibilities for the T2P, T2PB pins. (T2OE1 bit is in the T2CNBx register.
MAXQ7667 User’s Guide Bit 0: Gating Enable (G2EN). This bit enables the external T2Px pin to gate the input clock to the 16-bit (T2MD = 0) or highest 8-bit (T2MD = 1) timer. Gating uses T2Px as an input, so it can only be used when T2OE0 = 0 and C/T2 = 0. Gating is not possible on the low 8-bit timer (T2Lx) when the Type 2 timer is operated in dual 8-bit mode. Gating is not supported for counter mode operation (C/T2 = 1).
MAXQ7667 User’s Guide 6.4 Type 2 Counter Registers 6.4.
MAXQ7667 User’s Guide 6.4.
MAXQ7667 User’s Guide 6.5 Type 2 Reload Register 6.5.
MAXQ7667 User’s Guide 6.5.
MAXQ7667 User’s Guide 6.6 Type 2 Capture/Compare Registers 6.6.
MAXQ7667 User’s Guide 6.6.
MAXQ7667 User’s Guide 6.7 Type 2 Timer/Counter Operation Modes The MAXQ7667 Type 2 timer/counter supports six operation modes. Table 6-3 summarizes the modes supported by the Type 2 timer and the peripheral register bits associated with those modes. The Type 2 timer operating mode selection is illustrated in Figure 6-3. Figure 6-4 shows the PWM timer output possibilities. Table 6-3.
MAXQ7667 User’s Guide T2OE[0] T2CHx T2CLx T2Vx COMPARE MATCH OR T2Hx COMPARE MATCH TR2L T2MD T2Lx OVERFLOW T2Lx T2Hx:T2Lx OVERFLOW OR T2Hx OVERFLOW T2Hx T2CLK C/T2 T2RLx EDGE DETECTION AND GATING T2RHx T2Px PIN INPUT CCF[1:0] G2EN TR2 SS2 T2POL[0] Figure 6-3. Type 2 Timer Mode Selection PORT LATCH (IF PDn.q = 1, WHERE n = PORT # AND q = BIT #) T2Lx 8-BIT TIMER T2PBx PIN T2POL[1] T2MD T2Vx 16-BIT TIMER OR T2Hx 8-TIMER T2OE[1] POx.x DATA (IF PDx.
MAXQ7667 User’s Guide 6.7.1 16-Bit Timer: Autoreload/Compare The 16-bit autoreload/compare mode for the Type 2 timer is in effect when the timer-mode select bit (T2MD) is cleared and the capture/compare function definition bits are both cleared (CCF[1:0] = 00b). The timer value is contained in the T2Vx register. The timer run control bit (TR2) starts and stops the 16-bit timer.
MAXQ7667 User’s Guide 6.7.2 16-Bit Timer: Capture Mode The 16-bit capture mode requires that some event trigger the capture. Normally, this event will be an external edge. The CCF[1:0] bits define which edge(s) causes a capture to occur. If CCF[1:0] = 01b, a rising edge causes a capture. If CCF[1:0] = 10b, a falling edge causes a capture. If CCF[1:0] = 11b, rising and falling edges both cause a capture to occur. The CPRL2 bit enables both capture and reload to occur on the specified edge(s).
MAXQ7667 User’s Guide 6.7.4 Dual 8-Bit Timers The dual 8-bit timer mode of operation is initiated by setting the T2MD bit to logic 1. When T2MD = 1, each 16-bit register associated with the Type 2 timer is split into separate upper and lower 8-bit registers to support dual 8-bit timers. Thus, the primary 8-bit timer is composed of T2Hx (value), T2RHx (reload), T2CHx (capture/compare), and the secondary 8-bit timer is composed of T2Lx (value), T2RLx (reload), and T2CLx (capture/compare).
MAXQ7667 User’s Guide 6.7.7 Type 2 Timer Input Clock Selection The Type 2 timer clock source is illustrated in Figure 6-5. The timer input clock is selected by the T2CI bit while the clock prescale is determined by the T2DIV bits in the T2CFGx register. Note that when T2CI is configured to a 1, the alternate clock source (32kHz) is sampled by the current system clock selection. The maximum frequency that can be sampled on the alternate clock frequency is (system clock/4).
MAXQ7667 User’s Guide org 0 ; main_top: move T2V0, #04000h move move T2R0, #04000h T2C0, #0C000h move T2CFG0, #000h ; ; 0000 0000 0, ; C/T2 ; CCF1:0 00, ; T2MD 0, 000, ; T2DIV2:0 ;T2CI 0, move T2CNB0, #040h ; ; 0100 0000 ; TC2L 0, ; TCC2 0 ; TF2L 0, ; TF2 0, ; X x, ; T2POL1 0, ; T2OE1 1, ; ET2L 0, move ; ; ; ; ; ; ; ; ; ; ; ; ; ; Set to reload value to keep first pulse from being extra long Reload Value Compare Value Timer Mode Compare Mode 16-bit Mode No freq pre-scaling use system clock Not used
MAXQ7667 User’s Guide 6.7.8.2 Waveform Output with Gating This example uses the code from the previous example, with the modification that the primary pin is now the gating input. The output on the secondary pin is gated when the primary pin is low. The 1/3 duty cycle waveform is output on the secondary pin whenever the primary pin is held high. NOT TO SCALE INPUT ON THE PRIMARY PIN OUTPUT ON THE SECONDARY PIN COUNT SUSPENDED COUNT RESUMED Figure 6-7.
MAXQ7667 User’s Guide ; ; ; ; ; ; ; ; move ; ; ; ; ; ; ; ; ; 0100 0000 TC2L TCC2 TF2L TF2 T2POL1 T2OE1 ET2L 0, 0, 0, 0, 0, 1, 0, Not used Not used Not used Not used Low Starting value on secondary pin Secondary pin is enabled as output Not used T2CNA0, #009h 0000 1001 G2EN SS2 CPRL2 TR2 TR2L T2POl0 T2OE0 ET2 1, 0, 0, 1, 0, 0, 0, 0, Gating enabled Single shot disabled Not used Run enabled Not used gated when primary pin is low Primary pin is used for gating Not used loop1: ; body of the code, loop he
MAXQ7667 User’s Guide 6.7.9 Type 2 Timer Capture Application Examples The following examples are used to demonstrate some of the Type 2 timer capture functions. All examples assume that pulse and/or period measurements do not exceed 216 (i.e., 65,536) input clocks and that capture register holds the desired result. 6.7.9.
MAXQ7667 User’s Guide 6.7.9.2 Measure High-Pulse Duration Repeatedly To measure the duration of high pulses seen on the T2P0 input pin repeatedly, the Type 2 timer is configured for a single-shot delayed run, gating enabled for logic low, capture on the falling edge. The CPRL2 bit can be set to generate a reload on each falling edge.
MAXQ7667 User’s Guide 6.7.9.3 Measure Period To measure the period of the signal seen on the T2P0 input pin, the Type 2 timer is configured for a single-shot capture, no gating, either edge (selected by the CCF[1:0] bits). The CPRL2 bit can be set to generate a reload on each capture edge.
MAXQ7667 User’s Guide 6.7.9.4 Measure Duty Cycle Repeatedly To measure the duty cycle of the signal seen on the T2P0 input pin, the Type 2 timer is configured for a single-shot delayed run with both edges defined for capture. The CPRL2 bits should be configured to 1 to request reloads on each edge. To prevent reloads on one of the edges, gating should be enabled. The T2POL0 bit specifies which edge starts/ends the capture cycle and which edge does not have a reload associated with it.
MAXQ7667 User’s Guide 6.7.9.5 Overflow/Interrupt on Cumulative Time To cause an overflow only when the T2P0 pin has been low for some cumulative duration, the Type 2 timer can be configured to the gated compare mode of operation with an initial starting value appropriate for the cumulative duration to be detected.
MAXQ7667 User’s Guide SECTION 7: SCHEDULE TIMER This section contains the following information: 7.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2 7.2 Schedule Timer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.2.1 Schedule Timer Control Register (SCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.2.
MAXQ7667 User’s Guide SECTION 7: SCHEDULE TIMER The MAXQ7667’s schedule timer is a much simpler implementation of the real-time clock module found in many MAXQ microcontrollers. The schedule timer provides a means for general timekeeping and software synchronization to the external I/O.
MAXQ7667 User’s Guide 7.2 Schedule Timer Register Descriptions 7.2.
MAXQ7667 User’s Guide 7.2.
MAXQ7667 User’s Guide 7.3 Schedule Timer Operation The MAXQ7667 has a schedule timer that can be used for general timekeeping and interval alarms and wake-up alarms. The timer is a 16-bit up-counter that is incremented by the system clock after the system clock has been divided by a prescaler. The counter value is read through the STIM register. Writing to the STIM register sets the counter to the written value.
MAXQ7667 User’s Guide SECTION 8: UART AND LIN This section contains the following information: 8.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 8.2 UART/LIN Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 8.3 UART and LIN Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide 8.4.5 LIN Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21 8.4.5.1 LIN Slave Setup Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21 8.4.5.2 LIN Slave Receiving Protected ID and Break/Sync Example . . . . . . . . . . . . . .8-21 8.4.5.3 LIN Slave Polling for Receive Complete Example . . . . . . . . . . . . . . . . . . . . . .8-22 8.4.5.
MAXQ7667 User’s Guide LIST OF FIGURES Figure 8-1. UART/LIN Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Figure 8-2. LIN Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18 Figure 8-3. LIN Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18 Figure 8-4. LIN Bus Master Communication . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 8: UART AND LIN The MAXQ7667 contains a standard UART for serial communication and dedicated hardware for support of the LIN bus. The dedicated LIN hardware simplifies the application code and requires less processor intervention. The MAXQ7667 can be configured to use either the UART or LIN. Both the UART and LIN require external bus transceivers to connect to the physical layer. 8.1 Architecture Figure 8-1 shows the various blocks that comprise the UART/LIN interface.
MAXQ7667 User’s Guide 8.3 UART and LIN Register Descriptions The following sections describe the MAXQ7667 registers that control the UART and LIN hardware. 8.3.1 Control Register 1 (UART) (CNT1) Attention: All the bits in this register should be written simultaneously in one write instruction.
MAXQ7667 User’s Guide Bit 5: Serial Port Mode Bit 2 (SM2). The function of this bit is dependent on the operating mode of the serial port. In mode 0, it determines the speed of the serial clock signal (either 1/4 or 1/12 the system clock rate). In mode 1, setting this bit to 1 disables the receive interrupt if an invalid stop bit is received. In modes 2 and 3, setting this bit to 1 prevents the receive interrupt from being set if the 9th received bit is a 0.
MAXQ7667 User’s Guide 8.3.3 Serial Port Buffer Register (SBUF) Serial Port Buffer Register SBUF Module 03h, Index 07h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name SBUF7 SBUF6 SBUF5 SBUF4 SBUF3 SBUF2 SBUF1 SBUF0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Note: SBUF is cleared to 00h on all forms of reset. Bits 7 to 0: Serial Port Buffer Register (SBUF[7:0]).
MAXQ7667 User’s Guide 8.3.5 Error Register (UART) (ERRR) Error Register ERRR Module 03h, Index 0Dh Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name — OTE DME CKE P1 P1E P0 P0E Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r r = read Note: ERRR is cleared to 00h on all forms of reset. Bit 7: Reserved. Read returns 0. Bit 6: Other Communications Error (OTE).
MAXQ7667 User’s Guide 8.3.
MAXQ7667 User’s Guide 8.3.7 Interrupt State Vector Register (ISVEC) Interrupt State Vector Register ISVEC Module 03h, Index 0Fh Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name — — — — ISVEC3 ISVEC2 ISVEC1 ISVEC0 Reset 0 0 0 0 1 1 1 1 Access r r r r r r r r r = read Note: ISVEC is cleared to 0Fh on all forms of reset. Bits 7 to 4: Reserved. Bits 3 to 0: Interrupt State Vector 3:0 (ISVEC[3:0]).
MAXQ7667 User’s Guide 8.3.8 Status Register 0 (UART) (STA0) Status Register 0 STA0 Module 03h, Index 11h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name — — — — — — INP BUSY Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r r = read Note: STA0 is cleared to 00h on all forms of reset. Bits 7 to 2: Reserved. Bit 1: Interrupt Pending (INP).
MAXQ7667 User’s Guide 8.3.10 FIFO Control Register (UART) (FCON) FIFO Control Register FCON Module 03h, Index 13h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name FTF FRF TXFT1 TXFT0 RXFT1 RXFT0 OE FEN Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Note: FCON is cleared to 00h on all forms of reset. Bit 7: Flush Transmit FIFO (FTF).
MAXQ7667 User’s Guide 8.3.11 Control Register 0 (UART) (CNT0) Control Register 0 CNT0 Module 03h, Index 14h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name WU FP1 FP0 INE AUT INIT LUN1 LUN0 Reset 1 0 0 0 1 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Note: CNT0 is cleared to 8Bh on all forms of reset. Bit 7: Wake Up (WU). This bit enables the host to monitor and control the low-power sleep mode status of the peripheral.
MAXQ7667 User’s Guide 8.3.12 Control Register 2 (UART) (CNT2) Control Register 2 CNT2 Module 03h, Index 15h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name — — — DMIS PM HDO FBS BTH Reset 0 0 0 0 0 0 0 0 Access r r rw rw rw rw rw rw r = read, w = write Note: CNT2 is cleared to 00h on all forms of reset. Bits 7 to 5: Reserved. Read returns 0. Bit 4: Data Mismatch Disable (DMIS).
MAXQ7667 User’s Guide 8.3.
MAXQ7667 User’s Guide 8.3.15 Serial Address Mask Register (UART) (SADEN) Serial Address Mask Register SADEN Module 03h, Index 18h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name SADEN7 SADEN6 SADEN5 SADEN4 SADEN3 SADEN2 SADEN1 SADEN0 Reset 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw r = read, w = write Note: SADEN is cleared to 00h on all forms of reset. Bits 7 to 0: Serial Address Mask Register 7:0 (SADEN[7:0]).
MAXQ7667 User’s Guide 8.3.
MAXQ7667 User’s Guide 8.4.2 LIN Frame The LIN protocol uses a single message frame to synchronize and address the nodes and to exchange data between them. The master sets the transmission speed and sends the message header shown in Figure 8-2. The header starts with the sync/break sequence followed by the sync field. The slave recognizes the sync/break and sets up to receive the sync field. Once the slave receives the sync field, it adjusts its internal baud rate to match the master.
MAXQ7667 User’s Guide 8.4.4 LIN Master The MAXQ7667 can be used as the LIN bus master as shown in Figure 8-4. As the LIN bus master node, the MAXQ7667 controls all traffic on the bus. The master sets the communication speed by sending the break and sync sequence. It also sends the identification field and checksum for specific slaves to respond to.
MAXQ7667 User’s Guide 8.4.4.2 LIN Master Sending Protected ID and Break/Sync Example The LIN master is now configured and ready to send the identifier and break/sync sequence to initiate communication. To have the master send the identifier and break/sync sequence, a write to SBUF and CNT2 is required as follows. • Load SBUF with the master protected identifier in the range 0x00–0x3F. • Set the FBS bit (CNT2.1) to 1 to transmit a break/sync.
MAXQ7667 User’s Guide 8.4.5 LIN Slave The MAXQ7667 can be used as a LIN slave as shown in Figure 8-5. As the LIN slave, the bus master controls all traffic on the bus. The slave must synchronize its baud rate to match the master and respond if the master’s identifier is within the slave’s address range. LIN BUS MASTER MAXQ7667 LIN BUS SLAVE WRITE MASTER TASK LIN BUS CAN BUS READ/WRITE SLAVE TASK READ/WRITE SLAVE TASK Figure 8-5. LIN Bus Slave Communication 8.4.5.
MAXQ7667 User’s Guide 8.4.5.3 LIN Slave Polling for Receive Complete Example One method to accomplish this is to use the LIN interrupts to monitor the LIN state in the ISVEC register similar to what the master does. Using the LIN interrupt handler, ISVEC state 2 indicates when the protected identifier has been successfully received in slave mode. • In the interrupt handler a flag (e.g., RX_OK = 1) is set for state 2. • Wait until RX_OK = 1 before proceeding.
MAXQ7667 User’s Guide 8.4.9 Setting LIN Baud Rate The LIN baud rate is set using the BT register. The LIN master uses the baud-rate bit timing when it issues a break/sync sequence. The LIN slave captures the sync timing and set its BT to match the master’s. To set the LIN baud rate the following formula is used: BT = System Clock/LIN Baud Rate For example, for the LIN baud rate of 20kBd, with a 16MHz crystal as the clock source.
MAXQ7667 User’s Guide 8.4.12 LIN Error Handling When the MAXQ7667 is used as a LIN master or slave, the application software should monitor the status of all LIN communication with the ISVEC and ERRR registers. In the previous master and slave sections, no provision was provided to check for errors. When the LIN controller communicates on the LIN bus, the ISVEC register should be monitored for error conditions and action should be taken to handle the error.
MAXQ7667 User’s Guide 8.5.2 MAXQ7667 UART Modes 8.5.2.1 UART Mode 0 This mode is used to communicate in synchronous, half-duplex format with devices that accept the MAXQ7667 microcontroller as a master. Figure 8-7 shows a functional diagram and basic timing of this mode. As can be seen, there is one bidirectional data line (Rx) and one shift clock line (Tx) used for communication.
MAXQ7667 User’s Guide SYSTEM CLOCK DIVIDE BY 12 0 URX PIN LATCH S0 D7 D6 D5 D4 D3 D2 D1 D0 LOAD CLOCK SBUF OUTPUT SHIFT REGISTER DIVIDE BY 4 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL LOAD SERIAL BUFFER TI FLAG = SCON.1 WR SERIAL I/O CONTROL RECEIVE BUFFER DATA CLOCK RI FLAG = SCON.
MAXQ7667 User’s Guide 1 START SYSTEM CLOCK D7 D6 D5 D4 D3 D2 D1 D0 LOAD CLOCK STOP SBUF TRANSMIT SHIFT REGISTER UTX PIN LATCH S0 0 DIVIDE BY 4 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL BUFFER SBUF RD WR RB8 = SCON.2 RI FLAG = SCON.0 SI CLOCK TI FLAG = SCON.
MAXQ7667 User’s Guide 8.5.2.3 UART Mode 2 This mode uses a total of 11 bits in asynchronous, full-duplex communication as illustrated in Figure 8-9. The 11 bits consist of one start bit (a logic 0), 8 data bits, a programmable 9th bit, and one stop bit (a logic 1). Like mode 1, the transmissions occur on the Tx signal pin and receptions on Rx. For transmission purposes, the 9th bit can be stuffed as logic 0 or 1. A common use is to put the parity bit in this location.
MAXQ7667 User’s Guide SYSTEM CLOCK/2 1 DIVIDE BY 2 0 SMOD START LOAD CLOCK STOP D8 D7 D6 D5 D4 D3 D2 D1 D0 SBUF TRANSMIT SHIFT REGISTER LATCH S0 UTX PIN 0 TB8 = SCON.3 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL BUFFER SBUF RD WR SI D7 D6 D5 D4 D3 D2 D1 D0 START RI FLAG = SCON.0 STOP D8 RB8 = SCON.2 CLOCK TI FLAG = SCON.
MAXQ7667 User’s Guide 1 DIVIDE BY 4 LATCH S0 UTX PIN 0 TB8 = SCON.3 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL BUFFER SBUF RD WR RB8 = SCON.2 RI FLAG = SCON.0 SI CLOCK TI FLAG = SCON.
MAXQ7667 User’s Guide 8.5.4 UART Mode 1 Asynchronous Full-Duplex Setup Example To set up the UART/LIN controller for UART operation, the LIN or UART mode select (LUN[1:0]) bits in CNT0 are set for UART mode. To set up the UART mode, set the registers as shown in the following example. In this example the UART is set for asynchronous communication using mode 1 with 115,200 baud. • Set LUN bits (CNT0.1:0) to 0 to select the UART mode. • Set FEDE bit (SMD.0) to 0 to disable the framing error detection.
MAXQ7667 User’s Guide 8.5.7 UART Receive Data Example To receive serial data using the UART, the SBUF register is read. To ensure the data has been written, the application code should examine the receive interrupt (RI) flag immediately before reading the SBUF register. The application code can wait until the data has been completely shifted in to the receive buffer and the RI flag is set indicating new data has been received.
MAXQ7667 User’s Guide SECTION 9: ENHANCED SERIAL PERIPHERAL INTERFACE (SPI) MODULE This section contains the following information: 9.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 9.1.1 SPI Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 9.1.1.1 SPI Data Buffer Register (SPIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide LIST OF FIGURES Figure 9-1. SPI Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 Figure 9-2. SPI Port Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 Figure 9-3. Master Mode Transfer Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12 Figure 9-4. Slave Mode Transfer Cycle Operation . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 9: ENHANCED SERIAL PERIPHERAL INTERFACE (SPI) MODULE The MAXQ7667 has a powerful hardware serial peripheral interface (SPI) module that allows for serial communication with a variety of external devices. The SPI port on the MAXQ is a fully independent module that can be accessed under program control. This module supports access to the full 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode.
MAXQ7667 User’s Guide 9.1 Architecture The MAXQ7667 contains a shift register, an independent read buffer, a programmable baud-rate generator, and numerous flags to control and check the status of the port through interrupts or in a polled fashion. The SPI port shift register handles both transmit and receive data transfers. The read path is double buffered to free up the shift register for the next SPI transfer.
MAXQ7667 User’s Guide The MAXQ7667 supports: • 8-bit or 16-bit character lengths • Master or slave mode • Four standard SPI clocking modes • Programmable master SPICK baud-rate generator • Configurable SS pin • MSB first data shifting • Mode-fault detection • Data overrun and collision detection • Interrupt or polled operation The MAXQ7667 does not support: • Free-running SPICK and frame sync transfer modes • LSB first shift Peripherals used should be compatible with the MAXQ7667-supported SPI modes.
MAXQ7667 User’s Guide 9.1.1.1 SPI Data Buffer Register (SPIB) The SPI data buffer register (SPIB) uses the SPI port shift register for write operations and a separate read buffer for read operations. Bit 15 is the MSB of the register and bit 0 is the LSB of the register. This register is word- or byte-access enabled and the data is shifted towards the MSB only. The port is double buffered on read and single buffered on write. See Figure 9-2.
MAXQ7667 User’s Guide 9.1.1.2 SPI Control Register (SPICN) The SPI control register (SPICN) contains both mode control and status flags to monitor the operation of the SPI port.
MAXQ7667 User’s Guide Bit 5: Receive Overrun Flag (ROVR). This flag detects if a received character was lost because a previous piece of data had not been read out of the SPIB register. The data in the SPI port shift register is overrun and lost. This bit is read- and write-access enabled and can be set by individual bit write operations. 0 = No receive overrun has occurred. 1 = Receive overrun occurred. Bit 4: Write Collision Flag (WCOL).
MAXQ7667 User’s Guide 9.1.1.3 SPI Configuration Register (SPICF) The SPI configuration register (SPICF) contains the port configuration selects. The SPI port supports 8-bit and 16-bit character transfers using the SS pin and an internal bit counter to control transfer completion. Data is shifted on the rising or falling edge of the SCLK as selected by the clock polarity select (CKPOL) and the clock phase select (CKPHA) bits found in the SPICF. These registers can be word, byte, or bit accessed.
MAXQ7667 User’s Guide Bit 1: Clock Phase Select (CKPHA). This bit selects the clock phase and is used with the CKPOL bit to define the SPI data transfer format. 0 = Data sampled on the active clock edge. 1 = Data sampled on the inactive clock edge. Bit 0: Clock Polarity Select (CKPOL). This bit selects the clock polarity and is used with the CKPHA bit to define the SPI data transfer format. 0 = Clock idles in the logic 0 state (rising = active clock edge).
MAXQ7667 User’s Guide 9.1.2 Master Mode The master mode selection enables the MAXQ7667 to control transfer cycles on the SPI bus. An SPI master device drives the SCLK and the SS pins on the SPI bus. Transfers are initiated when firmware writes a character to the SPIB. The CHR bit selects between 8bit or 16-bit transfer cycles. Data is shifted out serially, with MSB first on the MOSI pin using the SCLK as the shift clock.
MAXQ7667 User’s Guide Data can be written to the serial register once the STBY flag is cleared and the SPIC flag is set. This allows the next transfer to begin while the read operation is pending. In this overlapped mode, the read buffer must be emptied before the next character is completely loaded into the shift register. Should the next transfer cycle complete, the ROVR flag is set if the SPIB contents have not been read.
MAXQ7667 User’s Guide 9.1.3 Slave Mode The MAXQ7667’s SPI port can also be configured as an SPI slave device. This is achieved by enabling the SPI port (SPIEN) with MSTM = 0. The SCLK and SS lines are then driven by the SPI bus master. Any master device driving the SCLK on the MAXQ7667 SPI port should limit the maximum shift rate to one-eighth the MAXQ SYSCLK rate.
MAXQ7667 User’s Guide Once the port is configured as an SPI bus slave, either polling or interrupts can be used to monitor the progress of the transfer cycle. The STBY flag is set once a transfer cycle is initiated from the SPI master to the slave device. Once the transfer cycle is complete, the SPIC flag is set and data should be read from the SPIB. 1) Poll SPIC or use interrupts to monitor the status of the transfer cycle. 2) Check to see the cause of the interrupt if interrupts used.
MAXQ7667 User’s Guide When CKPHA is cleared (0), SS must be cycled to mark the beginning of each transfer cycle. When CKPHA is set (1), SS can remain low between successive transfer cycles. The MAXQ7667’s flexible clocking schemes allow peripheral devices with different transfer formats to communicate with each other, however, the clock polarity and clock phase must be consistent for the master and selected slave device. 9.1.
MAXQ7667 User’s Guide 9.2.2 Write Collision Flag (WCOL) A write collision occurs if a write to the SPIB data register is attempted during a transfer cycle. The MAXQ7667’s write path is a singlebuffered path with the shift register acting as both the write buffer and shift register. If the STBY flag is set (1), this marks that a transfer cycle is in progress. Any writes to the SPIB with STBY set are blocked to maintain the integrity of the shift register contents.
MAXQ7667 User’s Guide 9.4 Resetting the SPI Port Any system reset completely resets the SPI. Partial resets occur whenever the SPI-enable bit (SPIE) is cleared. Whenever SPIE is cleared, the following occurs: • Any transmission currently in progress is aborted. • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new transmission. • All the SPI port logic is defaulted back to being general-purpose I/O pins.
MAXQ7667 User’s Guide SECTION 10: HARDWARE MULTIPLIER MODULE This section contains the following information: 10.1 Hardware Multiplier Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 10.2 Hardware Multiplier Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2.1 Hardware Multiplier Control Register (MCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2.
MAXQ7667 User’s Guide SECTION 10: HARDWARE MULTIPLIER MODULE The MAXQ7667 microcontroller includes a hardware multiplier module to support high-speed multiplications. The hardware multiplier module is equipped with two 16-bit operand registers, a 32-bit read-only result register, and an accumulator of 48-bit width. The multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle.
MAXQ7667 User’s Guide 10.2 Hardware Multiplier Peripheral Registers 10.2.
MAXQ7667 User’s Guide Bit 3: Operand Count Select (OPCS). This bit defines how many operands must be loaded to trigger a multiply or multiply-accumulate/subtract operation (except when SQU = 1 since this implicitly specifies a single operand). When this bit is cleared to logic 0, both operands (MA and MB) must be written to trigger the operation. When this bit is set to 1, the specified operation is triggered once either operand is written.
MAXQ7667 User’s Guide 10.2.
MAXQ7667 User’s Guide 10.2.
MAXQ7667 User’s Guide 10.2.
MAXQ7667 User’s Guide 10.3 Hardware Multiplier Controls The selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register: SUS, MSUB, MMAC, and SQU. The number of operands that must be loaded to trigger the specified operation is dictated by the OPCS bit setting, except when the square function is enabled (SQU = 1).
MAXQ7667 User’s Guide 10.8 Accessing the Multiplier There are no restrictions on how quickly data is entered into the operand registers or on the order of data entry. The only requirement to do a calculation is to perform the loading of MA and/or MB registers having specified data type and operation in the MCNT register. The multiplier keeps track of the writes to the MA and MB registers, and starts calculation immediately after the prescribed number of operands is loaded.
MAXQ7667 User’s Guide 10.9 MAXQ7667 Hardware Multiplier Examples The following are code examples of multiplier operations.
MAXQ7667 User’s Guide SECTION 11: TEST ACCESS PORT (TAP) This section contains the following information: 11.1 TAP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2 11.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2 11.2.1 TAP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide NOTE: BOUNDARY SCAN IS NOT AVAILABLE IN THE MAXQ7667. SECTION 11: TEST ACCESS PORT (TAP) Note: This section is only relevant to those users who plan to make their own debugging and programming tools through JTAG; most users can skip this section. Refer to Section 12 and Section 13 for JTAG in-circuit debug mode and in-system programming/bootloader. 11.
MAXQ7667 User’s Guide READ TO DEBUG ENGINE SHADOW REGISTER WRITE DEBUG REGISTER 7 DR-SCAN SEQUENCE DVDDIO 6 5 4 3 2 1 0 s1 s0 SYSTEM PROGRAMMING REGISTER 2 1 0 DVDDIO BYPASS P1.2/TDI P1.0/TDO IR-SCAN SEQUENCE DVDDIO DVDDIO 3-BIT INSTRUCTION SHIFT REGISTER P1.1/TMS 2 1 0 PARALLEL INSTRUCTION REGISTER P1.3/TCK TAP CONTROLLER POWER-ON RESET 2 1 0 IR[2:0] UPDATE-DR UPDATE-DR Figure 11-1. Simplified MAXQ7667 TAP and TAP Controller 11.2.
MAXQ7667 User’s Guide 11.3 TAP Interface Control Once an application has been loaded and starts running, the MAXQ7667 JTAG TAP interface can be controlled by the TAP bit in the system control register as described in Section 11.3.1. 11.3.
MAXQ7667 User’s Guide 11.4 TAP Controller Operation The MAXQ7667 TAP controller is formed by a finite state machine that provides 16 operational states for access control. The TAP state control is achieved through host manipulation of the TMS and TCK signals. The TMS signal is sampled at the rising edge of TCK and decoded by the TAP controller to control movement between the TAP states. The TDI input and TDO output are meaningful once the TAP is in a serial shift state.
MAXQ7667 User’s Guide 11.4.1 Communication via TAP The TAP controller is in test-logic-reset state after a power-on-reset. During this initial state, the instruction register contains bypass instruction and the serial path defined between the TDI and TDO pins for the shift-DR state is the 1-bit bypass register. All TAP signals (TCK, TMS, TDI, and TDO) default to being weakly pulled high internally on any reset. The TAP controller remains in the test-logic-reset state as long as TMS is held high.
MAXQ7667 User’s Guide When the parallel instruction register (IR[2:0]) is updated, the TAP controller decodes the instruction and performs any necessary operations, including activation of the data shift register to be used for the particular instruction during data register shift sequences (DRscan). The length of the activated shift register depends upon the value loaded to the instruction register (IR[2:0]).
MAXQ7667 User’s Guide 11.4.6 TAP Communication Examples—IR-Scans and DR-Scans Figures 11-3 and 11-4 illustrate examples of communication between the host JTAG controller and the TAP of the MAXQ7667. The host controls the TCK and TMS signals to move through the desired TAP states while accessing the selected shift register through the TDI input and TDO output pair.
MAXQ7667 User’s Guide TCK TMS TDI SHIFT REGISTER PARALLEL OUTPUT DON'T CARE OR UNDEFINED DON'T CARE OR UNDEFINED NEW DATA OLD DATA INSTRUCTION REGISTER DATA REGISTER DON'T CARE OR UNDEFINED TDO ENABLE TDO Figure 11-4.
MAXQ7667 User’s Guide SECTION 12: IN-CIRCUIT DEBUG MODE This section contains the following information: 12.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3 12.2 In-Circuit Debug Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4 12.2.1 In-Circuit Debug Temporary 0 Register (ICDT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4 12.2.
MAXQ7667 User’s Guide LIST OF FIGURES Figure 12-1. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3 Figure 12-2. Data Transmit and Receive During DR-Scan Sequence . . . . . . . . . . . . . . . . . . . . . .12-10 LIST OF TABLES Table 12-1. Background Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-11 Table 12-2. Background Mode Debug Commands . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 12: IN-CIRCUIT DEBUG MODE Note: This section is only relevant to users who are planning to make their own debugging tools, hence this section can be skipped by most users. However, those users intending to implement in-system programming (see Section 13) should read this section. The MAXQ7667 is equipped with embedded debug hardware and embedded ROM firmware developed for the purpose of providing in-circuit debugging capability to the user application.
MAXQ7667 User’s Guide The debug engine is supported by five functional registers: • ICDB: The ICDB register is an 8-bit data register that supports exchanging command/data between the host system and the incircuit debugger. The register functions as an 8-bit parallel buffer for the debug shift register in the TAP. The ICDB register is mapped to the peripheral register space and is read/write accessible by the CPU and the debug engine.
MAXQ7667 User’s Guide 12.2.2 In-Circuit Debug Temporary 1 Register (ICDT1) The ICDT1 register is read/write accessible by the CPU only in background mode or debug mode. This register is intended for use by the utility ROM routines as temporary storage to save registers that might otherwise have to be placed in the stack. This register is cleared after a power-on reset or by a test-logic-reset TAP state.
MAXQ7667 User’s Guide Bit 5: Break-On Register Enable (REGE). The REGE bit is used to enable the break-on register function. When the REGE bit is set to 1, BP4 and BP5 are used as register breakpoints. A break occurs when the content of BP4 is matched with the destination address of the current instruction. For BP5, a break occurs only on a selected data pattern for a selected destination register addressed by BP5. The data pattern is determined by the contents in the ICDA and ICDD register.
MAXQ7667 User’s Guide 12.2.4 In-Circuit Debug Flag Register (ICDF) In-Circuit Debug Flag Register ICDF Module 02h, Index 1Bh Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name — — — — PSS1 PSS0 SPE TXC Reset 0 0 0 0 0 0 0 0 Access r r r r rw rw rw rw r = read, w = write Bits 7 to 4: Reserved. Read 0, write ignored. Bits 3 and 2: Programming Source Select Bits 1 and 0 (PSS[1:0]). See Section 13 for information on these bits.
MAXQ7667 User’s Guide 12.2.6 In-Circuit Debug Address Register (ICDA) The debug engine uses the ICDA register to store addresses so that ROM code may view that information. This register is also used by the debug engine as a mask register to mask out don’t care bits in the ICDD register when BP5 is used as a register breakpoint.
MAXQ7667 User’s Guide 12.2.8 System Control Register (SC) System Control Register SC Module 08h, Index 08h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name TAP — CDA1 CDA0 UPA ROD PWL — Reset 0 0 0 0 0 0 1 0 Access rw r rw rw rw rw rw r r = read, w = write *This register defaults to 80h on all forms of reset except after power-on reset. After power-on reset, the PWL bit is also set and this register defaults to 82h.
MAXQ7667 User’s Guide 12.3 Debug Engine Operation To enable a communication link between the host and the MAXQ7667 debug engine, the debug instruction (010b) must be loaded into the TAP instruction register using the IR-scan sequence (see Section 11). Once the instruction is latched in the instruction parallel buffer (IR[2:0]) and is recognized by the TAP controller in the update-IR state, the 10-bit data shift register is activated as the communication channel for DR-scan sequences.
MAXQ7667 User’s Guide Table 12-1 shows the background mode commands supported by the MAXQ7667. Encodings (op code) not listed in this table are not supported in background mode and are treated as no operations. A command can consist of multiple-byte transactions between the external host and the debug engine via the TAP. However, a command code is always 8 bits and is always transmitted first, followed by address and/or data when needed. Table 12-1.
MAXQ7667 User’s Guide 12.3.2 Breakpoint Registers The MAXQ7667 incorporates six host-configurable breakpoint registers (BP0–BP5) for establishing different types of breakpoint mechanisms. The first four breakpoint registers (BP0–BP3) are 16-bit registers that are configurable as program memory address breakpoints. When enabled, the debug engine forces a break when a match between the breakpoint register and the program memory execution address occurs.
MAXQ7667 User’s Guide 12.3.2.2 Breakpoint Register 4 (BP4) Breakpoint Register 4 BP4 Register Description: Register Name: This register is accessible only via background mode read/write commands. When (REGE = 0): This register serves as one of the two data memory address breakpoints. When DME is set in background mode, the debug engine monitors the data memory address bus activity while the CPU is executing the user program.
MAXQ7667 User’s Guide 12.3.2.3 Breakpoint Register 5 (BP5) This register is accessible only through background mode read/write commands. When (REGE = 0): This register serves as one of the two data memory address breakpoints. When DME is set in background mode, the debug engine monitors the data memory address bus activity while the CPU is executing the user program. If an address match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
MAXQ7667 User’s Guide 12.3.4 Debug Mode There are two ways to enter debug mode from background mode: 1) issuance of the debug command directly by the host through the TAP communication port, or 2) the breakpoint matching mechanism. The host can issue the debug background command to the debug engine. The response time varies dependent on system conditions when the command is issued.
MAXQ7667 User’s Guide Internally, the ROM can ascertain when new data is available or when it can output the next data byte via the TXC flag. The TXC flag is an important indicator between the debug engine and the utility ROM debug routines. The utility ROM firmware sets the TXC flag to 1 to indicate that valid data has been loaded to the ICDB register.
MAXQ7667 User’s Guide 12.3.6 Read-Register Map Command Host-ROM Instruction A read-register map command reads out data contents for all implemented system and peripheral registers. The host does not specify a target register but instead should expect register data output in successive order, starting with the lowest order register in register module 0. Data is loaded by the ROM to the 8-bit ICDB register and is output one byte per transfer cycle.
MAXQ7667 User’s Guide 12.3.9 Debug Mode Special Considerations The following are special considerations when using debug mode. The debug engine cannot be operated reliably when the CPU is configured in the power management mode (divide-by-256 system clock mode). To allow for proper execution of debug mode commands when invoked during PMM, the switchback enable (SWB) bit should be configured to logic 1.
MAXQ7667 User’s Guide 12.3.10 Debug Command Operation The following sections provide specific notes on the MAXQ7667’s operation in debugging mode. 12.3.10.1 Register Read and Write Commands Any register location can be read or written using these commands, including reserved locations and those used for op code support. No protection is provided by the debugging interface, and avoiding side effects is the responsibility of the host system communicating with the MAXQ7667.
MAXQ7667 User’s Guide Table 12-3.
MAXQ7667 User’s Guide SECTION 13: IN-SYSTEM PROGRAMMING/BOOTLOADER This section contains the following information: 13.1 Bootstrap-Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2 13.2 In-System Programming Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.2.1 In-Circuit Debug Flag Register (ICDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.2.
MAXQ7667 User’s Guide SECTION 13: IN-SYSTEM PROGRAMMING/BOOTLOADER Note: The reader should be familiar with Section 11: Test Access Port (TAP) and Section 12: In-Circuit Debug Mode before reading this section. The MAXQ7667 is equipped with a bootstrap loader as part of the utility ROM firmware. The main function of the bootstrap loader is to provide in-system programming capability to the user application.
MAXQ7667 User’s Guide 13.2 In-System Programming Peripheral Registers The MAXQ7667 in-system programming peripheral registers are described here. It is also possible for the MAXQ7667 to bootstrap itself into in-system programming mode by setting the proper bits in the in-circuit debug flag register (ICDF) and invoking a reset. The procedure for invoking in-system programming in this manner must be defined and supported by the application firmware as discussed in Section 13.5 and Section 13.6. 13.2.
MAXQ7667 User’s Guide 13.2.2 System Control Register (SC) System Control Register SC Module 08h, Index 08h Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name TAP — CDA1 CDA0 UPA ROD PWL — Reset 1 0 0 0 0 0 1* 0 Access rw r rw rw rw rw rw r r = read, w = write *This register defaults to 80h on all forms of reset except after power-on reset. After power-on resert, the PWL bit is also set and this register defaults to 82h.
MAXQ7667 User’s Guide Table 13-2. Bootloader Status Codes STATUS VALUE FUNCTION 00 No Error. The last command completed successfully. 01 Family Not Supported. An attempt was made to use a command from a family the bootloader does not support. 02 Invalid Command. An attempt was made to use a nonexistent command within a supported command family. 03 No Password Match. An attempt was made to use a password-protected command without first matching a valid password.
MAXQ7667 User’s Guide Command 04h—Get Status The status code returned by this command is defined in Table 13-2. The flags byte contains the following bit status flags. I/O Byte 1 Input 04h Output Flags Byte 2 Status Code Table 13-3. Bootloader Status Flags FLAG BIT FUNCTION 0 Password Lock 0 = The password is unlocked or had a default value; password-protected commands can be used. 1 = The password is locked. Password-protected commands cannot be used.
MAXQ7667 User’s Guide Command 08h—Get Loader Version I/O Byte 1 Input 08h Output VersionL Byte 2 VersionH Command 09h—Get Utility ROM Version I/O Byte 1 Input 09h Output VersionL Byte 2 VersionH Command 0Ah—Set Word/Byte Mode Access The mode byte should be 0 to set byte access mode or 1 to set word access mode. The current access mode is returned in the status flag byte by command 04h, as well as a flag to indicate whether word access mode is supported by this particular bootloader.
MAXQ7667 User’s Guide 13.3.3 Family 2 Commands: Dump Variable Length (Password Protected) Command 20h—Dump Code Variable Length This command has a slightly different format depending on the length of the dump requested. It returns the contents of the application flash/ROM—(LengthL) or (LengthH:LengthL) bytes/words starting at (AddressH:AddressL).
MAXQ7667 User’s Guide 13.3.5 Family 4 Commands: Verify Variable Length (Password Protected) Command 40h—Verify Code Variable Length This command operates in the same manner as the “Load Code Variable Length” command, except that instead of programming the input data into code flash, it verifies that the input data matches the data already in code space. If the data does not match, the status code is set to reflect this failure.
MAXQ7667 User’s Guide 13.3.8 Family E Commands: Erase Fixed Length (Password Protected) Command E0h—Erase Code Fixed Length This command erases (programs to FFFFh) a 64-byte block of the program flash memory. The address given should be located in the block to be erased. I/O Byte 1 Byte 2 Byte 3 Byte 4 Input E0h 0 AddressL AddressH Output Command E1h—Erase Data Fixed Length This command erases a single word/byte in data RAM to zero at (AddressH:AddressL) to zero.
MAXQ7667 User’s Guide 13.4 Password-Protected Access Some applications require preventive measures to protect against simple access and viewing of program code memory. To address this need for code protection, the MAXQ7667 utility ROM that manages in-system programming, in-application programming, or in-circuit debugging grants full access to those utilities only after a password has been supplied. The password is defined as the 16 words (32 bytes) of physical program memory at addresses 0x0010 to 0x001Fh.
MAXQ7667 User’s Guide • SPB.2 and SPB.1: Programming Source Select (PSS[1:0]). These bits allow the host to select programming interface sources. PSS[1:0] = 00 for JTAG; PSS[1:0] = 01 for UART. The DR-scan sequence is used to configure the SPB bits. The data content of the SPB register is reflected in the ICDF register and allows read/write access by the CPU. These bits are cleared by power-on reset or test-logic-reset of the TAP controller.
MAXQ7667 User’s Guide 13.6 UART Bootloader Operation The host computer can request the application program to jump to the the utility ROM bootloader to access the bootloader function through the UART serial port. Figure 13-1 shows the steps for the MAXQ7667 to evoke the bootloader through the UART. . . .
MAXQ7667 User’s Guide START SET UART FOR MODE 1 TRANSMIT 0Dh LISTEN A WHILE AUTOBAUD: BAUD-RATE DETECTION NO 3Eh RECEIVED? YES TRANSMIT 02h (ERASE FLASH AND RAM) NO 3Eh RECEIVED? YES TRANSMIT 10h LENGTH w_addr_l w_addr_h byte_1 byte_2 . . . byte_length 10h IS THE LOAD CODE COMMAND. LENGTH IS THE NUMBER OF BYTES OF CODE TO BE UPLOADED. w_addr_l IS THE LOWER HALF OF THE 32-BIT ADDRESS WHERE LOADING OF THE CODE IS TO START.
MAXQ7667 User’s Guide SECTION 14: SAR ADC MODULE This section contains the following information: 14.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3 14.2 SAR ADC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4 14.3 SAR ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide LIST OF FIGURES Figure 14-1. SAR ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3 Figure 14-2. Equivalent Input Circuit (Track/Acquisition Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .14-11 Figure 14-3. Equivalent Input Circuit (Hold/Conversion Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .14-11 Figure 14-4. Unipolar Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 14: SAR ADC MODULE The MAXQ7667 incorporates a 12-bit SAR ADC with built-in sample-and-hold and a conversion rate up to 125ksps. The ADC allows general-purpose measurements for temperature, supply voltage, diagnostics, or other parameters. Some of the features include the following: • Low-power, 125ksps, SAR (successive approximation) ADC, available as 12 bits. • ADC can measure up to five external, single-ended signals or two differential signals.
MAXQ7667 User’s Guide The ADC gets the reference from three sources: external source REF, internal buffered-bandgap reference that provides 2.5V, and AVDD. The internal bandgap and reference buffer can be individually disabled, allowing external reference(s) to drive any of these nodes. All are disabled at power-on to avoid contention if external reference(s) are used.
MAXQ7667 User’s Guide 14.3 SAR ADC Registers 14.3.
MAXQ7667 User’s Guide Bit 3: SAR ADC Start/Busy (SARBY). Setting this bit to 1 starts a conversion if SARS = 111. Reading from this bit reflects the busy status of the SAR ADC. Changing SARBY from 1 to 0 by software is blocked by hardware. Bits 2 to 0: SAR ADC Conversion Control Source Select (SARS[2:0]). These bits select the source that initiates SAR ADC conversions.
MAXQ7667 User’s Guide 14.3.
MAXQ7667 User’s Guide 14.3.
MAXQ7667 User’s Guide 10 divides by 8 11 divides by 16 Note that the SAR ADC accuracy is not guaranteed for SAR ADC clock frequencies exceeding 2MHz. This divider should be selected with regard to the source clock frequency to ensure this restriction is met. Bit 1: Crystal Enable (XTE). See Section 15 for details on this bit. Bit 0: RC Oscillator Enable (RCE). See Section 15 for details on this bit. 14.3.
MAXQ7667 User’s Guide 14.4 Voltage References The voltage reference for the SAR ADC can either be an internal bandgap reference or an external reference. The internal, 2.5V bandgap reference can be activated by setting the BGE bit (APE.12) and the RBUFE bit (APE.14) to 1. The BGE bit enables the bandgap reference, while the RBUFE bit (APE.14) enables the buffer at the output of the bandgap. A bypass capacitor of 0.47µF should be placed between REFBG and AGND pin.
MAXQ7667 User’s Guide CAPACITIVE DAC AVDD CIN+ RIN+ AIN+ COMP CIN- CONTROL LOGIC RIN- AIN- AGND Figure 14-2. Equivalent Input Circuit (Track/Acquisition Mode) CAPACITIVE DAC AVDD CIN+ RIN+ AIN+ COMP CIN- CONTROL LOGIC RIN- AIN- AGND Figure 14-3. Equivalent Input Circuit (Hold/Conversion Mode) 14.5.
MAXQ7667 User’s Guide 14.5.4 Transfer Function The MAXQ7667 ADC output is straight binary in unipolar mode. Figure 14-4 shows the MAXQ7667 ADC unipolar transfer function. Table 14-2 shows the unipolar relationship between the differential analog input voltage and the digital output code. Table 14-2. Unipolar Code Table BINARY DIGITAL OUTPUT CODE D11–D0 HEXADECIMAL EQUIVALENT OF D11–D0 DECIMAL EQUIVALENT OF D11–D0 (CODE12) DIFFERENTIAL INPUT VOLTAGE (V) (EXTERNAL, REF = 2.
MAXQ7667 User’s Guide The MAXQ7667 ADC output is two’s complement in bipolar mode. Figure 14-5 shows the MAXQ7667 ADC bipolar transfer function. Table 14-3 shows the bipolar relationship between the differential analog input voltage and the digital output code. In bipolar mode, the inputs are measured in a truly differential fashion where either input can exceed the other by up to REF/2. Table 14-3.
MAXQ7667 User’s Guide 14.5.5 Analog Input Protection Internal ESD protection diodes limit all analog inputs to AVDD and AGND, allowing the inputs to swing from (AGND - 0.3V) to (AVDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs should not exceed AVDD by more than +50mV or be lower than AGND by -50mV. Input voltages beyond AGND - 0.3V and AVDD + 0.3V forward bias the internal protection diodes.
MAXQ7667 User’s Guide 14.5.7 Auto Shutdown Mode Power consumption is reduced significantly by placing the MAXQ7667 ADC in auto shutdown mode after a conversion. Auto shutdown is ideal for infrequent data sampling and fast wake-up time applications. Auto shutdown is controlled by the SARASD bit (SARC.4). If the SARASD bit is set, the ADC automatically shuts down when the ADC data ready (SARRDY) bit in the ASR register is set at the end of a conversion.
MAXQ7667 User’s Guide Table 14-5. ADC Dual- and Single-Edge Modes ADC DUALMODE (SARDUL) ADC CONVERSION SOURCE (SARS[2:0]) ADC CONVERSION TRIGGER ADC CONVERSION DESCRIPTION 000 (Timer 0) 001 (Timer 1) 010 (Timer 2) 100 (ADCCTL) Rising Edge of Conversion Source • Sets T/H into track (acquisition) mode. • Track duration is under user control. • If ADC is in auto shutdown, a minimum of 2.5µs (1µs for power-up and 1.5µs for acquisition) is required. • If ADC is not in auto shutdown, a minimum of 1.
MAXQ7667 User’s Guide Table 14-5. ADC Dual- and Single-Edge Modes (continued) ADC DUALMODE (SARDUL) ADC CONVERSION SOURCE (SARS[2:0]) 110 (Continuous) ADC CONVERSION TRIGGER Write 110 to SARS[2:0] • If in auto shutdown, logic requires 8 cycles to power up. • Sets T/H into track mode. • ADC control logic provides the required track duration. • T/H placed in hold after 3 clock cycles. • Then SAR conversion executes (13 ADC clock cycles). Conversion continuously repeated every 16 ADC clock cycles.
MAXQ7667 User’s Guide ADC_CNVST ACQUISITION (n) CONVERSION (n) ADCCLK 17 13 1 ADCDATA DATA (n-1) DATA (n) SARBY Figure 14-9. Single-Edge ADC Conversion Timing; ADC Previously On POWER-UP AND ACQUISITION ADC_CNVST CONVERSION (n) ADCCLK 13 1 ADCDATA DATA (n-1) DATA (n) SARBY Figure 14-10. Dual-Edge ADC Conversion Timing; ADC Previously Off In dual-edged conversions, it is up to the user to provide the required power-up and acquisition delay as explained in Table 14-5.
MAXQ7667 User’s Guide 14.5.9 ADC Interrupts The MAXQ7667 ADC can generate an interrupt when ADC data is ready. The ADC data ready interrupt is generated when the conversion on a channel is complete and a 12-bit result is written into the SARD register. The SAR ADC data ready (SARRDY) flag in the ASR register (ASR.0) is also set when a conversion is complete. The SARIE bit in the AIE register (AIE.0) must be set for the interrupt to be generated.
MAXQ7667 User’s Guide SELECT ADC CLOCK DIVIDE SARCD[1:0] RATIO IN THE OSCC REGISTER. SELECT IN ADC POWER ENABLE REGISTER (APE): A) SET SARE (APE.4) TO ENABLE ADC. B) IF INTERNAL BANDGAP REFERENCE IS DESIRED, SET BGE (APE.12). C) SET RBUFE (APE.14) TO ENABLE ADC REFERENCE BUFFER. TO GET ADC DATA READY INTERRUPT AFTER A CONVERSION, SET SARIE (AIE.0) BIT IN ANALOG INTERRUPT ENABLE REGISTER. ALSO, ENABLE MODULE AND GLOBAL INTERRUPT CONTROL BITS IM5 IN IMR AND IGE IN IC PERIPHERAL REGISTER.
MAXQ7667 User’s Guide SECTION 15: OSCILLATOR/CLOCK GENERATION This section contains the following information: 15.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-2 15.2 Oscillator/Clock Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-2 15.2.1 Analog Interrupt Enable Register (AIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-4 15.2.
MAXQ7667 User’s Guide SECTION 15: OSCILLATOR/CLOCK GENERATION The MAXQ7667 oscillator/clock generation module is the clock generator that supplies the system clock for the microcontroller core and all the peripheral modules. The oscillator is designed to allow flexibility for selecting a timing source for the MAXQ7667 microcontroller. The MAXQ7667 clock source can be derived from the following: • Internal RC oscillator with a maximum of 16MHz frequency (factory default setting is 13.
MAXQ7667 User’s Guide DVDD POWER-ON RESET RESET WDCN.3:WDIF WATCHDOG INTERRUPT FLAG WDCN.2:WTRF WATCHDOG TIMER RESET FLAG WATCHDOG TIMER OSCC.1:XTE CKCN.7:XTRC CKCN.4:STOP WDCN.6:EWDI WDCN.5:WD1 WDCN.4:WD0 WDCN.1:EWT WDCN.0:RWT AIE.7:XTIE XTAL/CLOCK FAILURE INTERRUPT XIN CLOCK/XTAL OSCILLATOR ASR.7:XTI 0 XOUT CLOCK DIVIDE SYSCLK 1 ASR.8:XTRDY RCTRM WDCN.1:EWT CKCN.2:PMME = 0 CKCN.1:CD1 = 0 CKCN.0:CD0 = 0 CKCN.5:RCMD RC OSCILLATOR CKCN.4:STOP OSCC.0:RCE ADC CLOCK PRESCALE CKCN.7:XTRC ASR.
MAXQ7667 User’s Guide 15.2.
MAXQ7667 User’s Guide 15.2.
MAXQ7667 User’s Guide 15.2.3 Oscillator Control Register (OSCC) Oscillator Control Register OSCC Module 05h, Index 0Bh Register Description: Register Name: Register Address: Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name — — — — SARCD1 SARCD0 XTE RCE Reset 0 0 0 0 0 0 0 1 Access r r r r r r r r r = read.
MAXQ7667 User’s Guide Changing XTRC from 1 to 0 selects the internal RC oscillator as the system clock source. If the RC oscillator is already turned on, then the switch to the RC clock is instantaneous. If the RC oscillator is turned off, then it takes four RC clock periods to turn on the oscillator and make the switch. Bit 6: Reserved. Read returns 0. Bit 5: RC Oscillator Mode (RCMD). This read-only bit reflects the selection of clock source.
MAXQ7667 User’s Guide 15.2.5 Watchdog Timer Control Register (WDCN) Watchdog Timer Control Register WDCN Module 08h, Index 0Fh Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name POR EWDI WD1 WD0 WDIF WTRF EWT RWT Reset 0 0 0 0 0 0 0 0 Access r rw rw rw r r rw rw r = read, w = write Note 1: The watchdog timer always uses the RC oscillator as the clock source. Note 2: Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset.
MAXQ7667 User’s Guide 15.2.6 RC Oscillator Trim Register (RCTRM) RC Oscillator Trim Register RCTRM Module 01h, Index 17h Register Description: Register Name: Register Address: Bit # 15 14 13 12 11 10 9 8 Name — — — — — — — — Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r Bit # 7 6 5 4 3 2 1 0 Name RCTRM7 RCTRM6 RCTRM5 RCTRM4 RCTRM3 RCTRM2 RCTRM1 RCTRM0 Reset 0 0 0 0 0 0 0 0 Access r r r r r r r r r = read (Writeable only when TME = 1).
MAXQ7667 User’s Guide 15.3.1.1 Recalibrating the RC Oscillator The MAXQ7667 has an internal RC oscillator that is factory calibrated to approximately 13.5MHz. Although the oscillator is factory calibrated, its frequency drifts with temperature and supply voltage. If precision timing is required, the MAXQ7667’s precision crystal-controlled oscillator must be used, or the RC oscillator must be recalibrated to account for any frequency drift.
MAXQ7667 User’s Guide 15.3.2 External Oscillator and Crystal The external clock source can be an external oscillator, a quartz crystal, or ceramic resonator. The core is designed to work at a maximum frequency of 16MHz. If an external oscillator is used, it can be connected to XIN (pin 20), and XOUT (pin 21) can be left floating. However, a crystal should be connected from XIN to XOUT. (Refer to the crystal manufacturer’s data sheet for more details.
MAXQ7667 User’s Guide 15.4 External Oscillator Clock/Crystal Failure Switchover The external oscillator clock/crystal failure can occur during normal operation and is detected when the XTRDY bit switches over to 0, indicating that the external source has failed. The hardware forces a switch to the internal RC oscillator to keep the MAXQ7667 processor operational.
MAXQ7667 User’s Guide As shown in Figure 15-2, the timer is driven by the internal RC clock (set at the maximum 16MHz frequency) through a series of dividers. The divider output is selectable and determines the interval between timeouts. When the watchdog interrupt timeout is reached, the interrupt flag WDIF (WDCN.3) is set and generates an interrupt if the interrupt enable bit EWDI (WDCN.6) bit is set. Typically, after the WDIF gets set the user code resets the watchdog timer RWT (WDCN.0).
MAXQ7667 User’s Guide 15.6.2 Switchback Mode The system clock is used to provide standard baud-rate generation for the external interface. However, the clock speed choice affects all functional logic including timers and the baud-rate generator in the serial port module. The switchback feature allows low-power operation and quick response to events that require full processing capacity. The switchback function is enabled by setting the SWB bit to logic 1.
MAXQ7667 User’s Guide SECTION 16: POWER-SUPPLY/SUPERVISORY MONITORING This section contains the following information: 16.1 Power-Supply/Supervisory Module Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3 16.2 Power-Supply/Supervisory Monitoring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-5 16.2.1 Analog Interrupt Enable Register (AIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-5 16.2.
MAXQ7667 User’s Guide LIST OF FIGURES Figure 16-1. MAXQ7667 Power-Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-4 Figure 16-2. Supply Configuration Using All External Power Supply . . . . . . . . . . . . . . . . . . . . . .16-9 Figure 16-3. Supply Configuration Using External Power Supply and Internal Regulators . . . . .16-9 Figure 16-4. DVDDIO Using a Depletion Mode Pass Transistor . . . . . . . . . . . . . . . . . . . . . . . . . .16-10 Figure 16-5.
MAXQ7667 User’s Guide SECTION 16: POWER-SUPPLY/SUPERVISORY MONITORING The MAXQ7667 power-supply/supervisory monitoring module supports dedicated supply pins to independently power analog, digital I/O, and digital core functions. The analog functions, digital core, and the digital I/O can be powered from an internal regulator. The MAXQ7667 power-supply/supervisory monitoring module includes the following features: • Dedicated analog supply (+3.3V) pins • Dedicated digital I/O supply (+5.
MAXQ7667 User’s Guide AVDD (+3.3V) ASR.4:AVBI APE.5:VABE AIE.4:AVBIE AVDD BROWNOUT MONITOR INT ASR.13:AVLVL ANALOG MODULE AGND DVDD (+2.5V) ASR.5:VDBI APE.7:VDPE APE.6:VDBE AIE.5:VDBIE DVDD POWER-ON RESET AND BROWNOUT MONITOR INT ASR.14:DVLVL DIGITAL CORE DGND DVDDIO RESET DVDDIO* (+5V) ASR.6:VIBI APE.8:VIBE AIE.6:VIBIE DVDDIO BROWNOUT MONITOR INT ASR.15:VIOLVL GENERAL-PURPOSE I/O DIGITAL DGND REG2P5 (OPTIONAL) 2.5V CAN BE CONNECTED TO DVDD AS POWER SOURCE APE.10:LRDPD 2.
MAXQ7667 User’s Guide 16.2 Power-Supply/Supervisory Monitoring Registers 16.2.
MAXQ7667 User’s Guide 16.2.
MAXQ7667 User’s Guide 16.2.
MAXQ7667 User’s Guide 16.2.4 Watchdog Timer Control Register (WDCN) Watchdog Timer Control Register WDCN Module 08h, Index 0Fh Register Description: Register Name: Register Address: Bit # 7 6 5 4 3 2 1 0 Name POR EWDI WD1 WD0 WDIF WTRF EWT RWT Reset 0 0 0 0 0 0 0 0 Access r rw rw r r r rw rw r = read, w = write Note 1: The watchdog timer always uses the RC oscillator as the clock source. Note 2: Bits 5, 4, 3, and 0 are cleared to 0 on all forms of reset.
MAXQ7667 User’s Guide SUPPLY CONFIGURATION USING ALL EXTERNAL POWER SUPPLY +2.5V DVDD 0.1µF GND DGND +5.0V DVDDIO 0.1µF GND +3.3V AVDD 0.1µF GND AGND REG2P5 REG3P3 GATE5 Figure 16-2. Supply Configuration Using All External Power Supply SUPPLY CONFIGURATION USING AN EXTERNAL POWER SUPPLY AND THE INTERNAL REGULATORS AVDD 0.1µF AGND DVDD 0.1µF DGND +V GND +VIN PASS TRANSISTOR CIRCUITRY DVDDIO 0.1µF 2.5V 3.3V REG2P5 REG3P3 GATE5 Figure 16-3.
MAXQ7667 User’s Guide 16.3.1 5V Regulator with External Pass Transistor The 5V supply (DVDDIO) for the MAXQ7667 can be economically obtained from a higher voltage supply through the use of a few external components. The MAXQ7667 has an internal error amplifier that compares DVDDIO to a fixed voltage reference. The output of the error amplifier can be used to control an external pass transistor and thus create a regulated 5V supply.
MAXQ7667 User’s Guide 16.3.1.2 Darlington Bipolar Transistor as the Pass Device Bipolar transistors may also be used for the pass transistor. In Figure 16-5 a Darlington pair is used to minimize the amount of base current that is required. Pullup resistor R1 is required to start the circuit and as part of the level shifter. All the base current for Q1 comes from R1. R1 must be sized so that it can supply the required base current when VIN is at its minimum and Q1 has the lowest beta.
MAXQ7667 User’s Guide 16.4 Power-On Reset On power-up, the VDPE bit (APE.7) is automatically set to 1, enabling the DVDD reset supervisor; consequently, the internal circuitry pulls the RESET pin low and all the internal system and peripheral registers are reset. As DVDD rises, it crosses the power-on-reset voltage threshold level, which can be between 2.10V and 2.25V, causing the crystal warmup counter to start. The RESET pin is held low until the completion of the counter.
MAXQ7667 User’s Guide 16.4.1 Reset Output The MAXQ7667 asserts the RESET signal during power-up. On power-up, once DVDD exceeds 1V RESET is asserted to be logic-low. As DVDD rises, RESET remains low. When DVDD exceeds the DVDD POR threshold, RESET is kept low until the internal RC oscillator becomes stable and has completed 65,536 cycles. After this period, if DVDD remains above the DVDD POR threshold, RESET goes high. If a brownout reset condition occurs, RESET is asserted low.
MAXQ7667 User’s Guide 16.5.2 Digital I/O Supply (DVDDIO) Monitor The DVDDIO monitor detects a brownout condition on the +5V digital I/O supply. The DVDDIO supply monitor can be independently activated by setting to 1 the VIBE bit in the APE register. A brownout is detected when the DVDDIO supply voltage falls below the programmed DVDDIO brownout detection threshold (see Figure 16-8).
MAXQ7667 User’s Guide 16.6 Reset Mode When the MAXQ7667 is in reset mode, the enabled system clock oscillator continues running, but no instruction execution or other system or peripheral operations occur, and all input/output pins return to default states. Once the condition that caused the reset (whether internal or external) is removed, code execution resumes at address 8000h for all reset types. There are four different sources that can cause the MAXQ7667 to enter reset mode. See Sections 16.4 and 16.
MAXQ7667 User’s Guide SYSTEM CLOCK RESET RESET SAMPLING INTERNAL RESET FIRST INSTRUCTION FETCH Figure 16-10.
MAXQ7667 User’s Guide SECTION 17: ULTRASONIC DISTANCE MEASUREMENT MODULE—BURST TRANSMISSION AND ECHO RECEPTION This section contains the following information: 17.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4 17.1.1 Burst Transmission Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4 17.1.2 Echo Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide 17.5 Echo Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-21 17.5.1 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-21 17.5.1.1 Receiver Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-21 17.5.1.2 Voltage Reference for the Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 17: ULTRASONIC DISTANCE MEASUREMENT MODULE—BURST TRANSMISSION AND ECHO RECEPTION The MAXQ7667 was developed for ultrasonic time-of-flight distance measurement. To accomplish this task several hardware blocks were added to the basic MAXQ. These blocks can be divided into two functioning units: burst transmission and echo reception.
MAXQ7667 User’s Guide 17.1 Architecture 17.1.1 Burst Transmission Stage The MAXQ7667’s burst output excites the transducer when transmitting a burst of ultrasonic sound. The burst output is typically used to switch an external transistor that drives a high voltage transformer, which excites the transducer. The burst signal can be derived from either the system clock or from a programmable oscillator (PLL) that is phase locked to the system clock.
MAXQ7667 User’s Guide The BPF center frequency tracks BFREQ. The bandpass width is 14% of the center frequency (Q = 7). The 16-bit Echo Envelope Bandpass Filter Input Data register (BPFI) and Echo Envelope Bandpass Filter Output Data register (BPFO) data are available in two’s complement format at a data rate equal to 10 x BFREQ. The BPFI and BPFO registers are typically used only for debugging purposes.
MAXQ7667 User’s Guide 17.2 Burst Transmission and Echo Reception Pinouts Table 17-1. Burst Transmission Pinout BURST TRANSMISSION SIGNAL PIN BURST 45 Burst Output. Provides transmit pulses to ultrasonic transducer. Output polarity is programmable. Powers up in three-state mode. FILT 26 Filter pin for burst frequency phase-locked loop (PLL). FUNCTION Table 17-2. Echo Reception Pinout ECHO RECEPTION SIGNAL PIN ECHOP 30 Positive Echo Input. Capacitively coupled from ultrasonic transducer.
MAXQ7667 User’s Guide Bit 14: Burst Drive Strength (BDS). This bit selects the drive strength on the BURST pin. When the BDS bit is set to 0, the output driver is lower; when set to 1, the output driver is higher. Bits 13 to 10: Reserved. Read returns 0. Bits 9 to 0: Burst Pulse-Width High (BPH[9:0]). Defines the number of PLL clock cycles (BCKS = 0), or system clock cycles (BCKS = 1) in each burst high pulse. When BPH is zero or one, the burst pulse-width high is 1 cycle.
MAXQ7667 User’s Guide Bit 11: Burst Polarity Control (BPOL). Setting this bit to 0 causes a low idle state and a high pulse width of BPH. Set BPOL 1 to invert the BURST output, idling high with BPH specifying the low period within the period. Bit 10: Burst Clock Source Select (BCKS). Setting this bit to 0 selects the PLL output as the clock source for burst transmission and for the echo receive path.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.3.
MAXQ7667 User’s Guide 17.4 Burst Signal Generation To facilitate implementation the following items must be addressed: • Hardware Setup: External RC Filter (FILT) Ultrasonic Transducer • Software Setup: Turning On the PLL and the Clock Sections Configuring the Burst Registers Triggering the Burst Signal 17.4.1 Setting Up the Hardware 17.4.1.1 External RC Filter (FILT) An external filter must be connected to the FILT pin if the PLL is used.
MAXQ7667 User’s Guide 17.4.2.2 Configuring the Burst Variables The Clock-Burst-In (Figure 17-1) is selected by the burst clock select bit, BCKS (BTRN.10). The Clock-Burst-In is the clock used to generate the burst frequency (BFREQ) and the Recv-Clock that feeds the echo reception section. If the BCKS bit is set to 1, the system clock is selected; otherwise, if BCKS = 0 the programmable PLL oscillator is selected. The reset state sets BCKS to a 1, selecting the system clock as the default.
MAXQ7667 User’s Guide Table 17-5. Integer Divisor Values BDIV Rdivisor Bdivisor NOMINAL BURST FREQUENCY IF f Clock-Burst-In = 16MHz (kHz) BINARY HEX 0000 00 — 12 1333 0001 01 — 16 1000 0010 02 — 20 800 0011 03 — 28 571 0100 04 — 36 444 0101 05 — 48 333 0110 06 — 64 250 0111 07 — 90 178 1000 08 — 120 133 1001 (default) 09 (default) 2 160 100 1010 0A 3 240 66.7 1011 0B 4 320 50 1100 0C 5 400 40 1101 0D 6 480 33.3 1110 0E 7 560 28.
MAXQ7667 User’s Guide 17.4.2.3 Triggering the Burst Signal Once all the register bits have been set to generate the frequency, duty cycle, and number of pulses, and enable the BURST pin, the burst signal can be transmitted out through the BURST output pin by setting the burst start bit, BSTT (BPH.15) to 1. Once a burst sequence is initiated, the sequence progresses to completion, always producing the exact number of whole pulses specified.
MAXQ7667 User’s Guide 17.5 Echo Reception To facilitate implementation the following items must be addressed: • Hardware Setup: Receiver Clock Frequency Voltage Reference for the Sigma-Delta ADC External Input Coupling Capacitors • Software Setup: Powering Up Receiver Hardware Echo Reception Register Configuration Echo Reception Interrupts 17.5.1 Hardware Setup 17.5.1.1 Receiver Clock Frequency The center frequency of the BPF tracks the burst frequency.
MAXQ7667 User’s Guide 17.5.2.2 Echo Receive Register Configuration The input of echo reception stage can be configured to accept external (echo) signal on the ECHOP and ECHON pins or internally generated diagnostic signals can be added to the echo signal (see Figure 17-2). Selection of the signal is done by setting the LNA input mux select bits, LNAISEL[1:0] (RCVC.7:6). Table 17-6 gives a description for the different settings of the LNAISEL bits. Table 17-6.
MAXQ7667 User’s Guide Table 17-7. Effective Gain for the Echo Reception Stage (continued) ECHO RECEIVE PATH GAIN FROM THE ECHO INPUTS TO THE LOWPASS FILTER OUTPUT (GAIN IS CONTROLLED BY THE VALUE IN RCVGN BIT) RCVGN FULL SCALE (mVP-P) LPFD RESOLUTION (µV P-P/LSB) RCVGN FULL SCALE (mVP-P) LPFD RESOLUTION (µVP-P/LSB) 0b01011 37.35 0.57 0b11011 9.17 0.14 0b01100 34.08 0.52 0b11100 8.52 0.13 0b01101 31.46 0.48 0b11101 7.86 0.12 0b01110 29.49 0.45 0b11110 7.21 0.11 0b01111 27.
MAXQ7667 User’s Guide 17.5.3 Echo Receive Data Register The LPFD register contains the most recent filtered and processed data. Reading LPFD does not clear it. The data in LPFD is updated as soon as a new value is available. The LPFD data is in straight binary format. When a new LPF value is ready, the data ready flag, LPFRDY (ASR.1), is set to 1. If the echo envelope LPF output data ready interrupt enable bit, LPFIE (AIE.2), is set to 1, an interrupt is generated by the LPFRDY flag.
MAXQ7667 User’s Guide SECTION 18: UTILITY ROM This section contains the following information: 18.1 In-Application Programming Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3 18.2 Data Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-4 18.3 ROM Example 1: Calling A MAXQ7667 Utility ROM Function Directly . . . . . . . . . . . . . . . . .18-7 18.
MAXQ7667 User’s Guide SECTION 18: UTILITY ROM The ROM in the MAXQ7667 provides routines for handling the bootloader and application code, the debug engine, and some utility function for the user. The focus of this section is the utility function. The area of the UROM where the utility functions reside is known as the utility ROM.
MAXQ7667 User’s Guide 18.1 In-Application Programming Functions Function: Summary: Inputs: Outputs: Destroys: flashWrite Write a word to the flash block (program memory). A[0]: Word address in main flash block to write to. A[1]: Word value to write to flash block. Carry: Set on error and cleared on success. If set, then A[0] contains one of the following error codes: 1: Failure due to software timeout. 2: Failure reported by hardware (DQ5).
MAXQ7667 User’s Guide Function: Summary: Input: Output: UARTloader* This is an entry point for the customer to call the UART bootloader from their application code. The UART performs an autobaud and if that succeeds, the loader will be launched and this function will never return. If the autobauding fails, the routine returns an error code in A[7]. Clear Password lock before calling (if desired).
MAXQ7667 User’s Guide Function: Summary: Inputs: Outputs: Destroys: moveDP1 Reads the byte/word value pointed to by DP[1]. DP[1]: Address to read from. GR: Data byte/word read. Selects DP[1] in DPC. Notes: 1) Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as explained in Section 2.
MAXQ7667 User’s Guide Function: Summary: Inputs: Outputs: Destroys: moveFPinc Reads the byte/word value pointed to by BP[OFFS] then increments OFFS. BP[OFFS]: Address to read from. GR: Data byte/word read. OFFS is incremented. Selects BP in DPC. Notes: 1) Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode. 2) The address passed to this function should be based on the data memory mapping for the utility ROM, as explained in Section 2.
MAXQ7667 User’s Guide 18.3 ROM Example 1: Calling A MAXQ7667 Utility ROM Function Directly This example shows the direct addressing method for calling MAXQ7667 utility functions, using the function moveDP1inc to read a static string from code space. Note the equate UROM_MOVEDP1INC. UROM_MOVEDP1INC EQU 0857Eh Text: DB “Hello World!”,0 ; Define a string in code space.
MAXQ7667 User’s Guide 18.4 ROM Example 2: Calling A MAXQ7667 Utility ROM Function Indirectly The second example shows the indirect addressing method (lookup table) for calling MAXQ7667 utility functions. We use the same function (UROM_MoveDP1Inc) to read our static string, but this time we must figure out the address we want dynamically. Note the inserted code where we before had a direct call to the function. Also note that the function index of moveDP1inc is 8.
MAXQ7667 User’s Guide SECTION 19: INSTRUCTION SET SUMMARY This section contains the following information: ADD/ADDC src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-5 AND src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-6 AND Acc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide RETI C/RETI NC, RETI Z/RETI NZ, RETI S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-23 RL/RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-25 RR/RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-26 SLA/SLA2/SLA4 . . . . . . . . . . . . . . . . . . . . .
MAXQ7667 User’s Guide SECTION 19: INSTRUCTION SET SUMMARY Table 19-1. MAXQ7667 Instruction Set Summary MATH BIT OPERATIONS LOGICAL OPERATIONS MNEMONIC 19-3 AND src OR src XOR src CPL NEG SLA SLA2 SLA4 RL RLC SRA SRA2 SRA4 SR RR RRC MOVE C, Acc. MOVE C, #0 MOVE C, #1 CPL C MOVE Acc., C AND Acc. OR Acc. XOR Acc. MOVE dst., #1 MOVE dst., #0 MOVE C, src.
MAXQ7667 User’s Guide Table 19-1.
MAXQ7667 User’s Guide ADD/ADDC src Add/Add with Carry Description: The ADD instruction sums the active accumulator (Acc or A[AP]) and the specified src data and stores the result back to the active accumulator. The ADDC instruction additionally includes the Carry (C) Status Flag in the summation. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7667 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
MAXQ7667 User’s Guide AND src Logical AND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7667 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
MAXQ7667 User’s Guide {L/S}CALL src {Long/Short} Call to Subroutine Description: Performs a call to the subroutine destination specified by src. The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words). The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute long CALL. Using the optional 'L' prefix (i.
MAXQ7667 User’s Guide CMP src Compare Accumulator Description: Compare for equality between the active accumulator and the least significant byte of the specified src. The MAXQ7667 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
MAXQ7667 User’s Guide CPL C Complement Carry Flag Description: Logically complements the Carry (C) Flag. Status Flags: C Operation: C ← ~C Encoding: 15 1101 0 1010 Example(s): 0010 1010 ;C=0 ;C←1 CPL C {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Description: The DJNZ LC[n], src instruction performs a conditional branch based upon the associated Loop Counter (LC[n]) register.
MAXQ7667 User’s Guide {L/S}JUMP src Unconditional {Long/Short} Jump Description: Performs an unconditional jump as determined by the src specifier. The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words). The JUMP instruction uses a 16-bit immediate src to perform an absolute JUMP to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute JUMP. Using the optional 'L' prefix (i.e.
MAXQ7667 User’s Guide Conditional {Long/Short} Jump on Status Flag {L/S}JUMP C/{L/S}JUMP NC, src, L/S}JUMP Z/{L/S}JUMP NZ, src, {{L/S}JUMP E/{L/S}JUMP NE, src, {L/S}JUMP S, src Description: Performs conditional branching based upon the state of a specific processor status flag. JUMP C results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear. JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear.
MAXQ7667 User’s Guide JUMP NZ Z=0: IP ← IP + src (relative) -or- src (absolute) Operation: Z=1: IP ← IP + 1 Encoding: 15 0 f101 1100 ssss ssss Example(s): JUMP NZ, label1 JUMP E E=1: IP ← IP + src (relative) -or- src (absolute) Operation: E=0: IP ← IP + 1 Encoding: 15 ; Z=1, branch taken 0 0011 1100 ssss ssss Example(s): JUMP E, label1 Special Notes: The src specifier must be immediate data.
MAXQ7667 User’s Guide MOVE dst, src Move Data Description: Moves data from a specified source (src) to a specified destination (dst). A list of defined source, destination specifiers is given in the table below. Also, since src can be either 8-bit (byte) or 16-bit (word) data, the rules governing data transfer are also explained below in the encoding section.
MAXQ7667 User’s Guide MOVE dst, src Move Data Table 19-3. Destination Specifier Codes dst dst BIT ENCODING (ddd dddd) WIDTH (16 OR 8) NUL 111 0110 8/16 Null (Virtual) Destination. Intended as a bit bucket to assist software with pointer increments/decrements. MN[n] nnn 0NNN 8/16 nnnn Selects One of First 8 Registers in Module NNN; where NNN = 0 to 5. Access to Next 24 Using PFX[n].
MAXQ7667 User’s Guide Example(s): MOVE A[0], A[3] MOVE DP[0], #110h ; A[0] ← A[3] ; DP[0] ← #0110h (PFX[0] register used) ; MOVE PFX[0], #01h (smart-prefixing) ; MOVE DP[0], #10h MOVE DP[0], #80h Special Notes: ; DP[0] ← #0080h (PFX[0] register not needed) Proper loading of the PFX[n] registers, when for the purpose of supplying 16-bit immediate data or accessing 2-cycle destinations, is handled automatically by the assembler and is therefore an optional step for the user when writing assembly source
MAXQ7667 User’s Guide MOVE C, Acc. Move Accumulator Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified active accumulator bit. Status Flags: C Operation: C ← Acc. Encoding: 15 0 1110 1010 bbbb Example(s): 1010 ; Acc = 01C0h, C=0 MOVE C, Acc.8 ; C =1 MOVE C, src. Move Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified source bit src.. Status Flags: C Operation: C ← src.
MAXQ7667 User’s Guide MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag. Status Flag: C←1 Operation: C←1 Encoding: 15 1101 0 1010 0001 Example(s): 1010 ;C=0 ;C←1 MOVE C, #1 MOVE dst., #0 Clear Bit Description: Clears the bit specified by dst.. Status Flags: C, E (if dst is PSF), S, Z Operation: dst. ← 0 Encoding: 15 1ddd 0 dddd 0bbb Example(s): Special Notes: 0111 ; M0[0] = FEh MOVE M0[0].1, #0 ; M0[0] = FCh MOVE M0[0].
MAXQ7667 User’s Guide NEG Negate Accumulator Description: Performs a negation (two’s complement) of the active accumulator and returns the result back to the active accumulator. Status Flags: S, Z Operation: Acc ← ~Acc + 1 Encoding: 15 0 1000 1010 1001 Example(s): 1010 ; Acc = FEEDh, S=1, Z=0 NEG ; Acc = 0113h, S=0, Z=0 OR src Logical OR Description: Performs a logical-OR between the active accumulator (Acc or A[AP]) and the specified src data.
MAXQ7667 User’s Guide OR Acc. Logical OR Carry Flag with Accumulator Bit Description: Performs a logical-OR between the Carry (C) status flag and a specified bit of the active accumulator (Acc.) and returns the result to the Carry. Status Flags: C Operation: C ← C OR Acc. Encoding: 15 1010 0 1010 bbbb Example(s): 1010 ; Acc = 2345h, C=0 at start OR Acc.1 ; Acc.1=0 → C=0 OR Acc.2 ; Acc.
MAXQ7667 User’s Guide POPI dst Pop Word from the Stack Enable Interrupts Description: Pops a single word from the stack (@SP) to the specified dst and decrements the stack pointer (SP). Additionally, POPI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
MAXQ7667 User’s Guide RET Return from Subroutine Description: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). The decremented SP is saved as the new stack pointer (SP).
MAXQ7667 User’s Guide RET NC Operation: C=0: IP ← @SP-C=1: IP ← IP +1 Encoding: 15 0 1110 Example(s): 1100 0000 RET NC 1101 ; C=1, return (RET) does not occur RET Z Operation: Z=1: IP ← @SP-Z=0: IP ← IP + 1 Encoding: 15 0 1001 Example(s): 1100 0000 RET Z 1101 ; Z=0, return (RET) does not occur RET NZ Operation: Z=0: IP ← @SP-Z=1: IP ← IP +1 Encoding: 15 0 1101 Example(s): 1100 0000 RET NZ 1101 ; Z=0, return (RET) is performed RET S Operation: S=1: IP ← @SP-- Encoding:
MAXQ7667 User’s Guide RETI Return from Interrupt Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). Additionally, RETI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
MAXQ7667 User’s Guide RETI Z Operation: Z=1: IP ← @SP-INS ← 0 Z=0: IP ← IP + 1 Encoding: 15 0 1001 Example(s): 1100 1000 RETI Z 1101 ; Z=0, return from interrupt (RETI) does not occur RETI NZ Operation: Z=0: IP ← @SP-INS ← 0 Z=1: IP ← IP +1 Encoding: 15 0 1101 Example(s): 1100 1000 RETI NZ 1101 ; Z=0, return from interrupt (RETI) is performed RETI S Operation: S=1: IP ← @SP-INS ← 0 S=0: IP ← IP + 1 Encoding: 15 0 1100 Example(s): RETI S 1100 1000 1101 ; S=0, return from i
MAXQ7667 User’s Guide RL/RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msb of the accumulator (bit 15) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 15 Active Accumulator (Acc) 0 Acc.[15:1]← Acc.[14:0]; Acc.0 ← Acc.
MAXQ7667 User’s Guide RR/RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsb of the accumulator (bit 0) back to the msb (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: 15 Active Accumulator (Acc) 0 Acc.[14:0]← Acc.[15:1]; Acc.15 ← Acc.
MAXQ7667 User’s Guide SLA/SLA2/SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iteration, a 0 is shifted into the lsb, and the msb is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
MAXQ7667 User’s Guide SR/SRA/SRA2/SRA4 Shift Accumulator Right/ Shift Accumulator Right Arithmetically One, Two, or Four Times Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times, respectively, for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msb while the SRA, SRA2, and SRA4 instructions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation.
MAXQ7667 User’s Guide SRA2 Operation: 15 Active Accumulator (Acc) 0 Carry Flag 0 Carry Flag Acc.[13:0] ← Acc.[15:2] Acc.[15:14] ← Acc.15 C ← Acc.1 Encoding: 15 1000 0 1010 1110 1010 Example(s): ; Acc = 0003h, C=0, Z=0 SRA2 SRA4 Operation: ; Acc = 0000h, C=1, Z=1 15 Active Accumulator (Acc) Acc.[11:0] ← Acc.[15:4] Acc.[15:12] ← Acc.15 C ← Acc.
MAXQ7667 User’s Guide SUB/SUBB src Subtract/Subtract with Borrow Description: Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumulator. The SUBB additionally subtracts the borrow (Carry Flag), which may have resulted from previous subtraction. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7667 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
MAXQ7667 User’s Guide XCH Exchange Accumulator Bytes Description: Exchanges the upper and lower bytes of the active accumulator. Status Flags: S Operation: Acc.[15:8] ← Acc.[7:0] Encoding: 15 Acc.[7:0] ← Acc.[15:8] 1000 0 1010 1000 1010 Example(s): ; Acc = 2345h XCHN ; Acc = 4523h XCHN Exchange Accumulator Nibbles Description: Exchanges the upper and lower nibbles in the active accumulator byte(s). Status Flags: S Operation: Acc.[7:4] ← Acc.[3:0] Acc.[3:0] ← Acc.[7:4] Acc.
MAXQ7667 User’s Guide XOR src Logical XOR Description: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. The MAXQ7667 may use the PFX[n] register to supply the high byte of data for 8-bit sources.
MAXQ7667 User’s Guide REVISION HISTORY REVISION NUMBER REVISION DATE SECTION NUMBER 0 4/09 — DESCRIPTION Initial release. PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
