Datasheet

secondary turns ratio plus an external on-board full bridge rectifier.
The MAX14850 (U3) accomplishes data isolation. On the Pmod side, the voltage supply can be 3.3V or 5V. (The Pmod power
output for both the Nexys 3 and ZedBoard platforms is fixed at 3.3V.) On the MAX31911 side, the voltage supply is 5V. The
combined power and data isolation achieved is 600V
RMS
.
To use the on-board isolation circuits, move the shunt on jumper JU1 to the 1–2 position and apply 7.6V to 36V DC supply on
terminals TP3 and TP4. If the on-board isolation circuit is not required, move the shunt on jumper JU1 to the 2-3 position and apply
7V to 36V DC supply on terminals TP1 and TP2. See Table 1 for the jumper settings and the input current requirements.
Detailed Description of Firmware for Nexys 3 Platform
The Corona firmware design was developed and tested for the Nexys 3 development kit. The design targets a MicroBlaze
™
soft
core microcontroller placed inside a Xilinx
®
Spartan-6 FPGA. The FPGA project files for the Nexys 3 platform are located under
Firmware Files in the All Design Files section.
The firmware is a working example of how to initiate the system and continuously read and display the MAX31911 register values.
The simple process flow is shown in Figure 2. The firmware is written in C using the Xilinx SDK tool, which is based on the
Eclipse
™
open source standard. Custom Corona-specific design functions were created utilizing the standard Xilinx XSpi core
version 3.03a. The SPI clock frequency is set to 3.125MHz.
Figure 2. The Corona firmware flowchart for Nexys 3 platform.
The complete source code is provided to speed up customer development. Code documentation can be found with the
corresponding firmware platform files.
Detailed Description of Firmware for ZedBoard Platform
The Corona firmware design is also developed and tested for the ZedBoard kit. The design targets an ARM
®
Cortex
®
-A9 processor
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