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Maxim > Design Support > Technical Documents > Subsystem Boards > APP 5822

Keywords: Alcatraz (MAXREFDES34), subsystem reference design, FPGA security, SHA-256

authentication, IP protection

SUBSYSTEM BOARD 5822

Alcatraz (MAXREFDES34#): SHA-256 Secure

Authentication Design

By:

Michael

D'Onofrio

Feb 12, 2014

Abstract:

The Alcatraz (MAXREFDES34#) subsystem provides a reference design for securing Xilinx

FPGAs to protect IP and prevent attached peripheral counterfeiting. The system implements a SHA-256

challenge-response between the FPGA and a DS28E15 secure authenticator. Boards for purchase,

hardware, and firmware design files provide complete system information for rapid prototyping and

development.

Introduction

Smart factories, industrial and

medical applications employ the

flexibility and high performance of

modern FPGAs. As these systems

become increasingly connected,

security emerges as a paramount

feature to protect IP, enable

system features using software

and prevent counterfeiting. The

Alcatraz (MAXREFDES34#)

subsystem reference design uses

the DS28E15 to immediately

implement SHA-256 authentication on Xilinx

FPGAs. The DS28E15 communicates over the single-

contact 1-Wire

bus, reducing the number of pins necessary to carry out the solution. The reference code

defines a combined SHA-256 processor and 1-Wire Master on the host FPGA.

Page 1 of 6

Summary of content (6 pages)

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Maxim > Design Support > Technical Documents > Subsystem Boards > APP 5822 Keywords: Alcatraz (MAXREFDES34), subsystem reference design, FPGA security, SHA-256 authentication, IP protection SUBSYSTEM BOARD 5822 Alcatraz (MAXREFDES34#): SHA-256 Secure Authentication Design Michael D'Onofrio Feb 12, 2014 By: Abstract: The Alcatraz (MAXREFDES34#) subsystem provides a reference design for securing Xilinx FPGAs to protect IP and prevent attached peripheral counterfeiting.
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Figure 1. The Alcatraz subsystem design block diagram with development platform.
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Figure 2. The Alcatraz subsystem design correctly inserted into the MicroZed development platform. Table 1 shows the supported platforms and ports. Table 1. Supported Platforms and Ports Supported Platforms Ports LX9™ 3 platform (Spartan®-6) J5 MicroZed™ platform (Zynq®-7000) J5 For symmetric authentication schemes like SHA-256, protection of both the secure authenticator secret key, along with the FPGA secret key, are important.
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FPGA secret key security can be risky. To this end, the DS28E15 uses DeepCover technology to protect against invasive and noninvasive attacks on its secret key; the reference design spells out various techniques to protect the FPGA secret key. Additional detail on secret key protection techniques may be found in application note 5803, "Secure Your FPGA System Using a DeepCover Secure Authenticator." Detailed Description of Firmware for LX9 Platform Table 1 shows currently supported platforms and ports.
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Hardware Files Schematic Bill of materials (BOM) PCB layout PCB Gerber Firmware Files The associated firmware files LX9 Platform (Spartan-6) and ZedBoard Platform (Zynq-7000) are available upon request. Please contact us. Buy Reference Design Buy Direct: Alcatraz (MAXREFDES34#) Or Order the Alcatraz reference design (MAXREFDES34#) from your local Maxim representative. 1-Wire is a registered trademark of Maxim Integrated Products, Inc.
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For Samples: http://www.maximintegrated.com/samples Other Questions and Comments: http://www.maximintegrated.com/contact Application Note 5822: http://www.maximintegrated.com/an5822 SUBSYSTEM BOARD 5822, AN5822, AN 5822, APP5822, Appnote5822, Appnote 5822 © 2013 Maxim Integrated Products, Inc. Additional Legal Notices: http://www.maximintegrated.